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ARM: PCI: Remove the IXP PCI driver
The driver is no longer used, remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michael Schwingen <michael@schwingen.org> Cc: Tom Rini <trini@ti.com>
This commit is contained in:
Marek Vasut
parent
b1c756782c
commit
c75692d362
3 changed files with 0 additions and 356 deletions
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@ -125,10 +125,6 @@ III) Analysis of in-tree drivers
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Shared driver for indirect PCI bridges, several CONFIG macros - will
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require significant cleanup.
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pci_ixp.c
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---------
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Standard driver, specifies all read/write functions separately.
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pci_sh4.c
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---------
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Shared init function for SH4 drivers, uses dword for read/write ops.
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@ -11,7 +11,6 @@ obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
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obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
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obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
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obj-$(CONFIG_FTPCI100) += pci_ftpci100.o
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obj-$(CONFIG_IXP_PCI) += pci_ixp.o
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obj-$(CONFIG_SH4_PCI) += pci_sh4.o
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obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
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obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
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@ -1,351 +0,0 @@
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/*
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* IXP PCI Init
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*
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* (C) Copyright 2011
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* Michael Schwingen, michael@schwingen.org
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* (C) Copyright 2004 eslab.whut.edu.cn
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* Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <pci.h>
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#include <asm/arch/ixp425.h>
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#include <asm/arch/ixp425pci.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void non_prefetch_read(unsigned int addr, unsigned int cmd,
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unsigned int *data);
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static void non_prefetch_write(unsigned int addr, unsigned int cmd,
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unsigned int data);
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/*define the sub vendor and subsystem to be used */
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#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
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#define PCI_MEMORY_BUS 0x00000000
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#define PCI_MEMORY_PHY 0x00000000
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#define PCI_MEMORY_SIZE 0x04000000
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#define PCI_MEM_BUS 0x48000000
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#define PCI_MEM_PHY 0x00000000
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#define PCI_MEM_SIZE 0x04000000
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#define PCI_IO_BUS 0x00000000
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#define PCI_IO_PHY 0x00000000
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#define PCI_IO_SIZE 0x00010000
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/* build address value for config sycle */
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static unsigned int pci_config_addr(pci_dev_t bdf, unsigned int reg)
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{
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unsigned int bus = PCI_BUS(bdf);
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unsigned int dev = PCI_DEV(bdf);
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unsigned int func = PCI_FUNC(bdf);
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unsigned int addr;
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if (bus) { /* secondary bus, use type 1 config cycle */
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addr = bdf | (reg & ~3) | 1;
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} else {
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/*
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primary bus, type 0 config cycle. address bits 31:28
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specify the device 10:8 specify the function
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*/
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addr = BIT((31 - dev)) | (func << 8) | (reg & ~3);
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}
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return addr;
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}
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static int pci_config_status(void)
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{
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unsigned int regval;
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regval = readl(PCI_CSR_BASE + PCI_ISR_OFFSET);
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if ((regval & PCI_ISR_PFE) == 0)
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return OK;
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/* no device present, make sure that the master abort bit is reset */
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writel(PCI_ISR_PFE, PCI_CSR_BASE + PCI_ISR_OFFSET);
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return ERROR;
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}
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static int pci_ixp_hose_read_config_dword(struct pci_controller *hose,
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pci_dev_t bdf, int where, unsigned int *val)
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{
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unsigned int retval;
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unsigned int addr;
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int stat;
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debug("pci_ixp_hose_read_config_dword: bdf %x, reg %x", bdf, where);
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/*Set the address to be read */
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addr = pci_config_addr(bdf, where);
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non_prefetch_read(addr, NP_CMD_CONFIGREAD, &retval);
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*val = retval;
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stat = pci_config_status();
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if (stat < 0)
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*val = -1;
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debug("-> val %x, status %x\n", *val, stat);
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return stat;
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}
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static int pci_ixp_hose_read_config_word(struct pci_controller *hose,
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pci_dev_t bdf, int where, unsigned short *val)
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{
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unsigned int n;
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unsigned int retval;
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unsigned int addr;
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unsigned int byteEnables;
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int stat;
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debug("pci_ixp_hose_read_config_word: bdf %x, reg %x", bdf, where);
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n = where % 4;
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/*byte enables are 4 bits active low, the position of each
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bit maps to the byte that it enables */
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byteEnables =
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(~(BIT(n) | BIT((n + 1)))) &
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IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
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byteEnables = byteEnables << PCI_NP_CBE_BESL;
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/*Set the address to be read */
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addr = pci_config_addr(bdf, where);
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non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
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/*Pick out the word we are interested in */
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*val = retval >> (8 * n);
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stat = pci_config_status();
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if (stat < 0)
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*val = -1;
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debug("-> val %x, status %x\n", *val, stat);
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return stat;
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}
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static int pci_ixp_hose_read_config_byte(struct pci_controller *hose,
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pci_dev_t bdf, int where, unsigned char *val)
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{
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unsigned int retval;
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unsigned int n;
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unsigned int byteEnables;
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unsigned int addr;
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int stat;
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debug("pci_ixp_hose_read_config_byte: bdf %x, reg %x", bdf, where);
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n = where % 4;
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/*byte enables are 4 bits, active low, the position of each
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bit maps to the byte that it enables */
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byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
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byteEnables = byteEnables << PCI_NP_CBE_BESL;
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/*Set the address to be read */
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addr = pci_config_addr(bdf, where);
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non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
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/*Pick out the byte we are interested in */
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*val = retval >> (8 * n);
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stat = pci_config_status();
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if (stat < 0)
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*val = -1;
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debug("-> val %x, status %x\n", *val, stat);
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return stat;
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}
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static int pci_ixp_hose_write_config_byte(struct pci_controller *hose,
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pci_dev_t bdf, int where, unsigned char val)
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{
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unsigned int addr;
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unsigned int byteEnables;
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unsigned int n;
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unsigned int ldata;
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int stat;
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debug("pci_ixp_hose_write_config_byte: bdf %x, reg %x, val %x",
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bdf, where, val);
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n = where % 4;
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/*byte enables are 4 bits active low, the position of each
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bit maps to the byte that it enables */
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byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
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byteEnables = byteEnables << PCI_NP_CBE_BESL;
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ldata = val << (8 * n);
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/*Set the address to be written */
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addr = pci_config_addr(bdf, where);
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non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
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stat = pci_config_status();
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debug("-> status %x\n", stat);
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return stat;
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}
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static int pci_ixp_hose_write_config_word(struct pci_controller *hose,
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pci_dev_t bdf, int where, unsigned short val)
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{
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unsigned int addr;
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unsigned int byteEnables;
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unsigned int n;
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unsigned int ldata;
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int stat;
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debug("pci_ixp_hose_write_config_word: bdf %x, reg %x, val %x",
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bdf, where, val);
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n = where % 4;
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/*byte enables are 4 bits active low, the position of each
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bit maps to the byte that it enables */
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byteEnables =
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(~(BIT(n) | BIT((n + 1)))) &
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IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
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byteEnables = byteEnables << PCI_NP_CBE_BESL;
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ldata = val << (8 * n);
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/*Set the address to be written */
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addr = pci_config_addr(bdf, where);
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non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
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stat = pci_config_status();
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debug("-> status %x\n", stat);
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return stat;
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}
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static int pci_ixp_hose_write_config_dword(struct pci_controller *hose,
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pci_dev_t bdf, int where, unsigned int val)
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{
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unsigned int addr;
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int stat;
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debug("pci_ixp_hose_write_config_dword: bdf %x, reg %x, val %x",
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bdf, where, val);
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/*Set the address to be written */
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addr = pci_config_addr(bdf, where);
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non_prefetch_write(addr, NP_CMD_CONFIGWRITE, val);
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stat = pci_config_status();
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debug("-> status %x\n", stat);
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return stat;
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}
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static void non_prefetch_read(unsigned int addr,
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unsigned int cmd, unsigned int *data)
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{
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writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET);
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/*set up and execute the read */
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writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET);
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/*The result of the read is now in np_rdata */
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*data = readl(PCI_CSR_BASE + PCI_NP_RDATA_OFFSET);
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return;
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}
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static void non_prefetch_write(unsigned int addr,
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unsigned int cmd, unsigned int data)
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{
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writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET);
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/*set up the write */
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writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET);
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/*Execute the write by writing to NP_WDATA */
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writel(data, PCI_CSR_BASE + PCI_NP_WDATA_OFFSET);
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return;
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}
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static void crp_write(unsigned int offset, unsigned int data)
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{
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/*
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* The CRP address register bit 16 indicates that we want to do a
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* write
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*/
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writel(PCI_CRP_WRITE | offset, PCI_CSR_BASE + PCI_CRP_AD_CBE_OFFSET);
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writel(data, PCI_CSR_BASE + PCI_CRP_WDATA_OFFSET);
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}
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void pci_ixp_init(struct pci_controller *hose)
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{
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unsigned int csr;
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/*
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* Specify that the AHB bus is operating in big endian mode. Set up
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* byte lane swapping between little-endian PCI and the big-endian
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* AHB bus
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*/
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#ifdef __ARMEB__
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csr = PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
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#else
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csr = PCI_CSR_ABE;
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#endif
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writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET);
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writel(0, PCI_CSR_BASE + PCI_INTEN_OFFSET);
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/*
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* We configure the PCI inbound memory windows to be
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* 1:1 mapped to SDRAM
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*/
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crp_write(PCI_CFG_BASE_ADDRESS_0, 0x00000000);
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crp_write(PCI_CFG_BASE_ADDRESS_1, 0x01000000);
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crp_write(PCI_CFG_BASE_ADDRESS_2, 0x02000000);
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crp_write(PCI_CFG_BASE_ADDRESS_3, 0x03000000);
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/*
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* Enable CSR window at 64 MiB to allow PCI masters
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* to continue prefetching past 64 MiB boundary.
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*/
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crp_write(PCI_CFG_BASE_ADDRESS_4, 0x04000000);
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/*
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* Enable the IO window to be way up high, at 0xfffffc00
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*/
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crp_write(PCI_CFG_BASE_ADDRESS_5, 0xfffffc01);
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/*Setup PCI-AHB and AHB-PCI address mappings */
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writel(0x00010203, PCI_CSR_BASE + PCI_AHBMEMBASE_OFFSET);
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writel(0x00000000, PCI_CSR_BASE + PCI_AHBIOBASE_OFFSET);
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writel(0x48494a4b, PCI_CSR_BASE + PCI_PCIMEMBASE_OFFSET);
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crp_write(PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM);
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crp_write(PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME);
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udelay(1000);
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/* clear error bits in status register */
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writel(PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE,
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PCI_CSR_BASE + PCI_ISR_OFFSET);
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/*
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* Set Initialize Complete in PCI Control Register: allow IXP4XX to
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* respond to PCI configuration cycles.
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*/
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csr |= PCI_CSR_IC;
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writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET);
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hose->first_busno = 0;
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hose->last_busno = 0;
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/* System memory space */
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pci_set_region(hose->regions + 0,
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PCI_MEMORY_BUS,
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PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY);
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/* PCI memory space */
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pci_set_region(hose->regions + 1,
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PCI_MEM_BUS,
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PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM);
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/* PCI I/O space */
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pci_set_region(hose->regions + 2,
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PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO);
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hose->region_count = 3;
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pci_set_ops(hose,
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pci_ixp_hose_read_config_byte,
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pci_ixp_hose_read_config_word,
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pci_ixp_hose_read_config_dword,
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pci_ixp_hose_write_config_byte,
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pci_ixp_hose_write_config_word,
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pci_ixp_hose_write_config_dword);
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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}
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