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https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
ipu_common: Let the MX6 IPU clock be calculated in run-time
MX6Q/QP IPU operates at 264MHz and MX6DL IPU at 198MHz. When running a SPL target, which supports multiple MX6 variants we cannot properly setup the IPU clock frequency via CONFIG_IPUV3_CLK option as such decision is done in build-time currently. Remove the CONFIG_IPUV3_CLK option and let the IPU clock frequency be configured in run-time on mx6. Reported-by: Eric Nelson <eric@nelint.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com> Reviewed-by: Stefano Babic <sbabic@denx.de> [agust: fixed #endif in cgtqmx6eval.h] Signed-off-by: Anatolij Gustschin <agust@denx.de>
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584f316f11
commit
c7430d7d5e
22 changed files with 13 additions and 30 deletions
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@ -19,6 +19,7 @@
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#include <linux/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/sys_proto.h>
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#include <div64.h>
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#include "ipu.h"
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#include "ipu_regs.h"
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@ -81,6 +82,11 @@ struct ipu_ch_param {
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#define IPU_SW_RST_TOUT_USEC (10000)
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#define IPUV3_CLK_MX51 133000000
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#define IPUV3_CLK_MX53 200000000
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#define IPUV3_CLK_MX6Q 264000000
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#define IPUV3_CLK_MX6DL 198000000
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void clk_enable(struct clk *clk)
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{
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if (clk) {
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@ -196,7 +202,6 @@ static void clk_ipu_disable(struct clk *clk)
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static struct clk ipu_clk = {
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.name = "ipu_clk",
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.rate = CONFIG_IPUV3_CLK,
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#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
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.enable_reg = (u32 *)(CCM_BASE_ADDR +
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offsetof(struct mxc_ccm_reg, CCGR5)),
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@ -476,6 +481,13 @@ int ipu_probe(void)
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g_pixel_clk[1] = &pixel_clk[1];
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g_ipu_clk = &ipu_clk;
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#if defined(CONFIG_MX51)
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g_ipu_clk->rate = IPUV3_CLK_MX51;
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#elif defined(CONFIG_MX53)
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g_ipu_clk->rate = IPUV3_CLK_MX53;
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#else
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g_ipu_clk->rate = is_mx6sdl() ? IPUV3_CLK_MX6DL : IPUV3_CLK_MX6Q;
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#endif
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debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
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g_ldb_clk = &ldb_clk;
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debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
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@ -253,7 +253,6 @@
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_IPUV3_CLK 260000000
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#define CONFIG_IMX_HDMI
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#define CONFIG_IMX_VIDEO_SKIP
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#endif
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@ -117,7 +117,6 @@
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_IPUV3_CLK 260000000
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#define CONFIG_CONSOLE_MUX
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#define CONFIG_IMX_HDMI
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#define CONFIG_IMX_VIDEO_SKIP
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@ -214,7 +214,6 @@
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_IPUV3_CLK 198000000
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#define CONFIG_IMX_VIDEO_SKIP
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#define CONFIG_PWM_IMX
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@ -78,11 +78,6 @@
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#ifdef CONFIG_MX6DL
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#define CONFIG_IPUV3_CLK 198000000
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#else
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#define CONFIG_IPUV3_CLK 264000000
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#endif
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#define CONFIG_IMX_HDMI
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/* SATA */
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@ -236,7 +236,6 @@
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/* Display */
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#define CONFIG_VIDEO_IPUV3
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#define CONFIG_IPUV3_CLK 260000000
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#define CONFIG_IMX_HDMI
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#define CONFIG_SPLASH_SCREEN
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@ -103,7 +103,6 @@
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_IPUV3_CLK 260000000
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#define CONFIG_CONSOLE_MUX
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#define CONFIG_IMX_HDMI
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#define CONFIG_IMX_VIDEO_SKIP
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@ -108,7 +108,6 @@
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_IPUV3_CLK 260000000
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#define CONFIG_IMX_HDMI
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#define CONFIG_IMX_VIDEO_SKIP
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@ -277,7 +277,6 @@
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_IPUV3_CLK 260000000
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#define CONFIG_IMX_HDMI
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#define CONFIG_IMX_VIDEO_SKIP
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#endif
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@ -156,7 +156,6 @@
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/* Framebuffer and LCD */
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#define CONFIG_VIDEO_IPUV3
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_IPUV3_CLK 260000000
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#define CONFIG_IMX_HDMI
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#define CONFIG_IMX_VIDEO_SKIP
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#define CONFIG_VIDEO_BMP_LOGO
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@ -199,7 +199,6 @@
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/* Framebuffer */
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#ifdef CONFIG_VIDEO_IPUV3
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# define CONFIG_IPUV3_CLK 260000000
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# define CONFIG_IMX_VIDEO_SKIP
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# define CONFIG_SPLASH_SCREEN
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@ -172,7 +172,6 @@
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
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#define CONFIG_IPUV3_CLK 200000000
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#endif
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/*
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@ -84,7 +84,6 @@
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_IPUV3_CLK 133000000
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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@ -179,6 +179,5 @@
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_IPUV3_CLK 200000000
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#endif /* __CONFIG_H */
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@ -197,6 +197,5 @@
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_IPUV3_CLK 200000000
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#endif /* __CONFIG_H */
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@ -41,7 +41,6 @@
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/* Framebuffer */
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#define CONFIG_VIDEO_IPUV3
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#define CONFIG_IPUV3_CLK 260000000
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_SPLASH_SCREEN_ALIGN
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@ -205,11 +205,6 @@
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#ifdef CONFIG_MX6DL
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#define CONFIG_IPUV3_CLK 198000000
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#else
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#define CONFIG_IPUV3_CLK 264000000
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#endif
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#define CONFIG_IMX_HDMI
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#define CONFIG_IMX_VIDEO_SKIP
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@ -80,7 +80,6 @@
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#define CONFIG_VIDEO_BMP_GZIP
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#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024)
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#define CONFIG_BMP_16BPP
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#define CONFIG_IPUV3_CLK 260000000
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#define CONFIG_IMX_HDMI
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#define CONFIG_IMX_VIDEO_SKIP
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@ -141,7 +141,6 @@
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_IPUV3_CLK 260000000
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#define CONFIG_IMX_HDMI
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#define CONFIG_IMX_VIDEO_SKIP
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#endif
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@ -64,7 +64,6 @@
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/* Framebuffer */
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#ifdef CONFIG_VIDEO
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#define CONFIG_VIDEO_IPUV3
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#define CONFIG_IPUV3_CLK 260000000
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_IMX_HDMI
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#define CONFIG_IMX_VIDEO_SKIP
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@ -71,7 +71,6 @@
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_IPUV3_CLK 260000000
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#define CONFIG_IMX_HDMI
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#define CONFIG_IMX_VIDEO_SKIP
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#endif
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@ -1119,7 +1119,6 @@ CONFIG_IPAM390_GPIO_BOOTMODE
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CONFIG_IPAM390_GPIO_LED_GREEN
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CONFIG_IPAM390_GPIO_LED_RED
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CONFIG_IPROC
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CONFIG_IPUV3_CLK
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CONFIG_IP_DEFRAG
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CONFIG_IRAM_BASE
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CONFIG_IRAM_END
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