mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-21 07:01:57 +00:00
Merge branch 'master' of git://www.denx.de/git/u-boot-marvell
This commit is contained in:
commit
c733c18e35
12 changed files with 39 additions and 43 deletions
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@ -452,8 +452,15 @@ int arch_cpu_init(void)
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u32 mvebu_get_nand_clock(void)
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u32 mvebu_get_nand_clock(void)
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{
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{
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u32 reg;
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if (mvebu_soc_family() == MVEBU_SOC_A38X)
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reg = MVEBU_DFX_DIV_CLK_CTRL(1);
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else
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reg = MVEBU_CORE_DIV_CLK_CTRL(1);
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return CONFIG_SYS_MVEBU_PLL_CLOCK /
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return CONFIG_SYS_MVEBU_PLL_CLOCK /
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((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) &
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((readl(reg) &
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NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
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NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
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}
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}
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@ -73,6 +73,7 @@
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#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
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#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
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#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
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#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
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#define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
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#define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
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#define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000))
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#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
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#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
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#define MBUS_ERR_PROP_EN (1 << 8)
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#define MBUS_ERR_PROP_EN (1 << 8)
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@ -92,6 +93,7 @@
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#define SPI_PUP_EN BIT(5)
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#define SPI_PUP_EN BIT(5)
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#define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8))
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#define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8))
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#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
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#define NAND_ECC_DIVCKL_RATIO_OFFS 8
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#define NAND_ECC_DIVCKL_RATIO_OFFS 8
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#define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
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#define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
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@ -184,7 +184,7 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8 count)
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DEBUG_INIT_S("PCIe, Idx ");
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DEBUG_INIT_S("PCIe, Idx ");
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DEBUG_INIT_D(pex_idx, 1);
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DEBUG_INIT_D(pex_idx, 1);
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DEBUG_INIT_S
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DEBUG_INIT_S
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(": Link upgraded to Gen2 based on client cpabilities\n");
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(": Link upgraded to Gen2 based on client capabilities\n");
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}
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}
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/* Update pex DEVICE ID */
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/* Update pex DEVICE ID */
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@ -835,25 +835,26 @@ u32 hws_serdes_topology_verify(enum serdes_type serdes_type, u32 serdes_id,
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}
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}
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} else {
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} else {
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test_result = SERDES_ALREADY_IN_USE;
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test_result = SERDES_ALREADY_IN_USE;
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if (test_result == SERDES_ALREADY_IN_USE) {
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}
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printf("%s: Error: serdes lane %d is configured to type %s: type already in use\n",
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__func__, serdes_id,
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if (test_result == SERDES_ALREADY_IN_USE) {
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serdes_type_to_string[serdes_type]);
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printf("%s: Error: serdes lane %d is configured to type %s: type already in use\n",
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return MV_FAIL;
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__func__, serdes_id,
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} else if (test_result == WRONG_NUMBER_OF_UNITS) {
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serdes_type_to_string[serdes_type]);
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printf("%s: Warning: serdes lane %d is set to type %s.\n",
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return MV_FAIL;
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__func__, serdes_id,
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} else if (test_result == WRONG_NUMBER_OF_UNITS) {
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serdes_type_to_string[serdes_type]);
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printf("%s: Warning: serdes lane %d is set to type %s.\n",
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printf("%s: Maximum supported lanes are already set to this type (limit = %d)\n",
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__func__, serdes_id,
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__func__, serd_max_num);
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serdes_type_to_string[serdes_type]);
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return MV_FAIL;
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printf("%s: Maximum supported lanes are already set to this type (limit = %d)\n",
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} else if (test_result == UNIT_NUMBER_VIOLATION) {
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__func__, serd_max_num);
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printf("%s: Warning: serdes lane %d type is %s: current device support only %d units of this type.\n",
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return MV_FAIL;
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__func__, serdes_id,
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} else if (test_result == UNIT_NUMBER_VIOLATION) {
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serdes_type_to_string[serdes_type],
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printf("%s: Warning: serdes lane %d type is %s: current device support only %d units of this type.\n",
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serd_max_num);
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__func__, serdes_id,
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return MV_FAIL;
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serdes_type_to_string[serdes_type],
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}
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serd_max_num);
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return MV_FAIL;
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}
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}
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return MV_OK;
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return MV_OK;
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@ -133,8 +133,6 @@
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_BUS 0
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#define CONFIG_SPL_SPI_CS 0
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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#endif
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#endif
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@ -100,8 +100,6 @@
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_BUS 0
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#define CONFIG_SPL_SPI_CS 0
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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@ -134,8 +134,6 @@
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_BUS 0
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#define CONFIG_SPL_SPI_CS 0
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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#endif
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#endif
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@ -125,8 +125,6 @@
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_BUS 0
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#define CONFIG_SPL_SPI_CS 0
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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@ -132,8 +132,6 @@
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_BUS 0
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#define CONFIG_SPL_SPI_CS 0
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
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/* DS414 bus width is 32bits */
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/* DS414 bus width is 32bits */
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@ -93,8 +93,6 @@
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_BUS 0
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#define CONFIG_SPL_SPI_CS 0
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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@ -158,8 +158,6 @@
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_BUS 0
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#define CONFIG_SPL_SPI_CS 0
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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@ -655,14 +655,6 @@ kwboot_img_patch_hdr(void *img, size_t size)
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hdr->blockid = IBR_HDR_UART_ID;
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hdr->blockid = IBR_HDR_UART_ID;
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/*
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* Subtract mkimage header size from destination address
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* as this header is not expected by the Marvell BootROM.
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* This way, the execution address is identical to the
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* one the image is compiled for (TEXT_BASE).
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*/
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hdr->destaddr = hdr->destaddr - sizeof(struct image_header);
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if (image_ver == 0) {
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if (image_ver == 0) {
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struct main_hdr_v0 *hdr_v0 = img;
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struct main_hdr_v0 *hdr_v0 = img;
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@ -672,6 +664,14 @@ kwboot_img_patch_hdr(void *img, size_t size)
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hdr_v0->srcaddr = hdr_v0->ext
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hdr_v0->srcaddr = hdr_v0->ext
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? sizeof(struct kwb_header)
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? sizeof(struct kwb_header)
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: sizeof(*hdr_v0);
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: sizeof(*hdr_v0);
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} else {
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/*
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* Subtract mkimage header size from destination address
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* as this header is not expected by the Marvell BootROM.
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* This way, the execution address is identical to the
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* one the image is compiled for (TEXT_BASE).
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*/
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hdr->destaddr = hdr->destaddr - sizeof(struct image_header);
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}
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}
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hdr->checksum = kwboot_img_csum8(hdr, hdrsz) - csum;
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hdr->checksum = kwboot_img_csum8(hdr, hdrsz) - csum;
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