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https://github.com/AsahiLinux/u-boot
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Add "cls" function to MPC823 LCD driver so we can reinitialize the
display even after showing a bitmap
This commit is contained in:
wdenk
parent
021bfcd3c6
commit
c3f4d17e05
4 changed files with 35 additions and 54 deletions
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@ -2,6 +2,9 @@
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Changes since U-Boot 1.1.1:
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======================================================================
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* Add "cls" function to MPC823 LCD driver so we can reinitialize the
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display even after showing a bitmap
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* Patch by Josef Wagner, 04 Jun 2004:
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- DDR Ram support for PM520 (MPC5200)
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- support for different flash types (PM520)
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@ -29,6 +29,7 @@
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <watchdog.h>
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#include <version.h>
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#include <stdarg.h>
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@ -434,8 +435,9 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count);
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static inline void lcd_puts_xy (ushort x, ushort y, uchar *s);
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static inline void lcd_putc_xy (ushort x, ushort y, uchar c);
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int lcd_init (void *lcdbase);
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static int lcd_init (void *lcdbase);
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static int lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
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static void lcd_ctrl_init (void *lcdbase);
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static void lcd_enable (void);
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static void *lcd_logo (void);
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@ -718,13 +720,8 @@ int drv_lcd_init (void)
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/*----------------------------------------------------------------------*/
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int lcd_init (void *lcdbase)
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static int lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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/* Initialize the lcd controller */
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debug ("[LCD] Initializing LCD frambuffer at %p\n", lcdbase);
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lcd_ctrl_init (lcdbase);
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#if LCD_BPP == LCD_MONOCHROME
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/* Setting the palette */
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lcd_initcolregs();
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@ -758,13 +755,33 @@ int lcd_init (void *lcdbase)
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COLOR_MASK(lcd_getbgcolor()),
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lcd_line_length*panel_info.vl_row);
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#endif
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lcd_enable ();
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/* Paint the logo and retrieve LCD base address */
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debug ("[LCD] Drawing the logo...\n");
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lcd_console_address = lcd_logo ();
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console_col = 0;
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console_row = 0;
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return (0);
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}
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U_BOOT_CMD(
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cls, 1, 1, lcd_clear,
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"cls - clear screen\n",
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NULL
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);
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/*----------------------------------------------------------------------*/
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static int lcd_init (void *lcdbase)
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{
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/* Initialize the lcd controller */
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debug ("[LCD] Initializing LCD frambuffer at %p\n", lcdbase);
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lcd_ctrl_init (lcdbase);
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lcd_clear (NULL, 1, 1, NULL); /* dummy args */
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lcd_enable ();
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/* Initialize the console */
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console_col = 0;
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#ifdef LCD_INFO_BELOW_LOGO
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@ -297,12 +297,7 @@
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*
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* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
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*/
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#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
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#define CFG_PLPRCR \
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( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
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#else /* up to 66 MHz we use a 1:1 clock */
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#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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#endif /* CONFIG_80MHz */
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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@ -311,33 +306,15 @@
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
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#define CFG_SCCR (/* SCCR_TBS | */ \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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#else /* up to 66 MHz we use a 1:1 clock */
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#define CFG_SCCR (SCCR_TBS | \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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#endif /* CONFIG_80MHz */
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*
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*/
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#ifndef CONFIG_HMI10
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#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
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#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
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#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
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#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_IO_ADDR (0xEC000000)
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#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
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#else /* CONFIG_HMI10 */
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#define CFG_PCMCIA_MEM_ADDR (0xE0100000)
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#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_DMA_ADDR (0xE4100000)
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@ -348,7 +325,6 @@
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#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
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#define PCMCIA_MEM_WIN_NO 5
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#define NSCU_OE_INV 1 /* PCMCIA_GCRX_CXOE is inverted */
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#endif
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
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@ -405,19 +381,8 @@
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/*
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* FLASH timing:
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*/
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#if defined(CONFIG_80MHz)
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/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
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OR_SCY_3_CLK | OR_EHTR | OR_BI)
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#elif defined(CONFIG_66MHz)
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/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
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OR_SCY_3_CLK | OR_EHTR | OR_BI)
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#else /* 50 MHz */
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/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
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OR_SCY_2_CLK | OR_EHTR | OR_BI)
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#endif /*CONFIG_??MHz */
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
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@ -478,13 +443,9 @@
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* 66 Mhz => 66.000.000 / Divider = 129
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* 80 Mhz => 80.000.000 / Divider = 156
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*/
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#if defined(CONFIG_80MHz)
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#define CFG_MAMR_PTA 156
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#elif defined(CONFIG_66MHz)
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#define CFG_MAMR_PTA 129
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#else /* 50 MHz */
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#define CFG_MAMR_PTA 98
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#endif /*CONFIG_??MHz */
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#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
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#define CFG_MAMR_PTA 98
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/*
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* For 16 MBit, refresh rates could be 31.3 us
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@ -37,7 +37,7 @@ extern char lcd_is_enabled;
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/* Video functions */
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int lcd_init (void *lcdbase);
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/* int lcd_init (void *lcdbase); */
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void lcd_putc (const char c);
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void lcd_puts (const char *s);
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void lcd_printf (const char *fmt, ...);
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