mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-26 14:40:41 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
This commit is contained in:
Tom Rini
commit
c3ebb8c38a
26 changed files with 2353 additions and 213 deletions
|
|
@ -70,6 +70,9 @@ obj-$(CONFIG_PPC_B4860) += ddr-gen3.o
|
|||
obj-$(CONFIG_BSC9131) += ddr-gen3.o
|
||||
obj-$(CONFIG_BSC9132) += ddr-gen3.o
|
||||
obj-$(CONFIG_PPC_T1040) += ddr-gen3.o
|
||||
obj-$(CONFIG_PPC_T1042) += ddr-gen3.o
|
||||
obj-$(CONFIG_PPC_T1020) += ddr-gen3.o
|
||||
obj-$(CONFIG_PPC_T1022) += ddr-gen3.o
|
||||
|
||||
obj-$(CONFIG_CPM2) += ether_fcc.o
|
||||
obj-$(CONFIG_OF_LIBFDT) += fdt.o
|
||||
|
|
@ -89,6 +92,10 @@ obj-$(CONFIG_PPC_T4160) += t4240_ids.o
|
|||
obj-$(CONFIG_PPC_B4420) += b4860_ids.o
|
||||
obj-$(CONFIG_PPC_B4860) += b4860_ids.o
|
||||
obj-$(CONFIG_PPC_T1040) += t1040_ids.o
|
||||
obj-$(CONFIG_PPC_T1042) += t1040_ids.o
|
||||
obj-$(CONFIG_PPC_T1020) += t1040_ids.o
|
||||
obj-$(CONFIG_PPC_T1022) += t1040_ids.o
|
||||
|
||||
|
||||
obj-$(CONFIG_QE) += qe_io.o
|
||||
obj-$(CONFIG_CPM2) += serial_scc.o
|
||||
|
|
@ -128,6 +135,9 @@ obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
|
|||
obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
|
||||
obj-$(CONFIG_BSC9132) += bsc9132_serdes.o
|
||||
obj-$(CONFIG_PPC_T1040) += t1040_serdes.o
|
||||
obj-$(CONFIG_PPC_T1042) += t1040_serdes.o
|
||||
obj-$(CONFIG_PPC_T1020) += t1040_serdes.o
|
||||
obj-$(CONFIG_PPC_T1022) += t1040_serdes.o
|
||||
|
||||
obj-y += cpu.o
|
||||
obj-y += cpu_init.o
|
||||
|
|
|
|||
|
|
@ -586,6 +586,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
|
|||
{
|
||||
int off;
|
||||
int val;
|
||||
int len;
|
||||
sys_info_t sysinfo;
|
||||
|
||||
/* delete crypto node if not on an E-processor */
|
||||
|
|
@ -615,8 +616,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
|
|||
get_sys_info(&sysinfo);
|
||||
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
|
||||
while (off != -FDT_ERR_NOTFOUND) {
|
||||
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
|
||||
val = cpu_to_fdt32(sysinfo.freq_processor[*reg]);
|
||||
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
|
||||
val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
|
||||
fdt_setprop(blob, off, "clock-frequency", &val, 4);
|
||||
off = fdt_node_offset_by_prop_value(blob, off, "device_type",
|
||||
"cpu", 4);
|
||||
|
|
|
|||
|
|
@ -239,9 +239,9 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
|
|||
#endif
|
||||
|
||||
#define CONFIG_SYS_MAX_PCI_EPS 8
|
||||
#define CONFIG_SYS_PCI_EP_LIODN_START 256
|
||||
|
||||
static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat)
|
||||
static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat,
|
||||
int ep_liodn_start)
|
||||
{
|
||||
int off, pci_idx = 0, pci_cnt = 0, i, rc;
|
||||
const uint32_t *base_liodn;
|
||||
|
|
@ -271,7 +271,7 @@ static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat)
|
|||
continue;
|
||||
}
|
||||
for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++)
|
||||
liodn_offs[i + 1] = CONFIG_SYS_PCI_EP_LIODN_START +
|
||||
liodn_offs[i + 1] = ep_liodn_start +
|
||||
i * pci_cnt + pci_idx - *base_liodn;
|
||||
rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list",
|
||||
liodn_offs, sizeof(liodn_offs));
|
||||
|
|
@ -338,5 +338,22 @@ void fdt_fixup_liodn(void *blob)
|
|||
fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz);
|
||||
#endif
|
||||
|
||||
fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie-v2.4");
|
||||
ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR;
|
||||
int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0;
|
||||
|
||||
if (pci_ver >= 0x0204) {
|
||||
if (pci_ver >= 0x0300)
|
||||
liodn_base = 1024;
|
||||
else
|
||||
liodn_base = 256;
|
||||
}
|
||||
|
||||
if (liodn_base) {
|
||||
char compat[32];
|
||||
|
||||
sprintf(compat, "fsl,qoriq-pcie-v%d.%d",
|
||||
(pci_ver & 0xff00) >> 8, pci_ver & 0xff);
|
||||
fdt_fixup_pci_liodn_offsets(blob, compat, liodn_base);
|
||||
fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie", liodn_base);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -86,10 +86,10 @@ struct liodn_id_table liodn_tbl[] = {
|
|||
SET_SATA_LIODN(1, 555),
|
||||
SET_SATA_LIODN(2, 556),
|
||||
|
||||
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
|
||||
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
|
||||
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
|
||||
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
|
||||
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
|
||||
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
|
||||
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
|
||||
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
|
||||
|
||||
SET_DMA_LIODN(1, 147),
|
||||
SET_DMA_LIODN(2, 227),
|
||||
|
|
|
|||
|
|
@ -674,7 +674,8 @@
|
|||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#endif
|
||||
|
||||
#elif defined(CONFIG_PPC_T1040)
|
||||
#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
|
||||
defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
||||
#define CONFIG_E5500
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
||||
|
|
|
|||
|
|
@ -763,6 +763,7 @@ typedef struct immap {
|
|||
u8 res7[0xC0000];
|
||||
} immap_t;
|
||||
|
||||
#ifndef CONFIG_MPC834x
|
||||
#ifdef CONFIG_HAS_FSL_MPH_USB
|
||||
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */
|
||||
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0
|
||||
|
|
@ -770,6 +771,10 @@ typedef struct immap {
|
|||
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0
|
||||
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */
|
||||
#endif
|
||||
#else
|
||||
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000
|
||||
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000
|
||||
#endif
|
||||
|
||||
#elif defined(CONFIG_MPC8313)
|
||||
typedef struct immap {
|
||||
|
|
|
|||
|
|
@ -282,7 +282,9 @@ typedef struct ccsr_pcix {
|
|||
u32 int_ack; /* PCIX IRQ Acknowledge */
|
||||
u8 res000c[52];
|
||||
u32 liodn_base; /* PCIX LIODN base register */
|
||||
u8 res0044[3004];
|
||||
u8 res0044[2996];
|
||||
u32 ipver1; /* PCIX IP block revision register 1 */
|
||||
u32 ipver2; /* PCIX IP block revision register 2 */
|
||||
u32 potar0; /* PCIX Outbound Transaction Addr 0 */
|
||||
u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
|
||||
u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
|
||||
|
|
@ -1847,7 +1849,8 @@ typedef struct ccsr_gur {
|
|||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
|
||||
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
|
||||
#elif defined(CONFIG_PPC_T1040)
|
||||
#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
|
||||
defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
|
||||
|
|
|
|||
|
|
@ -204,5 +204,5 @@ Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
|
|||
=> bootm 1000000 3000000 2000000
|
||||
|
||||
|
||||
Please contact your local field applications engineer or sales representative
|
||||
to obtain related documents, such as P1010-RDB User Guide for details.
|
||||
For more details, please refer to P1010RDB User Guide and access website
|
||||
www.freescale.com
|
||||
188
board/freescale/p1010rdb/README.P1010RDB-PB
Normal file
188
board/freescale/p1010rdb/README.P1010RDB-PB
Normal file
|
|
@ -0,0 +1,188 @@
|
|||
Overview
|
||||
=========
|
||||
The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
|
||||
P1010RDB-PB is a variation of previous P1010RDB-PA board.
|
||||
|
||||
The P1010 is a cost-effective, low-power, highly integrated host processor
|
||||
based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that
|
||||
addresses the requirements of several routing, gateways, storage, consumer,
|
||||
and industrial applications. Applications of interest include the main CPUs and
|
||||
I/O processors in network attached storage (NAS), the voice over IP (VoIP)
|
||||
router/gateway, and wireless LAN (WLAN) and industrial controllers.
|
||||
|
||||
The P1010RDB-PB board features are as following:
|
||||
Memory subsystem:
|
||||
- 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
|
||||
- 32M bytes NOR flash single-chip memory
|
||||
- 2G bytes NAND flash memory
|
||||
- 16M bytes SPI memory
|
||||
- 256K bit M24256 I2C EEPROM
|
||||
- I2C Board EEPROM 128x8 bit memory
|
||||
- SD/MMC connector to interface with the SD memory card
|
||||
Interfaces:
|
||||
- Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII)
|
||||
- PCIe 2.0: two x1 mini-PCIe slots
|
||||
- SATA 2.0: two SATA interfaces
|
||||
- USB 2.0: one USB interface
|
||||
- FlexCAN: two FlexCAN interfaces (revision 2.0B)
|
||||
- UART: one USB-to-Serial interface
|
||||
- TDM: 2 FXS ports connected via an external SLIC to the TDM interface.
|
||||
1 FXO port connected via a relay to FXS for switchover to POTS
|
||||
|
||||
Board connectors:
|
||||
- Mini-ITX power supply connector
|
||||
- JTAG/COP for debugging
|
||||
|
||||
POR: support critical POR setting changed via switch on board
|
||||
PCB: 6-layer routing (4-layer signals, 2-layer power and ground)
|
||||
|
||||
Physical Memory Map on P1010RDB
|
||||
===============================
|
||||
Address Start Address End Memory type Attributes
|
||||
0x0000_0000 0x3fff_ffff DDR 1G Cacheable
|
||||
0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
|
||||
0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
|
||||
0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
|
||||
0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
|
||||
0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
|
||||
0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
|
||||
0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
|
||||
|
||||
|
||||
Serial Port Configuration on P1010RDB
|
||||
=====================================
|
||||
Configure the serial port of the attached computer with the following values:
|
||||
-Data rate: 115200 bps
|
||||
-Number of data bits: 8
|
||||
-Parity: None
|
||||
-Number of Stop bits: 1
|
||||
-Flow Control: Hardware/None
|
||||
|
||||
|
||||
P1010RDB-PB default DIP-switch settings
|
||||
=======================================
|
||||
SW1[1:8]= 10101010
|
||||
SW2[1:8]= 11011000
|
||||
SW3[1:8]= 10010000
|
||||
SW4[1:4]= 1010
|
||||
SW5[1:8]= 11111010
|
||||
|
||||
|
||||
P1010RDB-PB boot mode settings via DIP-switch
|
||||
=============================================
|
||||
SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot
|
||||
SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot
|
||||
SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
|
||||
SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot
|
||||
Note: 1 stands for 'on', 0 stands for 'off'
|
||||
|
||||
|
||||
Switch P1010RDB-PB boot mode via software without setting DIP-switch
|
||||
====================================================================
|
||||
=> run boot_bank0 (boot from NOR bank0)
|
||||
=> run boot_bank1 (boot from NOR bank1)
|
||||
=> run boot_nand (boot from NAND flash)
|
||||
=> run boot_spi (boot from SPI flash)
|
||||
=> run boot_sd (boot from SD card)
|
||||
|
||||
|
||||
Frequency combination support on P1010RDB-PB
|
||||
=============================================
|
||||
SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s)
|
||||
0101 1 1010 0 800 400 800
|
||||
1001 1 1010 0 800 400 667
|
||||
1010 1 1100 0 667 333 667
|
||||
1000 0 1010 0 533 266 667
|
||||
0101 1 1010 1 1000 400 800
|
||||
1001 1 1010 1 1000 400 667
|
||||
|
||||
|
||||
Setting of pin mux
|
||||
==================
|
||||
Since pins multiplexing, TDM and CAN are muxed with SPI flash.
|
||||
SDHC is muxed with IFC. IFC and SPI flash are enabled by default.
|
||||
|
||||
To enable TDM:
|
||||
=> setenv hwconfig fsl_p1010mux:tdm_can=tdm
|
||||
=> save;reset
|
||||
|
||||
To enable FlexCAN:
|
||||
=> setenv hwconfig fsl_p1010mux:tdm_can=can
|
||||
=> save;reset
|
||||
|
||||
To enable SDHC in case of NOR/NAND/SPI boot
|
||||
a) For temporary use case in runtime without reboot system
|
||||
run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC.
|
||||
|
||||
b) For long-term use case
|
||||
set 'esdhc' in hwconfig and save it.
|
||||
|
||||
To enable IFC in case of SD boot
|
||||
a) For temporary use case in runtime without reboot system
|
||||
run 'mux ifc' in u-boot to validate IFC with invalidating SDHC.
|
||||
|
||||
b) For long-term use case
|
||||
set 'ifc' in hwconfig and save it.
|
||||
|
||||
|
||||
Build images for different boot mode
|
||||
====================================
|
||||
First setup cross compile environment on build host
|
||||
$ export ARCH=powerpc
|
||||
$ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu-
|
||||
|
||||
1. For NOR boot
|
||||
$ make P1010RDB-PB_NOR
|
||||
|
||||
2. For NAND boot
|
||||
$ make P1010RDB-PB_NAND
|
||||
|
||||
3. For SPI boot
|
||||
$ make P1010RDB-PB_SPIFLASH
|
||||
|
||||
4. For SD boot
|
||||
$ make P1010RDB-PB_SDCARD
|
||||
|
||||
|
||||
Steps to program images to flash for different boot mode
|
||||
========================================================
|
||||
1. NOR boot
|
||||
=> tftp 1000000 u-boot.bin
|
||||
For bank0
|
||||
=> pro off all;era eff80000 efffffff;cp.b 1000000 eff80000 $filesize
|
||||
set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
|
||||
|
||||
For bank1
|
||||
=> pro off all;era eef80000 eeffffff;cp.b 1000000 eef80000 $filesize
|
||||
set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
|
||||
|
||||
2. NAND boot
|
||||
=> tftp 1000000 u-boot-nand.bin
|
||||
=> nand erase 0 $filesize; nand write $loadaddr 0 $filesize
|
||||
Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board
|
||||
|
||||
3. SPI boot
|
||||
1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin
|
||||
2) => tftp 1000000 u-boot-spi-combined.bin
|
||||
3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000
|
||||
set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board
|
||||
|
||||
4. SD boot
|
||||
1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin
|
||||
2) => tftp 1000000 u-boot-sd-combined.bin
|
||||
3) => mux sdhc
|
||||
4) => mmc write 1000000 0 1050
|
||||
set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board
|
||||
|
||||
|
||||
Boot Linux from network using TFTP on P1010RDB-PB
|
||||
=================================================
|
||||
Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path.
|
||||
=> tftp 1000000 uImage
|
||||
=> tftp 2000000 p1010rdb.dtb
|
||||
=> tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
|
||||
=> bootm 1000000 3000000 2000000
|
||||
|
||||
|
||||
For more details, please refer to P1010RDB-PB User Guide and access website
|
||||
www.freescale.com and Freescale QorIQ SDK Infocenter document.
|
||||
27
board/freescale/t1040qds/t1040_pbi.cfg
Normal file
27
board/freescale/t1040qds/t1040_pbi.cfg
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
#PBI commands
|
||||
#Initialize CPC1
|
||||
09010000 00200400
|
||||
09138000 00000000
|
||||
091380c0 00000100
|
||||
#Configure CPC1 as 512KB SRAM
|
||||
09010100 00000000
|
||||
09010104 fffc0007
|
||||
09010f00 08000000
|
||||
09010000 80000000
|
||||
#Configure LAW for CPC1
|
||||
09000cf0 00000000
|
||||
09000cf4 fffc0000
|
||||
09000cf8 81000011
|
||||
#Configure alternate space
|
||||
09000010 00000000
|
||||
09000014 ff000000
|
||||
09000018 81000000
|
||||
#Configure SPI controller
|
||||
09110000 80000403
|
||||
09110020 2d170008
|
||||
09110024 00100008
|
||||
09110028 00100008
|
||||
0911002c 00100008
|
||||
#Flush PBL data
|
||||
09138000 00000000
|
||||
091380c0 00000000
|
||||
7
board/freescale/t1040qds/t1040_rcw.cfg
Normal file
7
board/freescale/t1040qds/t1040_rcw.cfg
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
#PBL preamble and RCW header
|
||||
aa55aa55 010e0100
|
||||
# serdes protocol 0x66
|
||||
0a10000c 0c000000 00000000 00000000
|
||||
66000002 00000000 fc027000 01000000
|
||||
00000000 00000000 00000000 00030810
|
||||
00000000 03fc500f 00000000 00000000
|
||||
12
board/freescale/t104xrdb/Makefile
Normal file
12
board/freescale/t104xrdb/Makefile
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#
|
||||
# Copyright 2013 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
|
||||
obj-y += t104xrdb.o
|
||||
obj-y += ddr.o
|
||||
obj-$(CONFIG_PCI) += pci.o
|
||||
obj-y += law.o
|
||||
obj-y += tlb.o
|
||||
200
board/freescale/t104xrdb/README
Normal file
200
board/freescale/t104xrdb/README
Normal file
|
|
@ -0,0 +1,200 @@
|
|||
Overview
|
||||
--------
|
||||
The T1040RDB is a Freescale reference board that hosts the T1040 SoC
|
||||
(and variants). Variants inclued T1042 presonality of T1040, in which
|
||||
case T1040RDB can also be called T1042RDB.
|
||||
|
||||
The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
|
||||
(a personality of T1040 SoC). The board is similar to T1040RDB but is
|
||||
designed specially with low power features targeted for Printing Image Market.
|
||||
|
||||
T1040 SoC Overview
|
||||
------------------
|
||||
The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
|
||||
processor cores with high-performance data path acceleration architecture
|
||||
and network peripheral interfaces required for networking & telecommunications.
|
||||
|
||||
The T1040/T1042 SoC includes the following function and features:
|
||||
|
||||
- Four e5500 cores, each with a private 256 KB L2 cache
|
||||
- 256 KB shared L3 CoreNet platform cache (CPC)
|
||||
- Interconnect CoreNet platform
|
||||
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
|
||||
support
|
||||
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
|
||||
for the following functions:
|
||||
- Packet parsing, classification, and distribution
|
||||
- Queue management for scheduling, packet sequencing, and congestion
|
||||
management
|
||||
- Cryptography Acceleration (SEC 5.0)
|
||||
- RegEx Pattern Matching Acceleration (PME 2.2)
|
||||
- IEEE Std 1588 support
|
||||
- Hardware buffer management for buffer allocation and deallocation
|
||||
- Ethernet interfaces
|
||||
- Integrated 8-port Gigabit Ethernet switch (T1040 only)
|
||||
- Four 1 Gbps Ethernet controllers
|
||||
- Two RGMII interfaces or one RGMII and one MII interfaces
|
||||
- High speed peripheral interfaces
|
||||
- Four PCI Express 2.0 controllers running at up to 5 GHz
|
||||
- Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
|
||||
- Upto two QSGMII interface
|
||||
- Upto six SGMII interface supporting 1000 Mbps
|
||||
- One SGMII interface supporting upto 2500 Mbps
|
||||
- Additional peripheral interfaces
|
||||
- Two USB 2.0 controllers with integrated PHY
|
||||
- SD/eSDHC/eMMC
|
||||
- eSPI controller
|
||||
- Four I2C controllers
|
||||
- Four UARTs
|
||||
- Four GPIO controllers
|
||||
- Integrated flash controller (IFC)
|
||||
- LCD and HDMI interface (DIU) with 12 bit dual data rate
|
||||
- TDM interface
|
||||
- Multicore programmable interrupt controller (PIC)
|
||||
- Two 8-channel DMA engines
|
||||
- Single source clocking implementation
|
||||
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
|
||||
|
||||
T1040 SoC Personalities
|
||||
-------------------------
|
||||
|
||||
T1022 Personality:
|
||||
T1022 is a reduced personality of T1040 with less core/clusters.
|
||||
|
||||
T1042 Personality:
|
||||
T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
|
||||
Ethernet switch. Rest of the blocks are same as T1040
|
||||
|
||||
|
||||
T1040RDB board Overview
|
||||
-------------------------
|
||||
- SERDES Connections, 8 lanes information:
|
||||
1: None
|
||||
2: SGMII
|
||||
3: QSGMII
|
||||
4: QSGMII
|
||||
5: PCIe1 x1 slot
|
||||
6: mini PCIe connector
|
||||
7: mini PCIe connector
|
||||
8: SATA connector
|
||||
- DDR Controller
|
||||
- Supports rates of up to 1600 MHz data-rate
|
||||
- Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
|
||||
- IFC/Local Bus
|
||||
- NAND flash: 1GB 8-bit NAND flash
|
||||
- NOR: 128MB 16-bit NOR Flash
|
||||
- Ethernet
|
||||
- Two on-board RGMII 10/100/1G ethernet ports.
|
||||
- CPLD
|
||||
- Clocks
|
||||
- System and DDR clock (SYSCLK, “DDRCLK”)
|
||||
- SERDES clocks
|
||||
- Power Supplies
|
||||
- USB
|
||||
- Supports two USB 2.0 ports with integrated PHYs
|
||||
- Two type A ports with 5V@1.5A per port.
|
||||
- SDHC
|
||||
- SDHC/SDXC connector
|
||||
- SPI
|
||||
- On-board 64MB SPI flash
|
||||
- Other IO
|
||||
- Two Serial ports
|
||||
- Four I2C ports
|
||||
|
||||
T1042RDB_PI board Overview
|
||||
-------------------------
|
||||
- SERDES Connections, 8 lanes information:
|
||||
1, 2, 3, 4 : PCIe x4 slot
|
||||
5: mini PCIe connector
|
||||
6: mini PCIe connector
|
||||
7: NA
|
||||
8: SATA connector
|
||||
- DDR Controller
|
||||
- Supports rates of up to 1600 MHz data-rate
|
||||
- Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
|
||||
- IFC/Local Bus
|
||||
- NAND flash: 1GB 8-bit NAND flash
|
||||
- NOR: 128MB 16-bit NOR Flash
|
||||
- Ethernet
|
||||
- Two on-board RGMII 10/100/1G ethernet ports.
|
||||
- CPLD
|
||||
- Clocks
|
||||
- System and DDR clock (SYSCLK, “DDRCLK”)
|
||||
- SERDES clocks
|
||||
- Video
|
||||
- DIU supports video at up to 1280x1024x32bpp
|
||||
- Power Supplies
|
||||
- USB
|
||||
- Supports two USB 2.0 ports with integrated PHYs
|
||||
- Two type A ports with 5V@1.5A per port.
|
||||
- SDHC
|
||||
- SDHC/SDXC connector
|
||||
- SPI
|
||||
- On-board 64MB SPI flash
|
||||
- Other IO
|
||||
- Two Serial ports
|
||||
- Four I2C ports
|
||||
|
||||
Memory map
|
||||
-----------
|
||||
The addresses in brackets are physical addresses.
|
||||
|
||||
Start Address End Address Description Size
|
||||
0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
|
||||
0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
|
||||
0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
|
||||
0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
|
||||
0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
|
||||
0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
|
||||
0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
|
||||
0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
|
||||
0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
|
||||
0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
|
||||
0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
|
||||
0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB
|
||||
0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
|
||||
0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
|
||||
0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
|
||||
0x0_0000_0000 0x0_ffff_ffff DDR 2GB
|
||||
|
||||
|
||||
NOR Flash memory Map
|
||||
---------------------
|
||||
Start End Definition Size
|
||||
0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB
|
||||
0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB
|
||||
0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB
|
||||
0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB
|
||||
0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB
|
||||
0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
|
||||
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
|
||||
0xEBF80000 0xEBFFFFFF u-boot (alt bank) 512KB
|
||||
0xEBF60000 0xEBF7FFFF u-boot env (alt bank) 128KB
|
||||
0xEBF40000 0xEBF5FFFF FMAN ucode (alt bank) 128KB
|
||||
0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB
|
||||
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
|
||||
0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
|
||||
0xE8000000 0xE801FFFF RCW (current bank) 128KB
|
||||
|
||||
|
||||
Various Software configurations/environment variables/commands
|
||||
--------------------------------------------------------------
|
||||
The below commands apply to the board
|
||||
|
||||
1. U-boot environment variable hwconfig
|
||||
The default hwconfig is:
|
||||
hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
|
||||
dr_mode=host,phy_type=utmi
|
||||
Note: For USB gadget set "dr_mode=peripheral"
|
||||
|
||||
2. FMAN Ucode versions
|
||||
fsl_fman_ucode_t1040.bin
|
||||
|
||||
3. Switching to alternate bank
|
||||
Commands for switching to alternate bank.
|
||||
|
||||
1. To change from vbank0 to vbank4
|
||||
=> qixis_reset altbank (it will boot using vbank4)
|
||||
|
||||
2.To change from vbank4 to vbank0
|
||||
=> qixis reset (it will boot using vbank0)
|
||||
132
board/freescale/t104xrdb/ddr.c
Normal file
132
board/freescale/t104xrdb/ddr.c
Normal file
|
|
@ -0,0 +1,132 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <hwconfig.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/fsl_ddr_sdram.h>
|
||||
#include <asm/fsl_ddr_dimm_params.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include "ddr.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
|
||||
unsigned int controller_number,
|
||||
unsigned int dimm_number)
|
||||
{
|
||||
const char dimm_model[] = "RAW timing DDR";
|
||||
|
||||
if ((controller_number == 0) && (dimm_number == 0)) {
|
||||
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
|
||||
memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
|
||||
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts,
|
||||
dimm_params_t *pdimm,
|
||||
unsigned int ctrl_num)
|
||||
{
|
||||
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
|
||||
ulong ddr_freq;
|
||||
|
||||
if (ctrl_num > 1) {
|
||||
printf("Not supported controller number %d\n", ctrl_num);
|
||||
return;
|
||||
}
|
||||
if (!pdimm->n_ranks)
|
||||
return;
|
||||
|
||||
pbsp = udimms[0];
|
||||
|
||||
/* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
|
||||
* freqency and n_banks specified in board_specific_parameters table.
|
||||
*/
|
||||
ddr_freq = get_ddr_freq(0) / 1000000;
|
||||
while (pbsp->datarate_mhz_high) {
|
||||
if (pbsp->n_ranks == pdimm->n_ranks &&
|
||||
(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
|
||||
if (ddr_freq <= pbsp->datarate_mhz_high) {
|
||||
popts->cpo_override = pbsp->cpo;
|
||||
popts->write_data_delay =
|
||||
pbsp->write_data_delay;
|
||||
popts->clk_adjust = pbsp->clk_adjust;
|
||||
popts->wrlvl_start = pbsp->wrlvl_start;
|
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
|
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
|
||||
popts->twot_en = pbsp->force_2t;
|
||||
goto found;
|
||||
}
|
||||
pbsp_highest = pbsp;
|
||||
}
|
||||
pbsp++;
|
||||
}
|
||||
|
||||
if (pbsp_highest) {
|
||||
printf("Error: board specific timing not found\n");
|
||||
printf("for data rate %lu MT/s\n", ddr_freq);
|
||||
printf("Trying to use the highest speed (%u) parameters\n",
|
||||
pbsp_highest->datarate_mhz_high);
|
||||
popts->cpo_override = pbsp_highest->cpo;
|
||||
popts->write_data_delay = pbsp_highest->write_data_delay;
|
||||
popts->clk_adjust = pbsp_highest->clk_adjust;
|
||||
popts->wrlvl_start = pbsp_highest->wrlvl_start;
|
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
|
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
|
||||
popts->twot_en = pbsp_highest->force_2t;
|
||||
} else {
|
||||
panic("DIMM is not supported by this board");
|
||||
}
|
||||
found:
|
||||
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
|
||||
"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
|
||||
"wrlvl_ctrl_3 0x%x\n",
|
||||
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
|
||||
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
|
||||
pbsp->wrlvl_ctl_3);
|
||||
|
||||
/*
|
||||
* Factors to consider for half-strength driver enable:
|
||||
* - number of DIMMs installed
|
||||
*/
|
||||
popts->half_strength_driver_enable = 0;
|
||||
/*
|
||||
* Write leveling override
|
||||
*/
|
||||
popts->wrlvl_override = 1;
|
||||
popts->wrlvl_sample = 0xf;
|
||||
|
||||
/*
|
||||
* rtt and rtt_wr override
|
||||
*/
|
||||
popts->rtt_override = 0;
|
||||
|
||||
/* Enable ZQ calibration */
|
||||
popts->zq_en = 1;
|
||||
|
||||
/* DHC_EN =1, ODT = 75 Ohm */
|
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
|
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
|
||||
}
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
phys_size_t dram_size;
|
||||
|
||||
puts("Initializing....using SPD\n");
|
||||
|
||||
dram_size = fsl_ddr_sdram();
|
||||
|
||||
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
|
||||
dram_size *= 0x100000;
|
||||
|
||||
puts(" DDR: ");
|
||||
return dram_size;
|
||||
}
|
||||
76
board/freescale/t104xrdb/ddr.h
Normal file
76
board/freescale/t104xrdb/ddr.h
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __DDR_H__
|
||||
#define __DDR_H__
|
||||
|
||||
dimm_params_t ddr_raw_timing = {
|
||||
.n_ranks = 2,
|
||||
.rank_density = 2147483648u,
|
||||
.capacity = 4294967296u,
|
||||
.primary_sdram_width = 64,
|
||||
.ec_sdram_width = 8,
|
||||
.registered_dimm = 0,
|
||||
.mirrored_dimm = 1,
|
||||
.n_row_addr = 15,
|
||||
.n_col_addr = 10,
|
||||
.n_banks_per_sdram_device = 8,
|
||||
.edc_config = 2, /* ECC */
|
||||
.burst_lengths_bitmask = 0x0c,
|
||||
|
||||
.tckmin_x_ps = 1071,
|
||||
.caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
|
||||
.taa_ps = 13910,
|
||||
.twr_ps = 15000,
|
||||
.trcd_ps = 13910,
|
||||
.trrd_ps = 6000,
|
||||
.trp_ps = 13910,
|
||||
.tras_ps = 34000,
|
||||
.trc_ps = 48910,
|
||||
.trfc_ps = 260000,
|
||||
.twtr_ps = 7500,
|
||||
.trtp_ps = 7500,
|
||||
.refresh_rate_ps = 7800000,
|
||||
.tfaw_ps = 35000,
|
||||
};
|
||||
|
||||
struct board_specific_parameters {
|
||||
u32 n_ranks;
|
||||
u32 datarate_mhz_high;
|
||||
u32 rank_gb;
|
||||
u32 clk_adjust;
|
||||
u32 wrlvl_start;
|
||||
u32 wrlvl_ctl_2;
|
||||
u32 wrlvl_ctl_3;
|
||||
u32 cpo;
|
||||
u32 write_data_delay;
|
||||
u32 force_2t;
|
||||
};
|
||||
|
||||
/*
|
||||
* These tables contain all valid speeds we want to override with board
|
||||
* specific parameters. datarate_mhz_high values need to be in ascending order
|
||||
* for each n_ranks group.
|
||||
*/
|
||||
|
||||
static const struct board_specific_parameters udimm0[] = {
|
||||
/*
|
||||
* memory controller 0
|
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
|
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
|
||||
*/
|
||||
{2, 1066, 4, 8, 4, 0x05070609, 0x08090a08, 0xff, 2, 0},
|
||||
{2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
|
||||
{2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
|
||||
{2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
|
||||
{2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct board_specific_parameters *udimms[] = {
|
||||
udimm0,
|
||||
};
|
||||
#endif
|
||||
32
board/freescale/t104xrdb/law.c
Normal file
32
board/freescale/t104xrdb/law.c
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct law_entry law_table[] = {
|
||||
#ifndef CONFIG_SYS_NO_FLASH
|
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
|
||||
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
|
||||
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_CPLD_BASE_PHYS
|
||||
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS
|
||||
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_NAND_BASE_PHYS
|
||||
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table);
|
||||
23
board/freescale/t104xrdb/pci.c
Normal file
23
board/freescale/t104xrdb/pci.c
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <pci.h>
|
||||
#include <asm/fsl_pci.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
fsl_pcie_init_board(0);
|
||||
}
|
||||
|
||||
void pci_of_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
FT_FSL_PCI_SETUP;
|
||||
}
|
||||
93
board/freescale/t104xrdb/t104xrdb.c
Normal file
93
board/freescale/t104xrdb/t104xrdb.c
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <netdev.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <asm/fsl_portals.h>
|
||||
#include <asm/fsl_liodn.h>
|
||||
#include <fm_eth.h>
|
||||
|
||||
#include "t104xrdb.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
struct cpu_type *cpu = gd->arch.cpu;
|
||||
|
||||
printf("Board: %sRDB\n", cpu->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_FLASH_BASE
|
||||
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
|
||||
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
|
||||
|
||||
/*
|
||||
* Remap Boot flash region to caching-inhibited
|
||||
* so that flash can be erased properly.
|
||||
*/
|
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
|
||||
/* invalidate existing TLB entry for flash */
|
||||
disable_tlb(flash_esel);
|
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, flash_esel, BOOKE_PAGESZ_256M, 1);
|
||||
#endif
|
||||
set_liodns();
|
||||
#ifdef CONFIG_SYS_DPAA_QBMAN
|
||||
setup_portals();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
phys_addr_t base;
|
||||
phys_size_t size;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
base = getenv_bootm_low();
|
||||
size = getenv_bootm_size();
|
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
pci_of_setup(blob, bd);
|
||||
#endif
|
||||
|
||||
fdt_fixup_liodn(blob);
|
||||
|
||||
#ifdef CONFIG_HAS_FSL_DR_USB
|
||||
fdt_fixup_dr_usb(blob, bd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
fdt_fixup_fman_ethernet(blob);
|
||||
#endif
|
||||
}
|
||||
13
board/freescale/t104xrdb/t104xrdb.h
Normal file
13
board/freescale/t104xrdb/t104xrdb.h
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __T104x_RDB_H__
|
||||
#define __T104x_RDB_H__
|
||||
|
||||
void fdt_fixup_board_enet(void *blob);
|
||||
void pci_of_setup(void *blob, bd_t *bd);
|
||||
|
||||
#endif
|
||||
107
board/freescale/t104xrdb/tlb.c
Normal file
107
board/freescale/t104xrdb/tlb.c
Normal file
|
|
@ -0,0 +1,107 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* TLB 1 */
|
||||
/* *I*** - Covers boot page */
|
||||
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
|
||||
/*
|
||||
* *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
|
||||
* SRAM is at 0xfffc0000, it covered the 0xfffff000.
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_256K, 1),
|
||||
#else
|
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_4K, 1),
|
||||
#endif
|
||||
|
||||
/* *I*G* - CCSRBAR */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_16M, 1),
|
||||
|
||||
/* *I*G* - Flash, localbus */
|
||||
/* This will be changed to *I*G* after relocation to RAM. */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/* *I*G* - PCI */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_1G, 1),
|
||||
|
||||
/* *I*G* - PCI I/O */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_256K, 1),
|
||||
|
||||
/* Bman/Qman */
|
||||
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 5, BOOKE_PAGESZ_16M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
|
||||
CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 6, BOOKE_PAGESZ_16M, 1),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 7, BOOKE_PAGESZ_16M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
|
||||
CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 8, BOOKE_PAGESZ_16M, 1),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 9, BOOKE_PAGESZ_4M, 1),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_NAND_BASE
|
||||
/*
|
||||
* *I*G - NAND
|
||||
* entry 14 and 15 has been used hard coded, they will be disabled
|
||||
* in cpu_init_f, so we use entry 16 for nand.
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 10, BOOKE_PAGESZ_64K, 1),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_CPLD_BASE
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 11, BOOKE_PAGESZ_256K, 1),
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
|
|
@ -963,6 +963,8 @@ Active powerpc mpc85xx - freescale t4qds
|
|||
Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
|
||||
Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
|
||||
Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Naveen Burmi <NaveenBurmi@freescale.com>
|
||||
Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
|
||||
Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal@freescale.com>
|
||||
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de>
|
||||
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de>
|
||||
Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de>
|
||||
|
|
|
|||
|
|
@ -1,198 +0,0 @@
|
|||
Overview
|
||||
=========
|
||||
The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
|
||||
|
||||
The P1010 is a cost-effective, low-power, highly integrated host processor
|
||||
based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
|
||||
that addresses the requirements of several routing, gateways, storage, consumer,
|
||||
and industrial applications. Applications of interest include the main CPUs and
|
||||
I/O processors in network attached storage (NAS), the voice over IP (VoIP)
|
||||
router/gateway, and wireless LAN (WLAN) and industrial controllers.
|
||||
|
||||
The P1010RDB board features are as follows:
|
||||
Memory subsystem:
|
||||
- 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
|
||||
- 32 Mbyte NOR flash single-chip memory
|
||||
- 32 Mbyte NAND flash memory
|
||||
- 256 Kbit M24256 I2C EEPROM
|
||||
- 16 Mbyte SPI memory
|
||||
- I2C Board EEPROM 128x8 bit memory
|
||||
- SD/MMC connector to interface with the SD memory card
|
||||
Interfaces:
|
||||
- PCIe:
|
||||
- Lane0: x1 mini-PCIe slot
|
||||
- Lane1: x1 PCIe standard slot
|
||||
- SATA:
|
||||
- 1 internal SATA connector to 2.5" 160G SATA2 HDD
|
||||
- 1 eSATA connector to rear panel
|
||||
- 10/100/1000 BaseT Ethernet ports:
|
||||
- eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
|
||||
- eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
|
||||
- eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
|
||||
- USB 2.0 port:
|
||||
- x1 USB2.0 port: via an ULPI PHY to micro-AB connector
|
||||
- x1 USB2.0 poort via an internal PHY to micro-AB connector
|
||||
- FlexCAN ports:
|
||||
- x2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
|
||||
interface;
|
||||
- DUART interface:
|
||||
- DUART interface: supports two UARTs up to 115200 bps for
|
||||
console display
|
||||
- J45 connectors are used for these 2 UART ports.
|
||||
- TDM
|
||||
- 2 FXS ports connected via an external SLIC to the TDM
|
||||
interface. SLIC is controllled via SPI.
|
||||
- 1 FXO port connected via a relay to FXS for switchover to
|
||||
POTS
|
||||
Board connectors:
|
||||
- Mini-ITX power supply connector
|
||||
- JTAG/COP for debugging
|
||||
IEEE Std. 1588 signals for test and measurement
|
||||
Real-time clock on I2C bus
|
||||
POR
|
||||
- support critical POR setting changed via switch on board
|
||||
PCB
|
||||
- 6-layer routing (4-layer signals, 2-layer power and ground)
|
||||
|
||||
|
||||
Serial Port Configuration on P1010RDB
|
||||
=====================================
|
||||
Configure the serial port of the attached computer with the following values:
|
||||
-Data rate: 115200 bps
|
||||
-Number of data bits: 8
|
||||
-Parity: None
|
||||
-Number of Stop bits: 1
|
||||
-Flow Control: Hardware/None
|
||||
|
||||
|
||||
Settings of DIP-switch
|
||||
======================
|
||||
SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
|
||||
SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
|
||||
SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
|
||||
Note: 1 stands for 'on', 0 stands for 'off'
|
||||
|
||||
|
||||
Setting of hwconfig
|
||||
===================
|
||||
If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
|
||||
"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
|
||||
setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
|
||||
By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
|
||||
is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
|
||||
instead of to CAN/UART1.
|
||||
|
||||
|
||||
Build and burn u-boot to NOR flash
|
||||
==================================
|
||||
1. Build u-boot.bin image
|
||||
export ARCH=powerpc
|
||||
export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
|
||||
make P1010RDB_NOR
|
||||
|
||||
2. Burn u-boot.bin into NOR flash
|
||||
=> tftp $loadaddr $uboot
|
||||
=> protect off eff80000 +$filesize
|
||||
=> erase eff80000 +$filesize
|
||||
=> cp.b $loadaddr eff80000 $filesize
|
||||
|
||||
3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
|
||||
|
||||
|
||||
Alternate NOR bank
|
||||
============================
|
||||
1. Burn u-boot.bin into alternate NOR bank
|
||||
=> tftp $loadaddr $uboot
|
||||
=> protect off eef80000 +$filesize
|
||||
=> erase eef80000 +$filesize
|
||||
=> cp.b $loadaddr eef80000 $filesize
|
||||
|
||||
2. Switch to alternate NOR bank
|
||||
=> mw.b ffb00009 1
|
||||
=> reset
|
||||
or set SW1[8]= ON
|
||||
|
||||
SW1[8]= OFF: Upper bank used for booting start
|
||||
SW1[8]= ON: Lower bank used for booting start
|
||||
CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
|
||||
0 - boot from upper 4 sectors
|
||||
1 - boot from lower 4 sectors
|
||||
|
||||
|
||||
Build and burn u-boot to NAND flash
|
||||
===================================
|
||||
1. Build u-boot.bin image
|
||||
export ARCH=powerpc
|
||||
export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
|
||||
make P1010RDB_NAND
|
||||
|
||||
2. Burn u-boot-nand.bin into NAND flash
|
||||
=> tftp $loadaddr $uboot-nand
|
||||
=> nand erase 0 $filesize
|
||||
=> nand write $loadaddr 0 $filesize
|
||||
|
||||
3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
|
||||
|
||||
|
||||
|
||||
Build and burn u-boot to SPI flash
|
||||
==================================
|
||||
1. Build u-boot-spi.bin image
|
||||
make P1010RDB_SPIFLASH_config; make
|
||||
Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
|
||||
Download u-boot.bin to linux and you can find some config files
|
||||
under /usr/share such as config_xx.dat. Do below command:
|
||||
boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
|
||||
u-boot-spi.bin
|
||||
to generate u-boot-spi.bin.
|
||||
|
||||
2. Burn u-boot-spi.bin into SPI flash
|
||||
=> tftp $loadaddr $uboot-spi
|
||||
=> sf erase 0 100000
|
||||
=> sf write $loadaddr 0 $filesize
|
||||
|
||||
3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
|
||||
|
||||
|
||||
|
||||
CPLD POR setting registers
|
||||
==========================
|
||||
1. Set POR switch selection register (addr 0xFFB00011) to 0.
|
||||
2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
|
||||
proper values.
|
||||
If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
|
||||
switch command by I2C.
|
||||
3. Send reset command.
|
||||
After reset, the new POR setting will be implemented.
|
||||
|
||||
Two examples are given in below:
|
||||
Switch from NOR to NAND boot with default frequency:
|
||||
=> i2c dev 0
|
||||
=> i2c mw 18 1 f9
|
||||
=> i2c mw 18 3 f0
|
||||
=> mw.b ffb00011 0
|
||||
=> mw.b ffb00017 1
|
||||
=> reset
|
||||
Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
|
||||
=> i2c dev 0
|
||||
=> i2c mw 18 1 f1
|
||||
=> i2c mw 18 3 f0
|
||||
=> mw.b ffb00011 0
|
||||
=> mw.b ffb00014 2
|
||||
=> mw.b ffb00015 5
|
||||
=> mw.b ffb00016 3
|
||||
=> mw.b ffb00017 f
|
||||
=> reset
|
||||
|
||||
|
||||
Boot Linux from network using TFTP on P1010RDB
|
||||
==============================================
|
||||
Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
|
||||
=> tftp 1000000 uImage
|
||||
=> tftp 2000000 p1010rdb.dtb
|
||||
=> tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
|
||||
=> bootm 1000000 3000000 2000000
|
||||
|
||||
|
||||
Please contact your local field applications engineer or sales representative
|
||||
to obtain related documents, such as P1010-RDB User Guide for details.
|
||||
|
|
@ -26,6 +26,9 @@ obj-$(CONFIG_PPC_P4080) += p4080.o
|
|||
obj-$(CONFIG_PPC_P5020) += p5020.o
|
||||
obj-$(CONFIG_PPC_P5040) += p5040.o
|
||||
obj-$(CONFIG_PPC_T1040) += t1040.o
|
||||
obj-$(CONFIG_PPC_T1042) += t1040.o
|
||||
obj-$(CONFIG_PPC_T1020) += t1040.o
|
||||
obj-$(CONFIG_PPC_T1022) += t1040.o
|
||||
obj-$(CONFIG_PPC_T4240) += t4240.o
|
||||
obj-$(CONFIG_PPC_T4160) += t4240.o
|
||||
obj-$(CONFIG_PPC_B4420) += b4860.o
|
||||
|
|
|
|||
|
|
@ -32,6 +32,8 @@
|
|||
#ifdef CONFIG_RAMBOOT_PBL
|
||||
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
|
||||
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg
|
||||
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
|
||||
#endif
|
||||
|
||||
/* High Level Configuration Options */
|
||||
|
|
|
|||
690
include/configs/T1040RDB.h
Normal file
690
include/configs/T1040RDB.h
Normal file
|
|
@ -0,0 +1,690 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* T1040 RDB board configuration file
|
||||
*/
|
||||
#define CONFIG_T104xRDB
|
||||
#define CONFIG_T1040RDB
|
||||
#define CONFIG_PHYS_64BIT
|
||||
|
||||
#ifdef CONFIG_RAMBOOT_PBL
|
||||
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
|
||||
#endif
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE
|
||||
#define CONFIG_E500 /* BOOKE e500 family */
|
||||
#define CONFIG_E500MC /* BOOKE e500mc family */
|
||||
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
|
||||
#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
|
||||
#define CONFIG_MP /* support multiple processors */
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xeff80000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||
#define CONFIG_PCI /* Enable PCI/PCIE */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE
|
||||
#define CONFIG_PCIE1 /* PCIE controler 1 */
|
||||
#define CONFIG_PCIE2 /* PCIE controler 2 */
|
||||
#define CONFIG_PCIE3 /* PCIE controler 3 */
|
||||
#define CONFIG_PCIE4 /* PCIE controler 4 */
|
||||
|
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#ifdef CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
#else
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_NO_FLASH
|
||||
#if defined(CONFIG_SPIFLASH)
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SPI_BUS 0
|
||||
#define CONFIG_ENV_SPI_CS 0
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 10000000
|
||||
#define CONFIG_ENV_SPI_MODE 0
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
|
||||
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000
|
||||
#elif defined(CONFIG_SDCARD)
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_OFFSET (512 * 1105)
|
||||
#elif defined(CONFIG_NAND)
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
||||
#endif
|
||||
#else /* CONFIG_SYS_NO_FLASH */
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 100000000
|
||||
#define CONFIG_DDR_CLK_FREQ 66666666
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_SYS_CACHE_STASHING
|
||||
#define CONFIG_BACKSIDE_L2_CACHE
|
||||
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
#define CONFIG_DDR_ECC
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
||||
#endif
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
#define CONFIG_ADDR_MAP
|
||||
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00400000
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */
|
||||
|
||||
/*
|
||||
* Config the L3 Cache as L3 SRAM
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
|
||||
|
||||
#define CONFIG_SYS_DCSRBAR 0xf0000000
|
||||
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
||||
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_DDR_RAW_TIMING
|
||||
#define CONFIG_FSL_DDR3
|
||||
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
#define SPD_EEPROM_ADDRESS 0x51
|
||||
|
||||
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
|
||||
|
||||
/*
|
||||
* IFC Definitions
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xe8000000
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
|
||||
|
||||
#define CONFIG_SYS_NOR_CSPR_EXT (0xf)
|
||||
#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V)
|
||||
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
|
||||
/* NOR Flash Timing Params */
|
||||
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
|
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
|
||||
FTIM0_NOR_TEADC(0x5) | \
|
||||
FTIM0_NOR_TEAHC(0x5))
|
||||
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
|
||||
FTIM1_NOR_TRAD_NOR(0x1A) |\
|
||||
FTIM1_NOR_TSEQRAD_NOR(0x13))
|
||||
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
|
||||
FTIM2_NOR_TCH(0x4) | \
|
||||
FTIM2_NOR_TWPH(0x0E) | \
|
||||
FTIM2_NOR_TWP(0x1c))
|
||||
#define CONFIG_SYS_NOR_FTIM3 0x0
|
||||
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
|
||||
/* CPLD on IFC */
|
||||
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
|
||||
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
|
||||
#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
|
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_GPCM \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
|
||||
#define CONFIG_SYS_CSOR2 0x0
|
||||
/* CPLD Timing parameters for IFC CS2 */
|
||||
#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
|
||||
FTIM0_GPCM_TEADC(0x0e) | \
|
||||
FTIM0_GPCM_TEAHC(0x0e))
|
||||
#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
|
||||
FTIM1_GPCM_TRAD(0x1f))
|
||||
#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
|
||||
FTIM2_GPCM_TCH(0x0) | \
|
||||
FTIM2_GPCM_TWP(0x1f))
|
||||
#define CONFIG_SYS_CS2_FTIM3 0x0
|
||||
|
||||
/* NAND Flash on IFC */
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
#define CONFIG_SYS_NAND_BASE 0xff800000
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
|
||||
|
||||
#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
|
||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
||||
| CSPR_MSEL_NAND /* MSEL = NAND */ \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
|
||||
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
|
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
|
||||
| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
|
||||
| CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
|
||||
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
|
||||
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* ONFI NAND Flash mode0 Timing Params */
|
||||
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
|
||||
FTIM0_NAND_TWP(0x18) | \
|
||||
FTIM0_NAND_TWCHT(0x07) | \
|
||||
FTIM0_NAND_TWH(0x0a))
|
||||
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
|
||||
FTIM1_NAND_TWBE(0x39) | \
|
||||
FTIM1_NAND_TRR(0x0e) | \
|
||||
FTIM1_NAND_TRP(0x18))
|
||||
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
|
||||
FTIM2_NAND_TREH(0x0a) | \
|
||||
FTIM2_NAND_TWHRE(0x1e))
|
||||
#define CONFIG_SYS_NAND_FTIM3 0x0
|
||||
|
||||
#define CONFIG_SYS_NAND_DDR_LAW 11
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE
|
||||
#define CONFIG_CMD_NAND
|
||||
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
|
||||
|
||||
#if defined(CONFIG_NAND)
|
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
|
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
|
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
|
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
|
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#else
|
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
|
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
|
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
|
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
|
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
|
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#if defined(CONFIG_RAMBOOT_PBL)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
#define CONFIG_HWCONFIG
|
||||
|
||||
/* define to use L1 as initial stack */
|
||||
#define CONFIG_L1_INIT_RAM
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
|
||||
/* The assembler doesn't like typecast */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
|
||||
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
|
||||
|
||||
/* Serial Port - controlled on board with jumper J8
|
||||
* open - index 2
|
||||
* shorted - index 1
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
|
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
|
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
|
||||
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS
|
||||
|
||||
/* new uImage format support */
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
|
||||
|
||||
/* I2C bus multiplexer */
|
||||
#define I2C_MUX_PCA_ADDR 0x70
|
||||
#define I2C_MUX_CH_DEFAULT 0x8
|
||||
|
||||
|
||||
/*
|
||||
* eSPI - Enhanced SPI
|
||||
*/
|
||||
#define CONFIG_FSL_ESPI
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SF_DEFAULT_SPEED 10000000
|
||||
#define CONFIG_SF_DEFAULT_MODE 0
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
|
||||
#ifdef CONFIG_PCIE1
|
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
||||
#endif
|
||||
|
||||
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
|
||||
#ifdef CONFIG_PCIE2
|
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
|
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
|
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
|
||||
#endif
|
||||
|
||||
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
|
||||
#ifdef CONFIG_PCIE3
|
||||
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
|
||||
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
|
||||
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
|
||||
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
|
||||
#endif
|
||||
|
||||
/* controller 4, Base address 203000 */
|
||||
#ifdef CONFIG_PCIE4
|
||||
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
|
||||
#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
|
||||
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
|
||||
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
|
||||
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
|
||||
#endif
|
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_E1000
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/* SATA */
|
||||
#define CONFIG_FSL_SATA_V2
|
||||
#ifdef CONFIG_FSL_SATA_V2
|
||||
#define CONFIG_LIBATA
|
||||
#define CONFIG_FSL_SATA
|
||||
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 1
|
||||
#define CONFIG_SATA1
|
||||
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
|
||||
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
|
||||
|
||||
#define CONFIG_LBA48
|
||||
#define CONFIG_CMD_SATA
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_CMD_EXT2
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_HAS_FSL_DR_USB
|
||||
|
||||
#ifdef CONFIG_HAS_FSL_DR_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_CMD_EXT2
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_MMC
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif
|
||||
|
||||
/* Qman/Bman */
|
||||
#ifndef CONFIG_NOBQFMAN
|
||||
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_SYS_DPAA_PME
|
||||
|
||||
/* Default address of microcode for the Linux Fman driver */
|
||||
#if defined(CONFIG_SPIFLASH)
|
||||
/*
|
||||
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
|
||||
* env, so we got 0x110000.
|
||||
*/
|
||||
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
|
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
|
||||
#elif defined(CONFIG_SDCARD)
|
||||
/*
|
||||
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
|
||||
* about 545KB (1089 blocks), Env is stored after the image, and the env size is
|
||||
* 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
|
||||
*/
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
|
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
|
||||
#elif defined(CONFIG_NAND)
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
|
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#else
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
|
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
|
||||
#endif
|
||||
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
|
||||
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
|
||||
#endif /* CONFIG_NOBQFMAN */
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_FMAN_ENET
|
||||
#define CONFIG_PHY_VITESSE
|
||||
#define CONFIG_PHY_REALTEK
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
|
||||
#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
|
||||
#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
|
||||
#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_ETHPRIME "FM1@DTSEC1"
|
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_ERRATA
|
||||
#define CONFIG_CMD_GREPENV
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_REGINFO
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_NET
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
|
||||
|
||||
/* default location for tftp and bootm */
|
||||
#define CONFIG_LOADADDR 1000000
|
||||
|
||||
#define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define __USB_PHY_TYPE utmi
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
|
||||
"bank_intlv=cs0_cs1;" \
|
||||
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot && " \
|
||||
"protect off $ubootaddr +$filesize && " \
|
||||
"erase $ubootaddr +$filesize && " \
|
||||
"cp.b $loadaddr $ubootaddr $filesize && " \
|
||||
"protect on $ubootaddr +$filesize && " \
|
||||
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=t1040rdb/ramdisk.uboot\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=t1040rdb/t1040rdb.dtb\0" \
|
||||
"bdev=sda3\0" \
|
||||
"c=ffe\0"
|
||||
|
||||
#define CONFIG_LINUX \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"setenv ramdiskaddr 0x02000000;" \
|
||||
"setenv fdtaddr 0x00c00000;" \
|
||||
"setenv loadaddr 0x1000000;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_HDBOOT \
|
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_LINUX
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
#include <asm/fsl_secure_boot.h>
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
694
include/configs/T1042RDB_PI.h
Normal file
694
include/configs/T1042RDB_PI.h
Normal file
|
|
@ -0,0 +1,694 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* T1042RDB_PI board configuration file
|
||||
*/
|
||||
#define CONFIG_T104xRDB
|
||||
#define CONFIG_T1042RDB_PI
|
||||
#define CONFIG_PHYS_64BIT
|
||||
|
||||
#ifdef CONFIG_RAMBOOT_PBL
|
||||
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
|
||||
#endif
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE
|
||||
#define CONFIG_E500 /* BOOKE e500 family */
|
||||
#define CONFIG_E500MC /* BOOKE e500mc family */
|
||||
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
|
||||
#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
|
||||
#define CONFIG_MP /* support multiple processors */
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xeff80000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||
#define CONFIG_PCI /* Enable PCI/PCIE */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE
|
||||
#define CONFIG_PCIE1 /* PCIE controler 1 */
|
||||
#define CONFIG_PCIE2 /* PCIE controler 2 */
|
||||
#define CONFIG_PCIE3 /* PCIE controler 3 */
|
||||
#define CONFIG_PCIE4 /* PCIE controler 4 */
|
||||
|
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#ifdef CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
#else
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_NO_FLASH
|
||||
#if defined(CONFIG_SPIFLASH)
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SPI_BUS 0
|
||||
#define CONFIG_ENV_SPI_CS 0
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 10000000
|
||||
#define CONFIG_ENV_SPI_MODE 0
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
|
||||
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000
|
||||
#elif defined(CONFIG_SDCARD)
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_OFFSET (512 * 1105)
|
||||
#elif defined(CONFIG_NAND)
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
||||
#endif
|
||||
#else /* CONFIG_SYS_NO_FLASH */
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 100000000
|
||||
#define CONFIG_DDR_CLK_FREQ 66666666
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_SYS_CACHE_STASHING
|
||||
#define CONFIG_BACKSIDE_L2_CACHE
|
||||
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
#define CONFIG_DDR_ECC
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
||||
#endif
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
#define CONFIG_ADDR_MAP
|
||||
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00400000
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */
|
||||
|
||||
/*
|
||||
* Config the L3 Cache as L3 SRAM
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
|
||||
|
||||
#define CONFIG_SYS_DCSRBAR 0xf0000000
|
||||
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
||||
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_DDR_RAW_TIMING
|
||||
#define CONFIG_FSL_DDR3
|
||||
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
#define SPD_EEPROM_ADDRESS 0x51
|
||||
|
||||
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
|
||||
|
||||
/*
|
||||
* IFC Definitions
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xe8000000
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
|
||||
|
||||
#define CONFIG_SYS_NOR_CSPR_EXT (0xf)
|
||||
#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V)
|
||||
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
|
||||
/* NOR Flash Timing Params */
|
||||
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
|
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
|
||||
FTIM0_NOR_TEADC(0x5) | \
|
||||
FTIM0_NOR_TEAHC(0x5))
|
||||
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
|
||||
FTIM1_NOR_TRAD_NOR(0x1A) |\
|
||||
FTIM1_NOR_TSEQRAD_NOR(0x13))
|
||||
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
|
||||
FTIM2_NOR_TCH(0x4) | \
|
||||
FTIM2_NOR_TWPH(0x0E) | \
|
||||
FTIM2_NOR_TWP(0x1c))
|
||||
#define CONFIG_SYS_NOR_FTIM3 0x0
|
||||
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
|
||||
/* CPLD on IFC */
|
||||
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
|
||||
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
|
||||
#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
|
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_GPCM \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
|
||||
#define CONFIG_SYS_CSOR2 0x0
|
||||
/* CPLD Timing parameters for IFC CS2 */
|
||||
#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
|
||||
FTIM0_GPCM_TEADC(0x0e) | \
|
||||
FTIM0_GPCM_TEAHC(0x0e))
|
||||
#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
|
||||
FTIM1_GPCM_TRAD(0x1f))
|
||||
#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
|
||||
FTIM2_GPCM_TCH(0x0) | \
|
||||
FTIM2_GPCM_TWP(0x1f))
|
||||
#define CONFIG_SYS_CS2_FTIM3 0x0
|
||||
|
||||
/* NAND Flash on IFC */
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
#define CONFIG_SYS_NAND_BASE 0xff800000
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
|
||||
|
||||
#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
|
||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
||||
| CSPR_MSEL_NAND /* MSEL = NAND */ \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
|
||||
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
|
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
|
||||
| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
|
||||
| CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
|
||||
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
|
||||
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* ONFI NAND Flash mode0 Timing Params */
|
||||
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
|
||||
FTIM0_NAND_TWP(0x18) | \
|
||||
FTIM0_NAND_TWCHT(0x07) | \
|
||||
FTIM0_NAND_TWH(0x0a))
|
||||
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
|
||||
FTIM1_NAND_TWBE(0x39) | \
|
||||
FTIM1_NAND_TRR(0x0e) | \
|
||||
FTIM1_NAND_TRP(0x18))
|
||||
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
|
||||
FTIM2_NAND_TREH(0x0a) | \
|
||||
FTIM2_NAND_TWHRE(0x1e))
|
||||
#define CONFIG_SYS_NAND_FTIM3 0x0
|
||||
|
||||
#define CONFIG_SYS_NAND_DDR_LAW 11
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE
|
||||
#define CONFIG_CMD_NAND
|
||||
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
|
||||
|
||||
#if defined(CONFIG_NAND)
|
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
|
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
|
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
|
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
|
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#else
|
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
|
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
|
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
|
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
|
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
|
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#if defined(CONFIG_RAMBOOT_PBL)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
#define CONFIG_HWCONFIG
|
||||
|
||||
/* define to use L1 as initial stack */
|
||||
#define CONFIG_L1_INIT_RAM
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
|
||||
/* The assembler doesn't like typecast */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
|
||||
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
|
||||
|
||||
/* Serial Port - controlled on board with jumper J8
|
||||
* open - index 2
|
||||
* shorted - index 1
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
|
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
|
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
|
||||
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS
|
||||
|
||||
/* new uImage format support */
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
|
||||
|
||||
/* I2C bus multiplexer */
|
||||
#define I2C_MUX_PCA_ADDR 0x70
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#define RTC
|
||||
#define CONFIG_RTC_DS1337 1
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
|
||||
/*DVI encoder*/
|
||||
#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
|
||||
|
||||
/*
|
||||
* eSPI - Enhanced SPI
|
||||
*/
|
||||
#define CONFIG_FSL_ESPI
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SF_DEFAULT_SPEED 10000000
|
||||
#define CONFIG_SF_DEFAULT_MODE 0
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
|
||||
#ifdef CONFIG_PCIE1
|
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
||||
#endif
|
||||
|
||||
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
|
||||
#ifdef CONFIG_PCIE2
|
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
|
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
|
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
|
||||
#endif
|
||||
|
||||
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
|
||||
#ifdef CONFIG_PCIE3
|
||||
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
|
||||
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
|
||||
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
|
||||
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
|
||||
#endif
|
||||
|
||||
/* controller 4, Base address 203000 */
|
||||
#ifdef CONFIG_PCIE4
|
||||
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
|
||||
#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
|
||||
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
|
||||
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
|
||||
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
|
||||
#endif
|
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_E1000
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/* SATA */
|
||||
#define CONFIG_FSL_SATA_V2
|
||||
#ifdef CONFIG_FSL_SATA_V2
|
||||
#define CONFIG_LIBATA
|
||||
#define CONFIG_FSL_SATA
|
||||
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 1
|
||||
#define CONFIG_SATA1
|
||||
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
|
||||
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
|
||||
|
||||
#define CONFIG_LBA48
|
||||
#define CONFIG_CMD_SATA
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_CMD_EXT2
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_HAS_FSL_DR_USB
|
||||
|
||||
#ifdef CONFIG_HAS_FSL_DR_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_CMD_EXT2
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_MMC
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif
|
||||
|
||||
/* Qman/Bman */
|
||||
#ifndef CONFIG_NOBQFMAN
|
||||
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_SYS_DPAA_PME
|
||||
|
||||
/* Default address of microcode for the Linux Fman driver */
|
||||
#if defined(CONFIG_SPIFLASH)
|
||||
/*
|
||||
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
|
||||
* env, so we got 0x110000.
|
||||
*/
|
||||
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
|
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
|
||||
#elif defined(CONFIG_SDCARD)
|
||||
/*
|
||||
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
|
||||
* about 545KB (1089 blocks), Env is stored after the image, and the env size is
|
||||
* 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
|
||||
*/
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
|
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
|
||||
#elif defined(CONFIG_NAND)
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
|
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#else
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
|
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
|
||||
#endif
|
||||
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
|
||||
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
|
||||
#endif /* CONFIG_NOBQFMAN */
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_FMAN_ENET
|
||||
#define CONFIG_PHY_VITESSE
|
||||
#define CONFIG_PHY_REALTEK
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_ETHPRIME "FM1@DTSEC1"
|
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_ERRATA
|
||||
#define CONFIG_CMD_GREPENV
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_REGINFO
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_NET
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
|
||||
|
||||
/* default location for tftp and bootm */
|
||||
#define CONFIG_LOADADDR 1000000
|
||||
|
||||
#define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define __USB_PHY_TYPE utmi
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
|
||||
"bank_intlv=cs0_cs1;" \
|
||||
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot && " \
|
||||
"protect off $ubootaddr +$filesize && " \
|
||||
"erase $ubootaddr +$filesize && " \
|
||||
"cp.b $loadaddr $ubootaddr $filesize && " \
|
||||
"protect on $ubootaddr +$filesize && " \
|
||||
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=t1040rdb_pi/ramdisk.uboot\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=t1040rdb_pi/t1040rdb_pi.dtb\0" \
|
||||
"bdev=sda3\0" \
|
||||
"c=ffe\0"
|
||||
|
||||
#define CONFIG_LINUX \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"setenv ramdiskaddr 0x02000000;" \
|
||||
"setenv fdtaddr 0x00c00000;" \
|
||||
"setenv loadaddr 0x1000000;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_HDBOOT \
|
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_LINUX
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
#include <asm/fsl_secure_boot.h>
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in a new issue