From 0df5b4e38f02b5f9b5b1410dac15ffb8f937e4f4 Mon Sep 17 00:00:00 2001 From: John Rigby Date: Wed, 7 Apr 2010 23:30:09 -0600 Subject: [PATCH 1/9] MX25 print arm clock instead of mpllclk on boot Replace call to imx_get_mpllclk with imx_get_armclk to show frequency of ARM core instead of mpll internal bus in print_cpuinfo. Signed-off-by: John Rigby CC: Stefano Babic --- arch/arm/cpu/arm926ejs/mx25/generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index 694841dd10..b80a389ed9 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -111,7 +111,7 @@ int print_cpuinfo (void) char buf[32]; printf ("CPU: Freescale i.MX25 at %s MHz\n\n", - strmhz (buf, imx_get_mpllclk ())); + strmhz (buf, imx_get_armclk ())); return 0; } #endif From 6686f10dd5ac791238d8c8afa1bce264083fc498 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 13 Apr 2010 12:38:22 +0200 Subject: [PATCH 2/9] mkimage: correct spelling error in imximage Signed-off-by: Stefano Babic --- tools/imximage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/imximage.c b/tools/imximage.c index df2d8c4d7b..39f89c2b93 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -36,7 +36,7 @@ * Supported commands for configuration file */ static table_entry_t imximage_cmds[] = { - {CMD_BOOT_FROM, "BOOT_FROM", "boot comand", }, + {CMD_BOOT_FROM, "BOOT_FROM", "boot command", }, {CMD_DATA, "DATA", "Reg Write Data", }, {-1, "", "", }, }; From 989359b3182cdd998b58c8cca92717263c8d513d Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 13 Apr 2010 12:38:43 +0200 Subject: [PATCH 3/9] mx51evk: correct list of possible BOOT_FROM values Signed-off-by: Stefano Babic --- board/freescale/mx51evk/imximage.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mx51evk/imximage.cfg b/board/freescale/mx51evk/imximage.cfg index db09913f49..a875e8ff55 100644 --- a/board/freescale/mx51evk/imximage.cfg +++ b/board/freescale/mx51evk/imximage.cfg @@ -26,7 +26,7 @@ # The syntax is taken as close as possible with the kwbimage # Boot Device : one of -# spi_flash, nand, onenand, sd_card +# spi, sd (the board has no nand neither onenand) BOOT_FROM spi From 83366790317042bf61c3260c7a61fd8a8fbf5db9 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 13 Apr 2010 12:07:00 +0200 Subject: [PATCH 4/9] MX31: add accessor function to get a gpio The patch adds an accessor function to get the value of a gpio. Signed-off-by: Stefano Babic --- arch/arm/include/asm/arch-mx31/mx31.h | 5 +++++ drivers/gpio/mx31_gpio.c | 15 +++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/include/asm/arch-mx31/mx31.h b/arch/arm/include/asm/arch-mx31/mx31.h index 3cc4b350b6..f702d260f1 100644 --- a/arch/arm/include/asm/arch-mx31/mx31.h +++ b/arch/arm/include/asm/arch-mx31/mx31.h @@ -37,12 +37,17 @@ enum mx31_gpio_direction { extern int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction); extern void mx31_gpio_set(unsigned int gpio, unsigned int value); +extern int mx31_gpio_get(unsigned int gpio); #else static inline int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction) { return 1; } +static inline int mx31_gpio_get(unsigned int gpio) +{ + return 1; +} static inline void mx31_gpio_set(unsigned int gpio, unsigned int value) { } diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mx31_gpio.c index 737aafa822..b07f038156 100644 --- a/drivers/gpio/mx31_gpio.c +++ b/drivers/gpio/mx31_gpio.c @@ -71,3 +71,18 @@ void mx31_gpio_set(unsigned int gpio, unsigned int value) l &= ~(1 << gpio); __REG(gpio_ports[port] + GPIO_DR) = l; } + +int mx31_gpio_get(unsigned int gpio) +{ + unsigned int port = gpio >> 5; + u32 l; + + if (port >= ARRAY_SIZE(gpio_ports)) + return -1; + + gpio &= 0x1f; + + l = (__REG(gpio_ports[port] + GPIO_DR) >> gpio) & 0x01; + + return l; +} From 89b4e39e1eb6be80ce248c991480dc35188c5a99 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 29 Mar 2010 15:56:10 +0200 Subject: [PATCH 5/9] MX31: add pin definitions for NAND controller Add pin definitions ralted to the NAND controller to be used to set up the pin multiplexer. Signed-off-by: Stefano Babic --- arch/arm/include/asm/arch-mx31/mx31-regs.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/include/asm/arch-mx31/mx31-regs.h b/arch/arm/include/asm/arch-mx31/mx31-regs.h index 6f6e9a4048..c59255e24b 100644 --- a/arch/arm/include/asm/arch-mx31/mx31-regs.h +++ b/arch/arm/include/asm/arch-mx31/mx31-regs.h @@ -207,6 +207,15 @@ struct clock_control_regs { #define MUX_CTL_CSPI1_SS0 0x8e #define MUX_CTL_CSPI1_SS1 0x8f +#define MUX_CTL_NFC_WP 0xD0 +#define MUX_CTL_NFC_CE 0xD1 +#define MUX_CTL_NFC_RB 0xD2 +#define MUX_CTL_NFC_WE 0xD4 +#define MUX_CTL_NFC_RE 0xD5 +#define MUX_CTL_NFC_ALE 0xD6 +#define MUX_CTL_NFC_CLE 0xD7 + + /* * Helper macros for the MUX_[contact name]__[pin function] macros */ From 3f3c7d3d920e27fa8288a3577762bd2d686187ce Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 29 Mar 2010 16:43:39 +0200 Subject: [PATCH 6/9] MX31: Add support for NAND to QONG board The NAND device is connected to the FPGA of the QONG board and not to the NFC controller. For this reason, the FPGA must be set and initialized before accessing to the NAND itself. Signed-off-by: Stefano Babic --- board/davedenx/qong/qong.c | 93 +++++++++++++++++++++++++-------- board/davedenx/qong/qong_fpga.h | 4 +- include/configs/qong.h | 27 ++++++++++ 3 files changed, 101 insertions(+), 23 deletions(-) diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index b801150036..e73d26b8f6 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "qong_fpga.h" DECLARE_GLOBAL_DATA_PTR; @@ -38,6 +39,15 @@ int dram_init (void) return 0; } +static void qong_fpga_reset(void) +{ + mx31_gpio_set(QONG_FPGA_RST_PIN, 0); + udelay(30); + mx31_gpio_set(QONG_FPGA_RST_PIN, 1); + + udelay(300); +} + int board_init (void) { /* Chip selects */ @@ -101,6 +111,15 @@ int board_init (void) mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO)); mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO)); + + /* FPGA reset Pin */ + /* rstn = 0 */ + mx31_gpio_set(QONG_FPGA_RST_PIN, 0); + mx31_gpio_direction(QONG_FPGA_RST_PIN, MX31_GPIO_DIRECTION_OUT); + + /* set interrupt pin as input */ + mx31_gpio_direction(QONG_FPGA_IRQ_PIN, MX31_GPIO_DIRECTION_IN); + #endif /* setup pins for UART1 */ @@ -127,32 +146,11 @@ int misc_init_r (void) #ifdef CONFIG_QONG_FPGA u32 tmp; - /* FPGA reset */ - /* rstn = 0 */ - tmp = __REG(GPIO2_BASE + GPIO_DR); - tmp &= (~(1 << QONG_FPGA_RST_PIN)); - __REG(GPIO2_BASE + GPIO_DR) = tmp; - /* set the GPIO as output */ - tmp = __REG(GPIO2_BASE + GPIO_GDIR); - tmp |= (1 << QONG_FPGA_RST_PIN); - __REG(GPIO2_BASE + GPIO_GDIR) = tmp; - /* wait */ - udelay(30); - /* rstn = 1 */ - tmp = __REG(GPIO2_BASE + GPIO_DR); - tmp |= (1 << QONG_FPGA_RST_PIN); - __REG(GPIO2_BASE + GPIO_DR) = tmp; - /* set interrupt pin as input */ - __REG(GPIO2_BASE + GPIO_GDIR) = tmp | (1 << QONG_FPGA_IRQ_PIN); - /* wait while the FPGA starts */ - udelay(300); - tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION; printf("FPGA: "); printf("version register = %u.%u.%u\n", (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF); #endif - return 0; } @@ -164,3 +162,56 @@ int board_eth_init(bd_t *bis) return 0; #endif } + +#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT) +static void board_nand_setup(void) +{ + + /* CS3: NAND 8-bit */ + __REG(CSCR_U(3)) = 0x00004f00; + __REG(CSCR_L(3)) = 0x20013b31; + __REG(CSCR_A(3)) = 0x00020800; + __REG(IOMUXC_GPR) |= 1 << 13; + + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO)); + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO)); + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO)); + + /* Make sure to reset the fpga else you cannot access NAND */ + qong_fpga_reset(); + + /* Enable NAND flash */ + mx31_gpio_set(15, 1); + mx31_gpio_set(14, 1); + mx31_gpio_direction(15, MX31_GPIO_DIRECTION_OUT); + mx31_gpio_direction(16, MX31_GPIO_DIRECTION_IN); + mx31_gpio_direction(14, MX31_GPIO_DIRECTION_IN); + mx31_gpio_set(15, 0); + +} + +int qong_nand_rdy(void *chip) +{ + udelay(1); + return mx31_gpio_get(16); +} + +void qong_nand_select_chip(struct mtd_info *mtd, int chip) +{ + if (chip >= 0) + mx31_gpio_set(15, 0); + else + mx31_gpio_set(15, 1); + +} + +void qong_nand_plat_init(void *chip) +{ + struct nand_chip *nand = (struct nand_chip *)chip; + nand->chip_delay = 20; + nand->select_chip = qong_nand_select_chip; + nand->options &= ~NAND_BUSWIDTH_16; + board_nand_setup(); +} + +#endif diff --git a/board/davedenx/qong/qong_fpga.h b/board/davedenx/qong/qong_fpga.h index e8042b131e..4e11f5a1cf 100644 --- a/board/davedenx/qong/qong_fpga.h +++ b/board/davedenx/qong/qong_fpga.h @@ -33,8 +33,8 @@ #define QONG_FPGA_TMS_PIN 25 #define QONG_FPGA_TDI_PIN 8 #define QONG_FPGA_TDO_PIN 7 -#define QONG_FPGA_RST_PIN 16 -#define QONG_FPGA_IRQ_PIN 8 +#define QONG_FPGA_RST_PIN 48 +#define QONG_FPGA_IRQ_PIN 40 #endif #endif /* QONG_FPGA_H */ diff --git a/include/configs/qong.h b/include/configs/qong.h index 64d0214e27..9566a6833a 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -52,6 +52,8 @@ #define CONFIG_MXC_UART 1 #define CONFIG_SYS_MX31_UART1 1 +#define CONFIG_MX31_GPIO + /* FPGA */ #define CONFIG_QONG_FPGA 1 #define CONFIG_FPGA_BASE (CS1_BASE) @@ -85,6 +87,7 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_MII #define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_NAND /* * You can compile in a MAC address and your custom net settings by using @@ -177,6 +180,30 @@ #define PHYS_SDRAM_1 CSD0_BASE #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ +/* + * NAND driver + */ + +#ifndef __ASSEMBLY__ +extern void qong_nand_plat_init(void *chip); +extern int qong_nand_rdy(void *chip); +#endif +#define CONFIG_NAND_PLAT +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CS3_BASE +#define NAND_PLAT_INIT() qong_nand_plat_init(nand) + +#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24)) +#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23)) +#define QONG_NAND_WRITE(addr, cmd) \ + do { \ + __REG8(addr) = cmd; \ + } while (0) + +#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd) +#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd) +#define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip)) + /*----------------------------------------------------------------------- * FLASH and environment organization */ From 41985bb74919e7e0c2ce04a9da4e4cb7d522daf9 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 31 Mar 2010 10:27:47 +0200 Subject: [PATCH 7/9] MX31: Support 128MB RAM on QONG module The QONG module can be downsized and delivered with 128MB instead of 256MB. The patch adds run time support for the two different memory configurations. Signed-off-by: Stefano Babic --- arch/arm/include/asm/arch-mx31/mx31-regs.h | 6 + board/davedenx/qong/lowlevel_init.S | 130 +++++++++++++++------ 2 files changed, 103 insertions(+), 33 deletions(-) diff --git a/arch/arm/include/asm/arch-mx31/mx31-regs.h b/arch/arm/include/asm/arch-mx31/mx31-regs.h index c59255e24b..d72585c8a0 100644 --- a/arch/arm/include/asm/arch-mx31/mx31-regs.h +++ b/arch/arm/include/asm/arch-mx31/mx31-regs.h @@ -303,4 +303,10 @@ struct clock_control_regs { */ #define NFC_BASE_ADDR 0xB8000000 +/* + * Internal RAM (16KB) + */ +#define IRAM_BASE_ADDR 0x1FFFC000 +#define IRAM_SIZE (16 * 1024) + #endif /* __ASM_ARCH_MX31_REGS_H */ diff --git a/board/davedenx/qong/lowlevel_init.S b/board/davedenx/qong/lowlevel_init.S index 198dd76b8a..80bed92329 100644 --- a/board/davedenx/qong/lowlevel_init.S +++ b/board/davedenx/qong/lowlevel_init.S @@ -42,6 +42,27 @@ bcs 1b .endm +.macro SETUP_RAM cfg, ctl + /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */ + REG 0xB8001010, 0x00000004 + ldr r3, =\cfg + ldr r2, =WEIM_ESDCFG0 + str r3, [r2] + REG 0xB8001000, 0x92100000 + REG 0x80000f00, 0x12344321 + REG 0xB8001000, 0xa2100000 + REG 0x80000000, 0x12344321 + REG 0x80000000, 0x12344321 + REG 0xB8001000, 0xb2100000 + REG8 0x80000033, 0xda + REG8 0x81000000, 0xff + ldr r3, =\ctl + ldr r2, =WEIM_ESDCTL0 + str r3, [r2] + REG 0x80000000, 0xDEADBEEF + REG 0xB8001010, 0x0000000c + +.endm /* RedBoot: To support 133MHz DDR */ .macro init_drive_strength /* @@ -130,43 +151,86 @@ lowlevel_init: /* Default: 1, 4, 12, 1 */ REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) - /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */ - REG 0xB8001010, 0x00000004 - REG 0xB8001004, ((3 << 21) | /* tXP */ \ - (0 << 20) | /* tWTR */ \ - (2 << 18) | /* tRP */ \ - (1 << 16) | /* tMRD */ \ - (0 << 15) | /* tWR */ \ - (5 << 12) | /* tRAS */ \ - (1 << 10) | /* tRRD */ \ - (3 << 8) | /* tCAS */ \ - (2 << 4) | /* tRCD */ \ - (7 << 0) /* tRC */ ) - REG 0xB8001000, 0x92100000 - REG 0x80000f00, 0x12344321 - REG 0xB8001000, 0xa2100000 - REG 0x80000000, 0x12344321 - REG 0x80000000, 0x12344321 - REG 0xB8001000, 0xb2100000 - REG8 0x80000033, 0xda - REG8 0x81000000, 0xff - REG 0xB8001000, ((1 << 31) | \ - (0 << 28) | \ - (0 << 27) | \ - (3 << 24) | /* 14 rows */ \ - (2 << 20) | /* 10 cols */ \ - (2 << 16) | \ - (4 << 13) | /* 3.91us (64ms/16384) */ \ - (0 << 10) | \ - (0 << 8) | \ - (1 << 7) | \ - (0 << 0)) - REG 0x80000000, 0xDEADBEEF - REG 0xB8001010, 0x0000000c +check_ddr_module: +/* Set stackpointer in internal RAM to call get_ram_size */ + ldr sp, =(IRAM_BASE_ADDR + IRAM_SIZE - 16) + stmfd sp!, {r0-r11, ip, lr} + mov ip, lr /* save link reg across call */ + + ldr r0,=0x08000000 + SETUP_RAM ESDCFG0_256MB, ESDCTL0_256MB + ldr r0,=0x80000000 + ldr r1,=0x10000000 + bl get_ram_size + ldr r1,=0x10000000 + cmp r0,r1 + beq restore_regs + SETUP_RAM ESDCFG0_128MB, ESDCTL0_128MB + ldr r0,=0x80000000 + ldr r1,=0x08000000 + bl get_ram_size + ldr r1,=0x08000000 + cmp r0,r1 + beq restore_regs + +restore_regs: + ldmfd sp!, {r0-r11, ip, lr} + mov lr, ip /* restore link reg */ mov pc, lr + MPCTL_PARAM_399: .word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0)) UPCTL_PARAM_240: .word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3 << 0)) + + .equ ESDCFG0_128MB, \ + (0 << 21) + /* tXP */ \ + (1 << 20) + /* tWTR */ \ + (2 << 18) + /* tRP */ \ + (1 << 16) + /* tMRD */ \ + (0 << 15) + /* tWR */ \ + (5 << 12) + /* tRAS */ \ + (1 << 10) + /* tRRD */ \ + (3 << 8) + /* tCAS */ \ + (2 << 4) + /* tRCD */ \ + (0x0F << 0) /* tRC */ + + .equ ESDCTL0_128MB, \ + (1 << 31) + /* enable */ \ + (0 << 28) + /* mode */ \ + (0 << 27) + /* supervisor protect */ \ + (2 << 24) + /* 13 rows */ \ + (2 << 20) + /* 10 cols */ \ + (2 << 16) + /* 32 bit */ \ + (3 << 13) + /* 7.81us (64ms/8192) */ \ + (0 << 10) + /* power down timer */ \ + (0 << 8) + /* full page */ \ + (1 << 7) + /* burst length */ \ + (0 << 0) /* precharge timer */ + + .equ ESDCFG0_256MB, \ + (3 << 21) + /* tXP */ \ + (0 << 20) + /* tWTR */ \ + (2 << 18) + /* tRP */ \ + (1 << 16) + /* tMRD */ \ + (0 << 15) + /* tWR */ \ + (5 << 12) + /* tRAS */ \ + (1 << 10) + /* tRRD */ \ + (3 << 8) + /* tCAS */ \ + (2 << 4) + /* tRCD */ \ + (7 << 0) /* tRC */ + + .equ ESDCTL0_256MB, \ + (1 << 31) + \ + (0 << 28) + \ + (0 << 27) + \ + (3 << 24) + /* 14 rows */ \ + (2 << 20) + /* 10 cols */ \ + (2 << 16) + \ + (4 << 13) + /* 3.91us (64ms/16384) */ \ + (0 << 10) + \ + (0 << 8) + \ + (1 << 7) + \ + (0 << 0) From 0bab9d666c2103ac16fda3120e38c56f4a56bd2e Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 8 Apr 2010 17:23:52 +0200 Subject: [PATCH 8/9] MX31: Add UBI support to QONG module The UBI/UBIFS support is added to the QONG module. Signed-off-by: Stefano Babic --- include/configs/qong.h | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/include/configs/qong.h b/include/configs/qong.h index 9566a6833a..178c8e7974 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -41,7 +41,7 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_SIZE 128 @@ -86,7 +86,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_NET #define CONFIG_CMD_MII -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NAND /* @@ -218,7 +217,7 @@ extern int qong_nand_rdy(void *chip); #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) /* Address and size of Redundant Environment Sector */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) @@ -237,9 +236,15 @@ extern int qong_nand_rdy(void *chip); #define CONFIG_SYS_FLASH_PROTECTION 1 /* - * JFFS2 partitions + * Filesystem */ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_PARTITIONS #define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=physmap-flash.0" From 655ef2595244346744f5e790f7b103d0b9c9d110 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 13 Apr 2010 12:19:06 +0200 Subject: [PATCH 9/9] MX31: Removed erroneous board name from QONG QONG is a module that can be installed on several boards, not only on the QONG-EVB manufactured by Dave srl. Signed-off-by: Stefano Babic --- board/davedenx/qong/qong.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index e73d26b8f6..eb9218ec50 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -137,7 +137,7 @@ int board_init (void) int checkboard (void) { - printf("Board: DAVE/DENX QongEVB-LITE\n"); + printf("Board: DAVE/DENX Qong\n"); return 0; }