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arm: socfpga: Add support for Denali NAND controller
Add common configuration bits for the Denali NAND controller and also support for using it as a boot device in SPL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
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1 changed files with 23 additions and 0 deletions
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@ -160,6 +160,19 @@
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#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
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#endif
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/*
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* NAND Support
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*/
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#ifdef CONFIG_NAND_DENALI
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_MAX_CHIPS 1
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_NAND_DENALI_ECC_SIZE 512
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#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
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#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
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#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
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#endif
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/*
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* I2C support
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*/
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@ -338,6 +351,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
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#ifdef CONFIG_DM_SPI
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#define CONFIG_SPL_SPI_SUPPORT
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#endif
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#ifdef CONFIG_SPL_NAND_DENALI
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#define CONFIG_SPL_NAND_SUPPORT
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#endif
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/* SPL SDMMC boot support */
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#ifdef CONFIG_SPL_MMC_SUPPORT
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@ -360,6 +376,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
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#endif
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/* SPL NAND boot support */
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#ifdef CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SYS_NAND_USE_FLASH_BBT
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
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#endif
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/*
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* Stack setup
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*/
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