Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-10 15:14:43 +00:00
Code Issues Projects Releases Packages Wiki Activity

Merge branch 'master' of git://git.denx.de/u-boot-nds32

Browse source
This commit is contained in:
Tom Rini 2017-05-22 14:14:44 -04:00
commit c2774e6149
38 changed files with 1491 additions and 116 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
arch/Kconfig
View file

@ -44,6 +44,7 @@ config MIPS
config NDS32
bool "NDS32 architecture"
select SUPPORT_OF_CONTROL
config NIOS2
bool "Nios II architecture"

4
arch/nds32/Kconfig
View file

@ -11,8 +11,12 @@ choice
config TARGET_ADP_AG101P
bool "Support adp-ag101p"
config TARGET_ADP_AE3XX
bool "Support adp-ae3xx"
endchoice
source "board/AndesTech/adp-ag101p/Kconfig"
source "board/AndesTech/adp-ae3xx/Kconfig"
endmenu

1
arch/nds32/cpu/n1213/Makefile
View file

@ -12,3 +12,4 @@
extra-y = start.o
obj-$(if $(filter ag101,$(SOC)),y) += ag101/
obj-$(if $(filter ae3xx,$(SOC)),y) += ae3xx/

18
arch/nds32/cpu/n1213/ae3xx/Makefile Normal file
View file

@ -0,0 +1,18 @@
#
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# Copyright (C) 2011 Andes Technology Corporation
# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := cpu.o timer.o
obj-y += lowlevel_init.o
ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
obj-y += watchdog.o
endif

45
arch/nds32/cpu/n1213/ae3xx/cpu.c Normal file
View file

@ -0,0 +1,45 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* CPU specific code */
#include <common.h>
#include <command.h>
#include <watchdog.h>
#include <asm/cache.h>
#include <faraday/ftwdt010_wdt.h>
/*
* cleanup_before_linux() is called just before we call linux
* it prepares the processor for linux
*
* we disable interrupt and caches.
*/
int cleanup_before_linux(void)
{
disable_interrupts();
/* turn off I/D-cache */
cache_flush();
icache_disable();
dcache_disable();
return 0;
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
disable_interrupts();
panic("AE3XX wdt not support yet.\n");
}

148
arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S Normal file
View file

@ -0,0 +1,148 @@
/*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
.pic
.text
#include <common.h>
#include <config.h>
#include <asm/macro.h>
#include <generated/asm-offsets.h>
/*
* parameters for the SDRAM controller
*/
#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
/*
* for Orca and Emerald
*/
#define BOARD_ID_REG 0x104
#define BOARD_ID_FAMILY_MASK 0xfff000
#define BOARD_ID_FAMILY_V5 0x556000
#define BOARD_ID_FAMILY_K7 0x74b000
/*
* parameters for the static memory controller
*/
#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
/*
* for Orca and Emerald
*/
#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
/*
* parameters for the pmu controoler
*/
#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
/*
* numeric 7 segment display
*/
.macro led, num
write32 CONFIG_DEBUG_LED, \num
.endm
/*
* Waiting for SDRAM to set up
*/
.macro wait_sdram
li $r0, CONFIG_FTSDMC021_BASE
1:
lwi $r1, [$r0+FTSDMC021_CR2]
bnez $r1, 1b
.endm
.globl mem_init
mem_init:
move $r11, $lp
li $r0, SMC_BANK0_CR_A
lwi $r1, [$r0+#0x00]
ori $r1, $r1, 0x8f0
xori $r1, $r1, 0x8f0
/* 16-bit mode */
ori $r1, $r1, 0x60
li $r2, 0x00153153
swi $r1, [$r0+#0x00]
swi $r2, [$r0+#0x04]
move $lp, $r11
ret
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
.globl lowlevel_init
lowlevel_init:
move $r10, $lp
jal remap
#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
jal enable_fpu
#endif
ret $r10
remap:
move $r11, $lp
relo_base:
mfusr $r0, $pc
#ifdef CONFIG_MEM_REMAP
li $r4, 0x00000000
li $r5, 0x80000000
la $r6, _end@GOTOFF
1:
lmw.bim $r12, [$r5], $r19
smw.bim $r12, [$r4], $r19
blt $r5, $r6, 1b
#endif /* #ifdef CONFIG_MEM_REMAP */
move $lp, $r11
2:
ret
/*
* enable_fpu:
* Some of Andes CPU version support FPU coprocessor, if so,
* and toolchain support FPU instruction set, we should enable it.
*/
#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
enable_fpu:
mfsr $r0, $CPU_VER /* enable FPU if it exists */
srli $r0, $r0, 3
andi $r0, $r0, 1
beqz $r0, 1f /* skip if no COP */
mfsr $r0, $FUCOP_EXIST
srli $r0, $r0, 31
beqz $r0, 1f /* skip if no FPU */
mfsr $r0, $FUCOP_CTL
ori $r0, $r0, 1
mtsr $r0, $FUCOP_CTL
1:
ret
#endif
#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */

16
arch/nds32/cpu/n1213/ae3xx/timer.c Normal file
View file

@ -0,0 +1,16 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef CONFIG_TIMER
#include <common.h>
#include <asm/io.h>
#include <faraday/fttmr010.h>
#error "AE3XX timer only support DM flow"
#endif /* CONFIG_TIMER */

17
arch/nds32/cpu/n1213/ae3xx/watchdog.S Normal file
View file

@ -0,0 +1,17 @@
/*
* Copyright (C) 2011 Andes Technology Corporation
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch-ag101/ag101.h>
#include <linux/linkage.h>
.text
#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
ENTRY(turnoff_watchdog)
#error "AE3XX not support wdt yet"
ENDPROC(turnoff_watchdog)
#endif

3
arch/nds32/cpu/n1213/ag101/Makefile
View file

@ -11,10 +11,7 @@
#
obj-y := cpu.o timer.o
ifndef CONFIG_SKIP_LOWLEVEL_INIT
obj-y += lowlevel_init.o
endif
ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
obj-y += watchdog.o

8
arch/nds32/cpu/n1213/ag101/cpu.c
View file

@ -31,16 +31,10 @@ int cleanup_before_linux(void)
{
disable_interrupts();
#ifdef CONFIG_MMU
/* turn off I/D-cache */
cache_flush();
icache_disable();
dcache_disable();
/* flush I/D-cache */
invalidate_icac();
invalidate_dcac();
#endif
return 0;
}

59
arch/nds32/cpu/n1213/ag101/lowlevel_init.S
View file

@ -86,25 +86,7 @@
bnez $r1, 1b
.endm
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
.globl lowlevel_init
lowlevel_init:
move $r10, $lp
led 0x0
jal mem_init
led 0x10
jal remap
#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
led 0x1f
jal enable_fpu
#endif
led 0x20
ret $r10
.globl mem_init
mem_init:
move $r11, $lp
@ -124,9 +106,7 @@ mem_init:
lwi $r1, [$r0+#0x00]
ori $r1, $r1, 0x8f0
xori $r1, $r1, 0x8f0
/*
* check board
*/
/* check board */
li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG
lwi $r3, [$r3]
li $r4, BOARD_ID_FAMILY_MASK
@ -134,29 +114,21 @@ mem_init:
li $r4, BOARD_ID_FAMILY_K7
xor $r4, $r3, $r4
beqz $r4, use_flash_16bit_boot
/*
* 32-bit mode
*/
/* 32-bit mode */
use_flash_32bit_boot:
ori $r1, $r1, 0x50
li $r2, 0x00151151
j sdram_b0_cr
/*
* 16-bit mode
*/
/* 16-bit mode */
use_flash_16bit_boot:
ori $r1, $r1, 0x60
li $r2, 0x00153153
/*
* SRAM bank0 config
*/
/* SRAM bank0 config */
sdram_b0_cr:
swi $r1, [$r0+#0x00]
swi $r2, [$r0+#0x04]
/*
* config AHB Controller
*/
/* config AHB Controller */
led 0x02
/*
@ -192,6 +164,21 @@ sdram_b0_cr:
move $lp, $r11
ret
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
.globl lowlevel_init
lowlevel_init:
move $r10, $lp
led 0x10
jal remap
#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
led 0x1f
jal enable_fpu
#endif
led 0x20
ret $r10
remap:
move $r11, $lp
#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
@ -203,9 +190,7 @@ relo_base:
mfusr $r0, $pc
#endif /* __NDS32_N1213_43U1H__ */
/*
* Remapping
*/
/* Remapping */
led 0x1a
write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001800
write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001880

3
arch/nds32/cpu/n1213/ag101/timer.c
View file

@ -8,7 +8,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef CONFIG_TIMER
#include <common.h>
#include <asm/io.h>
#include <faraday/fttmr010.h>
@ -189,3 +189,4 @@ ulong get_tbclk(void)
return CONFIG_SYS_CLK_FREQ;
#endif
}
#endif /* CONFIG_TIMER */

50
arch/nds32/cpu/n1213/start.S
View file

@ -114,11 +114,39 @@ reset_gp:
set_ivb:
li $r0, 0x0
/* turn on BTB */
mtsr $r0, $misc_ctl
/* set IVIC, vector size: 4 bytes, base: 0x0 */
mtsr $r0, $ivb
/*
* MMU_CTL NTC0 Cacheable/Write-Back
*/
li $r0, ~0x3
mfsr $r1, $mr8
and $r1, $r1, $r0
mtsr $r1, $mr8
#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
li $r0, 0x4
mfsr $r1, $mr0
or $r1, $r1, $r0
mtsr $r1, $mr0
#endif
#if !defined(CONFIG_SYS_ICACHE_OFF)
li $r0, 0x1
mfsr $r1, $mr8
or $r1, $r1, $r0
mtsr $r1, $mr8
#endif
#if !defined(CONFIG_SYS_DCACHE_OFF)
li $r0, 0x2
mfsr $r1, $mr8
or $r1, $r1, $r0
mtsr $r1, $mr8
#endif
jal mem_init
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
jal lowlevel_init
@ -133,7 +161,6 @@ update_gp:
ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4)
add5.pc $gp
#endif
/*
* do critical initializations first (shall be in short time)
* do self_relocation ASAP.
@ -161,11 +188,14 @@ update_gp:
*/
call_board_init_f:
li $sp, CONFIG_SYS_INIT_SP_ADDR
li $r10, GD_SIZE /* get GD size */
sub $sp, $sp, $r10 /* GD start addr */
move $r10, $sp
move $r0, $sp
bal board_init_f_alloc_reserve
move $sp, $r0
bal board_init_f_init_reserve
#ifdef CONFIG_DEBUG_UART
bal debug_uart_init
#endif
li $r0, 0x00000000
#ifdef __PIC__
#ifdef __NDS32_N1213_43U1H__
/* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
@ -201,12 +231,10 @@ stack_setup:
la $r1, _end@GOTOFF
move $r2, $r6 /* r2 <- scratch for copy_loop */
copy_loop:
lwi.p $r7, [$r0], #4
swi.p $r7, [$r2], #4
lmw.bim $r11, [$r0], $r18
smw.bim $r11, [$r2], $r18
blt $r0, $r1, copy_loop
/*
* fix relocations related issues
*/
@ -246,6 +274,8 @@ clbss_l:
* initialization, now running from RAM.
*/
call_board_init_r:
bal invalidate_icache_all
bal flush_dcache_all
la $r0, board_init_r@GOTOFF
move $lp, $r0 /* offset of board_init_r() */
add $lp, $lp, $r9 /* real address of board_init_r() */

15
arch/nds32/dts/Makefile Normal file
View file

@ -0,0 +1,15 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
dtb-$(CONFIG_TARGET_ADP_AG101P) += ag101p.dtb
dtb-$(CONFIG_TARGET_ADP_AE3XX) += ae3xx.dtb
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000
PHONY += dtbs
dtbs: $(addprefix $(obj)/, $(dtb-y))
@:
clean-files := *.dtb

65
arch/nds32/dts/ae3xx.dts Normal file
View file

@ -0,0 +1,65 @@
/dts-v1/;
/ {
compatible = "nds32 ae3xx";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
aliases {
uart0 = &serial0;
} ;
chosen {
/* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug bootmem_debug memblock=debug loglevel=7"; */
bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
stdout-path = "uart0:38400n8";
tick-timer = &timer0;
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x40000000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "andestech,n13";
reg = <0>;
/* FIXME: to fill correct frqeuency */
clock-frequency = <60000000>;
};
};
intc: interrupt-controller {
compatible = "andestech,atnointc010";
#interrupt-cells = <1>;
interrupt-controller;
};
serial0: serial@f0300000 {
compatible = "andestech,uart16550", "ns16550a";
reg = <0xf0300000 0x1000>;
interrupts = <7 4>;
clock-frequency = <14745600>;
reg-shift = <2>;
reg-offset = <32>;
no-loopback-test = <1>;
};
timer0: timer@f0400000 {
compatible = "andestech,atcpit100";
reg = <0xf0400000 0x1000>;
interrupts = <2 4>;
clock-frequency = <30000000>;
};
nor@0,0 {
compatible = "cfi-flash";
reg = <0x88000000 0x1000>;
bank-width = <2>;
device-width = <1>;
};
};

57
arch/nds32/dts/ag101p.dts Normal file
View file

@ -0,0 +1,57 @@
/dts-v1/;
/ {
compatible = "nds32 ag101p";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
aliases {
uart0 = &serial0;
} ;
chosen {
/* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug bootmem_debug memblock=debug loglevel=7"; */
bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug loglevel=7";
stdout-path = "uart0:38400n8";
tick-timer = &timer0;
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x40000000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "andestech,n13";
reg = <0>;
/* FIXME: to fill correct frqeuency */
clock-frequency = <60000000>;
};
};
intc: interrupt-controller {
compatible = "andestech,atnointc010";
#interrupt-cells = <1>;
interrupt-controller;
};
serial0: serial@99600000 {
compatible = "andestech,uart16550", "ns16550a";
reg = <0x99600000 0x1000>;
interrupts = <7 4>;
clock-frequency = <14745600>;
reg-shift = <2>;
no-loopback-test = <1>;
};
timer0: timer@98400000 {
compatible = "andestech,attmr010";
reg = <0x98400000 0x1000>;
interrupts = <19 4>;
clock-frequency = <15000000>;
};
};

54
arch/nds32/include/asm/arch-ae3xx/ae3xx.h Normal file
View file

@ -0,0 +1,54 @@
/*
* Copyright (C) 2016 Andes Technology Corporation
* Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __AE3XX_H
#define __AE3XX_H
/* Hardware register bases */
/* Static Memory Controller (SRAM) */
#define CONFIG_FTSMC020_BASE 0xe0400000
/* DMA Controller */
#define CONFIG_FTDMAC020_BASE 0xf0c00000
/* AHB-to-APB Bridge */
#define CONFIG_FTAPBBRG020S_01_BASE 0xf0000000
/* Reserved */
#define CONFIG_RESERVED_01_BASE 0xe0500000
/* Reserved */
#define CONFIG_RESERVED_02_BASE 0xf0800000
/* Reserved */
#define CONFIG_RESERVED_03_BASE 0xf0900000
/* Ethernet */
#define CONFIG_FTMAC100_BASE 0xe0100000
/* Reserved */
#define CONFIG_RESERVED_04_BASE 0xf1000000
/* APB Device definitions */
/* UART1 */
#define CONFIG_FTUART010_01_BASE 0xf0200000
/* UART2 */
#define CONFIG_FTUART010_02_BASE 0xf0300000
/* Counter/Timers */
#define CONFIG_FTTMR010_BASE 0xf0400000
/* Watchdog Timer */
#define CONFIG_FTWDT010_BASE 0xf0500000
/* Real Time Clock */
#define CONFIG_FTRTC010_BASE 0xf0600000
/* GPIO */
#define CONFIG_FTGPIO010_BASE 0xf0700000
/* I2C */
#define CONFIG_FTIIC010_BASE 0xf0a00000
/* SD Controller */
#define CONFIG_FTSDC010_BASE 0xf0e00000
/* The following address was not defined in Linux */
/* Synchronous Serial Port Controller (SSP) 01 */
#define CONFIG_FTSSP010_01_BASE 0xf0d00000
#endif /* __AE3XX_H */

65
arch/nds32/include/asm/bootm.h Normal file
View file

@ -0,0 +1,65 @@
/*
* Copyright (c) 2013, Google Inc.
*
* Copyright (C) 2011
* Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
*
* SPDX-License-Identifier: GPL-2.0+
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef NDS32_BOOTM_H
#define NDS32_BOOTM_H
extern void udc_disconnect(void);
#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
defined(CONFIG_CMDLINE_TAG) || \
defined(CONFIG_INITRD_TAG) || \
defined(CONFIG_SERIAL_TAG) || \
defined(CONFIG_REVISION_TAG)
# define BOOTM_ENABLE_TAGS 1
#else
# define BOOTM_ENABLE_TAGS 0
#endif
#ifdef CONFIG_SETUP_MEMORY_TAGS
# define BOOTM_ENABLE_MEMORY_TAGS 1
#else
# define BOOTM_ENABLE_MEMORY_TAGS 0
#endif
#ifdef CONFIG_CMDLINE_TAG
#define BOOTM_ENABLE_CMDLINE_TAG 1
#else
#define BOOTM_ENABLE_CMDLINE_TAG 0
#endif
#ifdef CONFIG_INITRD_TAG
#define BOOTM_ENABLE_INITRD_TAG 1
#else
#define BOOTM_ENABLE_INITRD_TAG 0
#endif
#ifdef CONFIG_SERIAL_TAG
#define BOOTM_ENABLE_SERIAL_TAG 1
void get_board_serial(struct tag_serialnr *serialnr);
#else
#define BOOTM_ENABLE_SERIAL_TAG 0
static inline void get_board_serial(struct tag_serialnr *serialnr)
{
}
#endif
#ifdef CONFIG_REVISION_TAG
#define BOOTM_ENABLE_REVISION_TAG 1
u32 get_board_rev(void);
#else
#define BOOTM_ENABLE_REVISION_TAG 0
static inline u32 get_board_rev(void)
{
return 0;
}
#endif
#endif

23
arch/nds32/include/asm/cache.h
View file

@ -16,6 +16,7 @@ void icache_disable(void);
int dcache_status(void);
void dcache_enable(void);
void dcache_disable(void);
void cache_flush(void);
#define DEFINE_GET_SYS_REG(reg) \
static inline unsigned long GET_##reg(void) \
@ -30,10 +31,24 @@ void dcache_disable(void);
enum cache_t {ICACHE, DCACHE};
DEFINE_GET_SYS_REG(ICM_CFG);
DEFINE_GET_SYS_REG(DCM_CFG);
#define ICM_CFG_OFF_ISZ 6 /* I-cache line size */
#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ)
#define DCM_CFG_OFF_DSZ 6 /* D-cache line size */
#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ)
/* I-cache sets (# of cache lines) per way */
#define ICM_CFG_OFF_ISET 0
/* I-cache ways */
#define ICM_CFG_OFF_IWAY 3
#define ICM_CFG_MSK_ISET (0x7 << ICM_CFG_OFF_ISET)
#define ICM_CFG_MSK_IWAY (0x7 << ICM_CFG_OFF_IWAY)
/* D-cache sets (# of cache lines) per way */
#define DCM_CFG_OFF_DSET 0
/* D-cache ways */
#define DCM_CFG_OFF_DWAY 3
#define DCM_CFG_MSK_DSET (0x7 << DCM_CFG_OFF_DSET)
#define DCM_CFG_MSK_DWAY (0x7 << DCM_CFG_OFF_DWAY)
/* I-cache line size */
#define ICM_CFG_OFF_ISZ 6
#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ)
/* D-cache line size */
#define DCM_CFG_OFF_DSZ 6
#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ)
/*
* The current upper bound for NDS32 L1 data cache line sizes is 32 bytes.

1
arch/nds32/include/asm/config.h
View file

@ -8,5 +8,6 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_LMB
#endif

1
arch/nds32/include/asm/mach-types.h
View file

@ -13,6 +13,7 @@ extern unsigned int __machine_arch_type;
/* see arch/arm/kernel/arch.c for a description of these */
#define MACH_TYPE_ADPAG101P 1
#define MACH_TYPE_ADPAE3XX 2
#ifdef CONFIG_ARCH_ADPAG101P
# ifdef machine_arch_type

1
arch/nds32/lib/Makefile
View file

@ -11,4 +11,5 @@
obj-y += cache.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += interrupts.o

20
arch/nds32/lib/boot.c Normal file
View file

@ -0,0 +1,20 @@
/*
* Copyright (C) 2011 Andes Technology Corporation
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned long do_go_exec(ulong (*entry)(int, char * const []),
int argc, char * const argv[])
{
cleanup_before_linux();
return entry(argc, argv);
}

29
arch/nds32/lib/bootm.c
View file

@ -11,9 +11,16 @@
#include <image.h>
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
#include <asm/bootm.h>
DECLARE_GLOBAL_DATA_PTR;
int arch_fixup_fdt(void *blob)
{
return 0;
}
#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
defined(CONFIG_CMDLINE_TAG) || \
defined(CONFIG_INITRD_TAG) || \
@ -67,6 +74,15 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
debug("## Transferring control to Linux (at address %08lx) ...\n",
(ulong)theKernel);
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
debug("using: FDT\n");
if (image_setup_linux(images)) {
printf("FDT creation failed! hanging...");
hang();
}
#endif
} else if (BOOTM_ENABLE_TAGS) {
#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
defined(CONFIG_CMDLINE_TAG) || \
defined(CONFIG_INITRD_TAG) || \
@ -101,16 +117,17 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
udc_disconnect();
}
#endif
}
cleanup_before_linux();
theKernel(0, machid, bd->bi_boot_params);
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
theKernel(0, machid, (unsigned long)images->ft_addr);
else
theKernel(0, machid, bd->bi_boot_params);
/* does not return */
return 1;
}
#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
defined(CONFIG_CMDLINE_TAG) || \
defined(CONFIG_INITRD_TAG) || \
@ -130,7 +147,6 @@ static void setup_start_tag(bd_t *bd)
params = tag_next(params);
}
#ifdef CONFIG_SETUP_MEMORY_TAGS
static void setup_memory_tags(bd_t *bd)
{
@ -148,7 +164,6 @@ static void setup_memory_tags(bd_t *bd)
}
#endif /* CONFIG_SETUP_MEMORY_TAGS */
static void setup_commandline_tag(bd_t *bd, char *commandline)
{
char *p;
@ -176,7 +191,6 @@ static void setup_commandline_tag(bd_t *bd, char *commandline)
params = tag_next(params);
}
#ifdef CONFIG_INITRD_TAG
static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
{
@ -224,7 +238,6 @@ void setup_revision_tag(struct tag **in_params)
}
#endif /* CONFIG_REVISION_TAG */
static void setup_end_tag(bd_t *bd)
{
params->hdr.tag = ATAG_NONE;

197
arch/nds32/lib/cache.c
View file

@ -7,32 +7,56 @@
*/
#include <common.h>
#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
static inline unsigned long CACHE_SET(unsigned char cache)
{
if (cache == ICACHE)
return 64 << ((GET_ICM_CFG() & ICM_CFG_MSK_ISET) \
>> ICM_CFG_OFF_ISET);
else
return 64 << ((GET_DCM_CFG() & DCM_CFG_MSK_DSET) \
>> DCM_CFG_OFF_DSET);
}
static inline unsigned long CACHE_WAY(unsigned char cache)
{
if (cache == ICACHE)
return 1 + ((GET_ICM_CFG() & ICM_CFG_MSK_IWAY) \
>> ICM_CFG_OFF_IWAY);
else
return 1 + ((GET_DCM_CFG() & DCM_CFG_MSK_DWAY) \
>> DCM_CFG_OFF_DWAY);
}
static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
{
if (cache == ICACHE)
return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
>> ICM_CFG_OFF_ISZ) - 1);
>> ICM_CFG_OFF_ISZ) - 1);
else
return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
>> DCM_CFG_OFF_DSZ) - 1);
>> DCM_CFG_OFF_DSZ) - 1);
}
#endif
void flush_dcache_range(unsigned long start, unsigned long end)
#ifndef CONFIG_SYS_ICACHE_OFF
void invalidate_icache_all(void)
{
unsigned long line_size;
unsigned long end, line_size;
line_size = CACHE_LINE_SIZE(ICACHE);
end = line_size * CACHE_WAY(ICACHE) * CACHE_SET(ICACHE);
do {
end -= line_size;
__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
line_size = CACHE_LINE_SIZE(DCACHE);
end -= line_size;
__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
while (end > start) {
asm volatile (
"\n\tcctl %0, L1D_VA_WB"
"\n\tcctl %0, L1D_VA_INVAL"
:
: "r" (start)
);
start += line_size;
}
end -= line_size;
__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
end -= line_size;
__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
} while (end > 0);
}
void invalidate_icache_range(unsigned long start, unsigned long end)
@ -50,27 +74,6 @@ void invalidate_icache_range(unsigned long start, unsigned long end)
}
}
void invalidate_dcache_range(unsigned long start, unsigned long end)
{
unsigned long line_size;
line_size = CACHE_LINE_SIZE(DCACHE);
while (end > start) {
asm volatile (
"\n\tcctl %0, L1D_VA_INVAL"
:
: "r"(start)
);
start += line_size;
}
}
void flush_cache(unsigned long addr, unsigned long size)
{
flush_dcache_range(addr, addr + size);
invalidate_icache_range(addr, addr + size);
}
void icache_enable(void)
{
asm volatile (
@ -107,6 +110,81 @@ int icache_status(void)
return ret;
}
#else
void invalidate_icache_all(void)
{
}
void invalidate_icache_range(unsigned long start, unsigned long end)
{
}
void icache_enable(void)
{
}
void icache_disable(void)
{
}
int icache_status(void)
{
return 0;
}
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void dcache_wbinval_all(void)
{
unsigned long end, line_size;
line_size = CACHE_LINE_SIZE(DCACHE);
end = line_size * CACHE_WAY(DCACHE) * CACHE_SET(DCACHE);
do {
end -= line_size;
__asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
__asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
end -= line_size;
__asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
__asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
end -= line_size;
__asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
__asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
end -= line_size;
__asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
__asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
} while (end > 0);
}
void flush_dcache_range(unsigned long start, unsigned long end)
{
unsigned long line_size;
line_size = CACHE_LINE_SIZE(DCACHE);
while (end > start) {
asm volatile (
"\n\tcctl %0, L1D_VA_WB"
"\n\tcctl %0, L1D_VA_INVAL" : : "r" (start)
);
start += line_size;
}
}
void invalidate_dcache_range(unsigned long start, unsigned long end)
{
unsigned long line_size;
line_size = CACHE_LINE_SIZE(DCACHE);
while (end > start) {
asm volatile (
"\n\tcctl %0, L1D_VA_INVAL" : : "r"(start)
);
start += line_size;
}
}
void dcache_enable(void)
{
asm volatile (
@ -131,7 +209,6 @@ void dcache_disable(void)
int dcache_status(void)
{
int ret;
asm volatile (
"mfsr $p0, $mr8\n\t"
"andi %0, $p0, 0x02\n\t"
@ -139,6 +216,52 @@ int dcache_status(void)
:
: "memory"
);
return ret;
}
#else
void dcache_wbinval_all(void)
{
}
void flush_dcache_range(unsigned long start, unsigned long end)
{
}
void invalidate_dcache_range(unsigned long start, unsigned long end)
{
}
void dcache_enable(void)
{
}
void dcache_disable(void)
{
}
int dcache_status(void)
{
return 0;
}
#endif
void flush_dcache_all(void)
{
dcache_wbinval_all();
}
void cache_flush(void)
{
flush_dcache_all();
invalidate_icache_all();
}
void flush_cache(unsigned long addr, unsigned long size)
{
flush_dcache_range(addr, addr + size);
invalidate_icache_range(addr, addr + size);
}

18
board/AndesTech/adp-ae3xx/Kconfig Normal file
View file

@ -0,0 +1,18 @@
if TARGET_ADP_AE3XX
config SYS_CPU
default "n1213"
config SYS_BOARD
default "adp-ae3xx"
config SYS_VENDOR
default "AndesTech"
config SYS_SOC
default "ae3xx"
config SYS_CONFIG_NAME
default "adp-ae3xx"
endif

6
board/AndesTech/adp-ae3xx/MAINTAINERS Normal file
View file

@ -0,0 +1,6 @@
ADP-AG101P BOARD
M: Andes <uboot@andestech.com>
S: Maintained
F: board/AndesTech/adp-ae3xx/
F: include/configs/adp-ae3xx.h
F: configs/adp-ae3xx_defconfig

8
board/AndesTech/adp-ae3xx/Makefile Normal file
View file

@ -0,0 +1,8 @@
#
# Copyright (C) 2016 Andes Technology Corporation
# Rick Chen, Andes Technology Corporation <rick@andestech.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := adp-ae3xx.o

86
board/AndesTech/adp-ae3xx/adp-ae3xx.c Normal file
View file

@ -0,0 +1,86 @@
/*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#if defined(CONFIG_FTMAC100)
#include <netdev.h>
#endif
#include <linux/io.h>
#include <faraday/ftsdc010.h>
#include <faraday/ftsmc020.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Miscellaneous platform dependent initializations
*/
int board_init(void)
{
/*
* refer to BOOT_PARAMETER_PA_BASE within
* "linux/arch/nds32/include/asm/misc_spec.h"
*/
printf("Board: %s\n" , CONFIG_SYS_BOARD);
gd->bd->bi_arch_number = MACH_TYPE_ADPAE3XX;
gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
return 0;
}
int dram_init(void)
{
unsigned long sdram_base = PHYS_SDRAM_0;
unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
unsigned long actual_size;
actual_size = get_ram_size((void *)sdram_base, expected_size);
gd->ram_size = actual_size;
if (expected_size != actual_size) {
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
}
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE;
return 0;
}
#if defined(CONFIG_FTMAC100)
int board_eth_init(bd_t *bd)
{
return ftmac100_initialize(bd);
}
#endif
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
{
if (banknum == 0) { /* non-CFI boot flash */
info->portwidth = FLASH_CFI_8BIT;
info->chipwidth = FLASH_CFI_BY8;
info->interface = FLASH_CFI_X8;
return 1;
} else {
return 0;
}
}
int board_mmc_init(bd_t *bis)
{
#ifndef CONFIG_DM_MMC
#ifdef CONFIG_FTSDC010
ftsdc010_mmc_init(0);
#endif
#endif
return 0;
}

9
board/AndesTech/adp-ag101p/adp-ag101p.c
View file

@ -7,8 +7,10 @@
*/
#include <common.h>
#if defined(CONFIG_FTMAC100)
#include <netdev.h>
#include <asm/io.h>
#endif
#include <linux/io.h>
#include <faraday/ftsdc010.h>
#include <faraday/ftsmc020.h>
@ -25,6 +27,7 @@ int board_init(void)
* refer to BOOT_PARAMETER_PA_BASE within
* "linux/arch/nds32/include/asm/misc_spec.h"
*/
printf("Board: %s\n" , CONFIG_SYS_BOARD);
gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P;
gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
@ -59,10 +62,12 @@ int dram_init_banksize(void)
return 0;
}
#if defined(CONFIG_FTMAC100)
int board_eth_init(bd_t *bd)
{
return ftmac100_initialize(bd);
}
#endif
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
{
@ -78,6 +83,8 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
int board_mmc_init(bd_t *bis)
{
#ifdef CONFIG_FTSDC010
ftsdc010_mmc_init(0);
#endif
return 0;
}

25
configs/adp-ae3xx_defconfig Normal file
View file

@ -0,0 +1,25 @@
CONFIG_NDS32=y
CONFIG_TARGET_ADP_AE3XX=y
CONFIG_DEFAULT_DEVICE_TREE="ae3xx"
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="NDS32 # "
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_BAUDRATE=38400
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_MTD=y
CONFIG_CFI_FLASH=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_TIMER=y
CONFIG_AE3XX_TIMER=y

8
configs/adp-ag101p_defconfig
View file

@ -1,9 +1,12 @@
CONFIG_NDS32=y
CONFIG_TARGET_ADP_AG101P=y
CONFIG_DEFAULT_DEVICE_TREE="ag101p"
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="NDS32 # "
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
@ -12,4 +15,9 @@ CONFIG_CMD_FAT=y
CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_BAUDRATE=38400
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_TIMER=y
CONFIG_AG101P_TIMER=y

12
drivers/timer/Kconfig
View file

@ -74,4 +74,16 @@ config ARC_TIMER
usually at least one of them exists. Either of them is supported
in U-Boot.
config AG101P_TIMER
bool "AG101P timer support"
depends on TIMER && NDS32
help
Select this to enable a timer for AG01P devices.
config AE3XX_TIMER
bool "AE3XX timer support"
depends on TIMER && NDS32
help
Select this to enable a timer for AE3XX devices.
endmenu

2
drivers/timer/Makefile
View file

@ -12,3 +12,5 @@ obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
obj-$(CONFIG_AST_TIMER) += ast_timer.o
obj-$(CONFIG_STI_TIMER) += sti-timer.o
obj-$(CONFIG_ARC_TIMER) += arc_timer.o
obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o

117
drivers/timer/ae3xx_timer.c Normal file
View file

@ -0,0 +1,117 @@
/*
* Andestech ATCPIT100 timer driver
*
* (C) Copyright 2016
* Rick Chen, NDS32 Software Engineering, rick@andestech.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <timer.h>
#include <linux/io.h>
DECLARE_GLOBAL_DATA_PTR;
#define REG32_TMR(x) (*(unsigned long *) ((plat->regs) + (x>>2)))
/*
* Definition of register offsets
*/
/* ID and Revision Register */
#define ID_REV 0x0
/* Configuration Register */
#define CFG 0x10
/* Interrupt Enable Register */
#define INT_EN 0x14
#define CH_INT_EN(c , i) ((1<<i)<<(4*c))
/* Interrupt Status Register */
#define INT_STA 0x18
#define CH_INT_STA(c , i) ((1<<i)<<(4*c))
/* Channel Enable Register */
#define CH_EN 0x1C
#define CH_TMR_EN(c , t) ((1<<t)<<(4*c))
/* Ch n Control REgister */
#define CH_CTL(n) (0x20+0x10*n)
/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */
#define APB_CLK (1<<3)
/* Channel mode , bit 0~2 */
#define TMR_32 1
#define TMR_16 2
#define TMR_8 3
#define PWM 4
#define CH_REL(n) (0x24+0x10*n)
#define CH_CNT(n) (0x28+0x10*n)
struct atctmr_timer_regs {
u32 id_rev; /* 0x00 */
u32 reservd[3]; /* 0x04 ~ 0x0c */
u32 cfg; /* 0x10 */
u32 int_en; /* 0x14 */
u32 int_st; /* 0x18 */
u32 ch_en; /* 0x1c */
u32 ch0_ctrl; /* 0x20 */
u32 ch0_reload; /* 0x24 */
u32 ch0_cntr; /* 0x28 */
u32 reservd1; /* 0x2c */
u32 ch1_ctrl; /* 0x30 */
u32 ch1_reload; /* 0x34 */
u32 int_mask; /* 0x38 */
};
struct atftmr_timer_platdata {
unsigned long *regs;
};
static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
{
struct atftmr_timer_platdata *plat = dev->platdata;
u32 val;
val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
*count = timer_conv_64(val);
return 0;
}
static int atctmr_timer_probe(struct udevice *dev)
{
struct atftmr_timer_platdata *plat = dev->platdata;
REG32_TMR(CH_REL(1)) = 0xffffffff;
REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32;
REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0);
return 0;
}
static int atctme_timer_ofdata_to_platdata(struct udevice *dev)
{
struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
plat->regs = map_physmem(dev_get_addr(dev) , 0x100 , MAP_NOCACHE);
return 0;
}
static const struct timer_ops ag101p_timer_ops = {
.get_count = atftmr_timer_get_count,
};
static const struct udevice_id ag101p_timer_ids[] = {
{ .compatible = "andestech,atcpit100" },
{}
};
U_BOOT_DRIVER(altera_timer) = {
.name = "ae3xx_timer",
.id = UCLASS_TIMER,
.of_match = ag101p_timer_ids,
.ofdata_to_platdata = atctme_timer_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata),
.probe = atctmr_timer_probe,
.ops = &ag101p_timer_ops,
.flags = DM_FLAG_PRE_RELOC,
};

122
drivers/timer/ag101p_timer.c Normal file
View file

@ -0,0 +1,122 @@
/*
* Andestech ATFTMR010 timer driver
*
* (C) Copyright 2016
* Rick Chen, NDS32 Software Engineering, rick@andestech.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <timer.h>
#include <linux/io.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Timer Control Register
*/
#define T3_UPDOWN (1 << 11)
#define T2_UPDOWN (1 << 10)
#define T1_UPDOWN (1 << 9)
#define T3_OFENABLE (1 << 8)
#define T3_CLOCK (1 << 7)
#define T3_ENABLE (1 << 6)
#define T2_OFENABLE (1 << 5)
#define T2_CLOCK (1 << 4)
#define T2_ENABLE (1 << 3)
#define T1_OFENABLE (1 << 2)
#define T1_CLOCK (1 << 1)
#define T1_ENABLE (1 << 0)
/*
* Timer Interrupt State & Mask Registers
*/
#define T3_OVERFLOW (1 << 8)
#define T3_MATCH2 (1 << 7)
#define T3_MATCH1 (1 << 6)
#define T2_OVERFLOW (1 << 5)
#define T2_MATCH2 (1 << 4)
#define T2_MATCH1 (1 << 3)
#define T1_OVERFLOW (1 << 2)
#define T1_MATCH2 (1 << 1)
#define T1_MATCH1 (1 << 0)
struct atftmr_timer_regs {
u32 t1_counter; /* 0x00 */
u32 t1_load; /* 0x04 */
u32 t1_match1; /* 0x08 */
u32 t1_match2; /* 0x0c */
u32 t2_counter; /* 0x10 */
u32 t2_load; /* 0x14 */
u32 t2_match1; /* 0x18 */
u32 t2_match2; /* 0x1c */
u32 t3_counter; /* 0x20 */
u32 t3_load; /* 0x24 */
u32 t3_match1; /* 0x28 */
u32 t3_match2; /* 0x2c */
u32 cr; /* 0x30 */
u32 int_state; /* 0x34 */
u32 int_mask; /* 0x38 */
};
struct atftmr_timer_platdata {
struct atftmr_timer_regs *regs;
};
static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
{
struct atftmr_timer_platdata *plat = dev->platdata;
struct atftmr_timer_regs *const regs = plat->regs;
u32 val;
val = readl(&regs->t3_counter);
*count = timer_conv_64(val);
return 0;
}
static int atftmr_timer_probe(struct udevice *dev)
{
struct atftmr_timer_platdata *plat = dev->platdata;
struct atftmr_timer_regs *const regs = plat->regs;
u32 cr;
writel(0, &regs->t3_load);
writel(0, &regs->t3_counter);
writel(TIMER_LOAD_VAL, &regs->t3_match1);
writel(TIMER_LOAD_VAL, &regs->t3_match2);
/* disable interrupts */
writel(T3_MATCH1|T3_MATCH2|T3_OVERFLOW , &regs->int_mask);
cr = readl(&regs->cr);
cr |= (T3_ENABLE|T3_UPDOWN);
writel(cr, &regs->cr);
return 0;
}
static int atftme_timer_ofdata_to_platdata(struct udevice *dev)
{
struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
plat->regs = map_physmem(dev_get_addr(dev),
sizeof(struct atftmr_timer_regs),
MAP_NOCACHE);
return 0;
}
static const struct timer_ops ag101p_timer_ops = {
.get_count = atftmr_timer_get_count,
};
static const struct udevice_id ag101p_timer_ids[] = {
{ .compatible = "andestech,attmr010" },
{}
};
U_BOOT_DRIVER(altera_timer) = {
.name = "ag101p_timer",
.id = UCLASS_TIMER,
.of_match = ag101p_timer_ids,
.ofdata_to_platdata = atftme_timer_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata),
.probe = atftmr_timer_probe,
.ops = &ag101p_timer_ops,
.flags = DM_FLAG_PRE_RELOC,
};

260
include/configs/adp-ae3xx.h Normal file
View file

@ -0,0 +1,260 @@
/*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch-ae3xx/ae3xx.h>
/*
* CPU and Board Configuration Options
*/
#define CONFIG_USE_INTERRUPT
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SKIP_TRUNOFF_WATCHDOG
#define CONFIG_CMDLINE_EDITING
#define CONFIG_PANIC_HANG
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_SERVERIP
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE 0x00500000
#ifdef CONFIG_OF_CONTROL
#undef CONFIG_OF_SEPARATE
#define CONFIG_OF_EMBED
#endif
#else
#define CONFIG_SYS_TEXT_BASE 0x80000000
#endif
/*
* Timer
*/
#define CONFIG_SYS_CLK_FREQ 39062500
#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
/*
* Use Externel CLOCK or PCLK
*/
#undef CONFIG_FTRTC010_EXTCLK
#ifndef CONFIG_FTRTC010_EXTCLK
#define CONFIG_FTRTC010_PCLK
#endif
#ifdef CONFIG_FTRTC010_EXTCLK
#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
#else
#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
#endif
#define TIMER_LOAD_VAL 0xffffffff
/*
* Real Time Clock
*/
#define CONFIG_RTC_FTRTC010
/*
* Real Time Clock Divider
* RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
*/
#define OSC_5MHZ (5*1000000)
#define OSC_CLK (4*OSC_5MHZ)
#define RTC_DIV_COUNT (0.5) /* Why?? */
/*
* Serial console configuration
*/
/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#endif
#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
/*
* Ethernet
*/
#define CONFIG_FTMAC100
/*
* SD (MMC) controller
*/
#define CONFIG_FTSDC010
#define CONFIG_FTSDC010_NUMBER 1
#define CONFIG_FTSDC010_SDIO
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS 16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* Size of malloc() pool
*/
/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
#define CONFIG_SYS_MALLOC_LEN (512 << 10)
/*
* Physical Memory Map
*/
#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1 \
(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
GENERATED_GBL_DATA_SIZE)
/*
* Load address and memory test area should agree with
* arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
*/
#define CONFIG_SYS_LOAD_ADDR 0x300000
/* memtest works on 63 MB in DRAM */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
/*
* Static memory controller configuration
*/
#define CONFIG_FTSMC020
#ifdef CONFIG_FTSMC020
#include <faraday/ftsmc020.h>
#define CONFIG_SYS_FTSMC020_CONFIGS { \
{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
}
#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
FTSMC020_BANK_SIZE_32M | \
FTSMC020_BANK_MBW_32)
#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
FTSMC020_TPR_AST(1) | \
FTSMC020_TPR_CTW(1) | \
FTSMC020_TPR_ATI(1) | \
FTSMC020_TPR_AT2(1) | \
FTSMC020_TPR_WTC(1) | \
FTSMC020_TPR_AHT(1) | \
FTSMC020_TPR_TRNA(1))
#endif
/*
* FLASH on ADP_AG101P is connected to BANK0
* Just disalbe the other BANK to avoid detection error.
*/
#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
FTSMC020_BANK_SIZE_32M | \
FTSMC020_BANK_MBW_32)
#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
FTSMC020_TPR_CTW(3) | \
FTSMC020_TPR_ATI(0xf) | \
FTSMC020_TPR_AT2(3) | \
FTSMC020_TPR_WTC(3) | \
FTSMC020_TPR_AHT(3) | \
FTSMC020_TPR_TRNA(0xf))
#define FTSMC020_BANK1_CONFIG (0x00)
#define FTSMC020_BANK1_TIMING (0x00)
#endif /* CONFIG_FTSMC020 */
/*
* FLASH and environment organization
*/
/* use CFI framework */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
/* support JEDEC */
#ifdef CONFIG_CFI_FLASH
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#endif
/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
/* max number of memory banks */
/*
* There are 4 banks supported for this Controller,
* but we have only 1 bank connected to flash on board
*/
#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#endif
#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
/* max number of sectors on one chip */
#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
#define CONFIG_SYS_MAX_FLASH_SECT 512
/* environments */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
#define CONFIG_ENV_SIZE 8192
#define CONFIG_ENV_OVERWRITE
/*
* For booting Linux, the board info and command line data
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
/* Increase max gunzip size */
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
#endif /* __CONFIG_H */

33
include/configs/adp-ag101p.h
View file

@ -20,14 +20,13 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#define CONFIG_CMDLINE_EDITING
/*
* Definitions related to passing arguments to kernel.
*/
#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
#define CONFIG_INITRD_TAG /* send initrd params */
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_SERVERIP
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_MEM_REMAP
@ -35,6 +34,10 @@
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE 0x00500000
#ifdef CONFIG_OF_CONTROL
#undef CONFIG_OF_SEPARATE
#define CONFIG_OF_EMBED
#endif
#else
#ifdef CONFIG_MEM_REMAP
#define CONFIG_SYS_TEXT_BASE 0x80000000
@ -87,7 +90,9 @@
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#endif
#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
/*
@ -95,7 +100,6 @@
*/
#define CONFIG_FTMAC100
/*
* SD (MMC) controller
*/
@ -348,7 +352,9 @@
* There are 4 banks supported for this Controller,
* but we have only 1 bank connected to flash on board
*/
#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#endif
#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
/* max number of sectors on one chip */
@ -362,4 +368,15 @@
#define CONFIG_ENV_SIZE 8192
#define CONFIG_ENV_OVERWRITE
/*
* For booting Linux, the board info and command line data
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
/* Increase max gunzip size */
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
#endif /* __CONFIG_H */