mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
* Add variable CPU clock for MPC859/866 systems (so far only TQM866M):
see doc/README.MPC866 for details; implement workaround for "SIU4" and "SIU9" silicon bugs on MPC866; calculate CPU clock frequency from PLL register values. * Add support for 128 MB RAM on TQM8xxL/M modules
This commit is contained in:
wdenk
parent
ef978730dc
commit
c178d3da6f
11 changed files with 392 additions and 157 deletions
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@ -2,6 +2,13 @@
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Changes since U-Boot 1.0.1:
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======================================================================
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* Add variable CPU clock for MPC859/866 systems (so far only TQM866M):
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see doc/README.MPC866 for details;
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implement workaround for "SIU4" and "SIU9" silicon bugs on MPC866;
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calculate CPU clock frequency from PLL register values.
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* Add support for 128 MB RAM on TQM8xxL/M modules
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* Fix PS/2 keyboard problem caused by statically initialized variable
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pointing to a location in flash
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6
Makefile
6
Makefile
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@ -483,11 +483,7 @@ TQM862M_config \
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TQM862M_66MHz_config \
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TQM862M_80MHz_config \
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TQM862M_100MHz_config \
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TQM866M_config \
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TQM866M_66MHz_config \
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TQM866M_80MHz_config \
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TQM866M_100MHz_config \
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TQM866M_133MHz_config: unconfig
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TQM866M_config: unconfig
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@ >include/config.h
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@[ -z "$(findstring _66MHz,$@)" ] || \
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{ echo "#define CONFIG_66MHz" >>include/config.h ; \
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2
README
2
README
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@ -3158,7 +3158,7 @@ Please note that U-Boot is implemented in C (and to some small parts
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in Assembler); no C++ is used, so please do not use C++ style
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comments (//) in your code.
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Please also stick to the following formatiing rules:
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Please also stick to the following formatting rules:
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- remove any trailing white space
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- use TAB characters for indentation, not spaces
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- make sure NOT to use DOS '\r\n' line feeds
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@ -128,6 +128,14 @@ int checkboard (void)
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break;
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putc (*s);
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}
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#if defined(CFG_866_CPUCLK_MIN) && defined(CFG_866_CPUCLK_MAX)
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printf (" [%d.%d...%d.%d MHz]",
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CFG_866_CPUCLK_MIN / 1000000,
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((CFG_866_CPUCLK_MIN % 1000000) + 50000) / 100000,
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CFG_866_CPUCLK_MAX / 1000000,
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((CFG_866_CPUCLK_MAX % 1000000) + 50000) / 100000
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);
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#endif
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putc ('\n');
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return (0);
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@ -139,7 +147,7 @@ long int initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size8, size9;
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long int size8, size9, size10;
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long int size_b0 = 0;
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long int size_b1 = 0;
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@ -228,9 +236,26 @@ long int initdram (int board_type)
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SDRAM_MAX_SIZE);
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debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
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if (size8 < size9) { /* leave configuration at 9 columns */
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udelay(1000);
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#if defined(CFG_MAMR_10COL)
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/*
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* try 10 column mode
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*/
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size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE2_PRELIM,
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SDRAM_MAX_SIZE);
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debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
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#else
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size10 = 0;
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#endif /* CFG_MAMR_10COL */
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if ((size8 < size10) && (size9 < size10)) {
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size_b0 = size10;
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} else if ((size8 < size9) && (size10 < size9)) {
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size_b0 = size9;
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} else { /* back to 8 columns */
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memctl->memc_mamr = CFG_MAMR_9COL;
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udelay (500);
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} else {
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size_b0 = size8;
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memctl->memc_mamr = CFG_MAMR_8COL;
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udelay (500);
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@ -272,17 +297,14 @@ long int initdram (int board_type)
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if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
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memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br3 =
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(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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if (size_b0 > 0) {
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/*
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* Position Bank 0 immediately above Bank 1
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*/
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memctl->memc_or2 =
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((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br2 =
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((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
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memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
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+ size_b1;
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} else {
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unsigned long reg;
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@ -32,16 +32,17 @@ OBJS = bedbug_860.o commproc.o cpu.o cpu_init.o \
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fec.o i2c.o interrupts.o lcd.o scc.o \
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serial.o speed.o spi.o \
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traps.o upatch.o video.o
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SOBJS = plprcr_write.o
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all: .depend $(START) $(LIB)
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$(LIB): $(OBJS)
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$(AR) crv $@ $(OBJS) kgdb.o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS) $(SOBJS) kgdb.o
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#########################################################################
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.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
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.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(SOBJS:.o=.S)
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$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(SOBJS:.o=.S) > $@
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sinclude .depend
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@ -42,7 +42,9 @@ void cpu_init_f (volatile immap_t * immr)
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{
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#ifndef CONFIG_MBX
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volatile memctl8xx_t *memctl = &immr->im_memctl;
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# ifdef CFG_PLPRCR
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ulong mfmask;
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# endif
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#endif
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ulong reg;
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@ -92,6 +94,7 @@ void cpu_init_f (volatile immap_t * immr)
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*
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* For newer (starting MPC866) chips PLPRCR layout is different.
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*/
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#ifdef CFG_PLPRCR
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if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK)
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mfmask = PLPRCR_MFACT_MSK;
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else
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@ -105,6 +108,7 @@ void cpu_init_f (volatile immap_t * immr)
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reg |= CFG_PLPRCR; /* reset control bits */
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}
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immr->im_clkrst.car_plprcr = reg;
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#endif
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/*
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* Memory Controller:
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145
cpu/mpc8xx/plprcr_write.S
Normal file
145
cpu/mpc8xx/plprcr_write.S
Normal file
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@ -0,0 +1,145 @@
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/*
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* (C) Copyright 2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <mpc8xx.h>
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#include <ppc_asm.tmpl>
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#include <asm/cache.h>
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#define CACHE_CMD_ENABLE 0x02000000
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#define CACHE_CMD_DISABLE 0x04000000
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#define CACHE_CMD_LOAD_LOCK 0x06000000
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#define CACHE_CMD_UNLOCK_LINE 0x08000000
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#define CACHE_CMD_UNLOCK_ALL 0x0A000000
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#define CACHE_CMD_INVALIDATE 0x0C000000
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#define SPEED_PLPRCR_WAIT_5CYC 150
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#define _CACHE_ALIGN_SIZE 16
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.text
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.align 2
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.globl plprcr_write_866
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/*
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* void plprcr_write_866 (long plprcr)
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* Write PLPRCR, including workaround for device errata SIU4 and SIU9.
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*/
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plprcr_write_866:
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mfspr r10, LR /* save the Link Register value */
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/* turn instruction cache on (no MMU required for instructions)
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*/
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lis r4, CACHE_CMD_ENABLE@h
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ori r4, r4, CACHE_CMD_ENABLE@l
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mtspr IC_CST, r4
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isync
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/* clear IC_CST error bits
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*/
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mfspr r4, IC_CST
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bl plprcr_here
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plprcr_here:
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mflr r5
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/* calculate relocation offset
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*/
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lis r4, plprcr_here@h
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ori r4, r4, plprcr_here@l
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sub r5, r5, r4
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/* calculate first address of this function
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*/
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lis r6, plprcr_write_866@h
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ori r6, r6, plprcr_write_866@l
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add r6, r6, r5
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/* calculate end address of this function
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*/
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lis r7, plprcr_end@h
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ori r7, r7, plprcr_end@l
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add r7, r7, r5
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/* load and lock code addresses
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*/
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mr r5, r6
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plprcr_loop:
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mtspr IC_ADR, r5
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addi r5, r5, _CACHE_ALIGN_SIZE /* increment by one line */
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lis r4, CACHE_CMD_LOAD_LOCK@h
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ori r4, r4, CACHE_CMD_LOAD_LOCK@l
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mtspr IC_CST, r4
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isync
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cmpw r5, r7
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blt plprcr_loop
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/* IC_CST error bits not evaluated
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*/
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/* switch PLPRCR
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*/
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mfspr r4, IMMR /* read IMMR */
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rlwinm r4, r4, 0, 0, 15 /* only high 16 bits count */
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/* write sequence according to MPC866 Errata
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*/
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stw r3, PLPRCR(r4)
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isync
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lis r3, SPEED_PLPRCR_WAIT_5CYC@h
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ori r3, r3, SPEED_PLPRCR_WAIT_5CYC@l
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plprcr_wait:
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cmpwi r3, 0
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beq plprcr_wait_end
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nop
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subi r3, r3, 1
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b plprcr_wait
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plprcr_wait_end:
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/* turn instruction cache off
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*/
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lis r4, CACHE_CMD_UNLOCK_ALL@h
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ori r4, r4, CACHE_CMD_UNLOCK_ALL@l
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mtspr IC_CST, r4
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isync
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lis r4, CACHE_CMD_INVALIDATE@h
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ori r4, r4, CACHE_CMD_INVALIDATE@l
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mtspr IC_CST, r4
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isync
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lis r4, CACHE_CMD_DISABLE@h
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ori r4, r4, CACHE_CMD_DISABLE@l
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mtspr IC_CST, r4
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isync
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mtspr LR, r10 /* restore original Link Register value */
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blr
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plprcr_end:
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@ -25,6 +25,8 @@
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#include <mpc8xx.h>
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#include <asm/processor.h>
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#ifndef CONFIG_TQM866M
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#define PITC_SHIFT 16
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#define PITR_SHIFT 16
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/* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */
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@ -203,4 +205,117 @@ int get_clocks (void)
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return (0);
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}
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#else /* CONFIG_MPC866_et_al */
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static long init_pll_866 (long clk);
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/* This function sets up PLL (init_pll_866() is called) and
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* fills gd->cpu_clk and gd->bus_clk according to the environment
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* variable 'cpuclk' or to CFG_866_CPUCLK_DEFAULT (if 'cpuclk'
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* contains invalid value).
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* This functions requires an MPC866 series CPU.
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*/
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int get_clocks_866 (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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char tmp[64];
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long cpuclk = 0;
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if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
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cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
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if ((CFG_866_CPUCLK_MIN > cpuclk) || (CFG_866_CPUCLK_MAX < cpuclk))
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cpuclk = CFG_866_CPUCLK_DEFAULT;
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gd->cpu_clk = init_pll_866 (cpuclk);
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if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0)
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gd->bus_clk = gd->cpu_clk;
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else
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gd->bus_clk = gd->cpu_clk / 2;
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return (0);
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}
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/* Adjust sdram refresh rate to actual CPU clock.
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*/
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int sdram_adjust_866 (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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long mamr;
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mamr = immr->im_memctl.memc_mamr;
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mamr &= ~MAMR_PTA_MSK;
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mamr |= ((gd->cpu_clk / CFG_866_PTA_PER_CLK) << MAMR_PTA_SHIFT);
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immr->im_memctl.memc_mamr = mamr;
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return (0);
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}
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/* Configure PLL for MPC866/859 CPU series
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* PLL multiplication factor is set to the value nearest to the desired clk,
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* assuming a oscclk of 10 MHz.
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*/
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static long init_pll_866 (long clk)
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{
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extern void plprcr_write_866 (long);
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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long n, plprcr;
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char mfi, mfn, mfd, s, pdf;
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long step_mfi, step_mfn;
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pdf = 0;
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if (clk < 80000000) {
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s = 1;
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step_mfi = CFG_866_OSCCLK / 2;
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mfd = 14;
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step_mfn = CFG_866_OSCCLK / 30;
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} else {
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s = 0;
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step_mfi = CFG_866_OSCCLK;
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mfd = 29;
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step_mfn = CFG_866_OSCCLK / 30;
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}
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/* Calculate integer part of multiplication factor
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*/
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n = clk / step_mfi;
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mfi = (char)n;
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/* Calculate numerator of fractional part of multiplication factor
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*/
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n = clk - (n * step_mfi);
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mfn = (char)(n / step_mfn);
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/* Calculate effective clk
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*/
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n = (mfi * step_mfi) + (mfn * step_mfn);
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immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
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plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK
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| PLPRCR_MFD_MSK | PLPRCR_S_MSK
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| PLPRCR_MFI_MSK | PLPRCR_DBRMO))
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| (mfn << PLPRCR_MFN_SHIFT)
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| (mfd << PLPRCR_MFD_SHIFT)
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| (s << PLPRCR_S_SHIFT)
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| (mfi << PLPRCR_MFI_SHIFT)
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| (pdf << PLPRCR_PDF_SHIFT);
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if( (mfn > 0) && ((mfd / mfn) > 10) )
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plprcr |= PLPRCR_DBRMO;
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plprcr_write_866 (plprcr); /* set value using SIU4/9 workaround */
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immr->im_clkrstk.cark_plprcrk = 0x00000000;
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return (n);
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}
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#endif /* CONFIG_MPC866_et_al */
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/* ------------------------------------------------------------------------- */
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@ -355,6 +355,8 @@ int serial_tstc (void);
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/* $(CPU)/speed.c */
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int get_clocks (void);
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int get_clocks_866 (void);
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int sdram_adjust_866 (void);
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#if defined(CONFIG_8260)
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int prt_8260_clks (void);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -36,7 +36,12 @@
|
|||
#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
|
||||
#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
|
||||
|
||||
#define CFG_8XX_XIN 10000000 /* XXX XXX XXX */
|
||||
#define CFG_866_OSCCLK 10000000 /* 10 MHz - PLL input clock */
|
||||
#define CFG_866_CPUCLK_MIN 40000000 /* 40 MHz - CPU minimum clock */
|
||||
#define CFG_866_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
|
||||
#define CFG_866_CPUCLK_DEFAULT 100000000 /* 100 MHz - CPU default clock */
|
||||
/* (it will be used if there is no */
|
||||
/* 'cpuclk' variable with valid value) */
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
#undef CONFIG_8xx_CONS_SMC2
|
||||
|
|
@ -278,29 +283,6 @@
|
|||
*/
|
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* set PLL multiplication factor
|
||||
*/
|
||||
#if defined(CONFIG_133MHz)
|
||||
/* for 133 MHz, we use a 10 MHz clock:
|
||||
* MFN = 0x09, MFD = 0x1D, S = 0, MFI = 13
|
||||
*/
|
||||
#define CFG_PLPRCR \
|
||||
( 9 << PLPRCR_MFN_SHIFT | 0x1D << PLPRCR_MFD_SHIFT | \
|
||||
0 << PLPRCR_S_SHIFT | 0x0D << PLPRCR_MFI_SHIFT | \
|
||||
PLPRCR_TEXPS )
|
||||
#elif defined(CONFIG_80MHz) /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MFI_SHIFT | PLPRCR_TEXPS )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR ( PLPRCR_SPLSS | PLPRCR_TEXPS )
|
||||
#endif /* CONFIG_??MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
|
|
@ -308,22 +290,9 @@
|
|||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#if defined(CONFIG_133MHz) /* for 133 MHz, we use a 10 MHz clock * 13 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#elif defined(CONFIG_80MHz) /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_??MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
|
|
@ -390,27 +359,10 @@
|
|||
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
|
||||
|
||||
/*
|
||||
* FLASH timing:
|
||||
* FLASH timing: Default value of OR0 after reset
|
||||
*/
|
||||
#if defined(CONFIG_133MHz)
|
||||
/* 133 MHz CPU - 66 MHz bus: */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_100MHz)
|
||||
/* 100 MHz CPU - 50 MHz bus: */
|
||||
#elif defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
|
||||
OR_SCY_15_CLK | OR_TRLX)
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
|
|
@ -446,42 +398,21 @@
|
|||
#endif /* CONFIG_CAN_DRIVER */
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*
|
||||
* The Divider for PTA (refresh timer) configuration is based on an
|
||||
* example SDRAM configuration (64 MBit, one bank). The adjustment to
|
||||
* the number of chip selects (NCS) and the actually needed refresh
|
||||
* rate is done by setting MPTPR.
|
||||
*
|
||||
* PTA is calculated from
|
||||
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
|
||||
*
|
||||
* gclk CPU clock (not bus clock!)
|
||||
* Trefresh Refresh cycle * 4 (four word bursts used)
|
||||
*
|
||||
* 4096 Rows from SDRAM example configuration
|
||||
* 1000 factor s -> ms
|
||||
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
|
||||
* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
|
||||
* 4 Number of refresh cycles per period
|
||||
* 64 Refresh cycle in ms per number of rows
|
||||
* --------------------------------------------
|
||||
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
|
||||
*
|
||||
* 50 MHz => 50.000.000 / Divider = 98
|
||||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_133MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#elif defined(CONFIG_100MHz)
|
||||
#define CFG_MAMR_PTA 98
|
||||
#elif defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
#define CFG_866_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
* Periodic timer for refresh, start with refresh rate for 40 MHz clock
|
||||
* (CFG_866_CPUCLK_MIN / CFG_866_PTA_PER_CLK)
|
||||
*/
|
||||
#define CFG_MAMR_PTA 39
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
|
@ -510,6 +441,10 @@
|
|||
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
/* 10 column SDRAM */
|
||||
#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
|
|
|
|||
|
|
@ -260,8 +260,11 @@ init_fnc_t *init_sequence[] = {
|
|||
#if defined(CONFIG_BOARD_EARLY_INIT_F)
|
||||
board_early_init_f,
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_TQM866M)
|
||||
get_clocks, /* get CPU and bus clocks (etc.) */
|
||||
init_timebase,
|
||||
#endif
|
||||
#ifdef CFG_ALLOC_DPRAM
|
||||
#if !(defined(CONFIG_8260) || defined(CONFIG_MPC8560))
|
||||
dpram_init,
|
||||
|
|
@ -271,6 +274,11 @@ init_fnc_t *init_sequence[] = {
|
|||
board_postclk_init,
|
||||
#endif
|
||||
env_init,
|
||||
#if defined(CONFIG_TQM866M)
|
||||
get_clocks_866, /* get CPU and bus clocks according to the environment variable */
|
||||
sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */
|
||||
init_timebase,
|
||||
#endif
|
||||
init_baudrate,
|
||||
serial_init,
|
||||
console_init_f,
|
||||
|
|
|
|||
Loading…
Reference in a new issue