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imx6ul: synchronise device tree with linux

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Synchronise device tree with linux v6.0-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Marcel Ziswiler 2022-10-22 23:59:32 +02:00 • committed by Stefano Babic
parent 8dff3abbbc
commit bf947d2a4b
3 changed files with 19 additions and 24 deletions
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2
arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi
View file

@ -8,7 +8,7 @@
display0 = &lcdif;
};
&{/soc} {
&soc {
u-boot,dm-pre-reloc;
};

5
arch/arm/dts/imx6ul-phytec-segin.dtsi
View file

@ -83,11 +83,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
vref-supply = <&reg_adc1_vref_3v3>;
/*
* driver can not separate a specific channel so we request 4 channels
* here - we need only the fourth channel
*/
num-channels = <4>;
status = "disabled";
};

36
arch/arm/dts/imx6ul.dtsi
View file

@ -64,20 +64,18 @@
clock-frequency = <696000000>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
operating-points = <
operating-points =
/* kHz uV */
696000 1275000
528000 1175000
396000 1025000
198000 950000
>;
fsl,soc-operating-points = <
<696000 1275000>,
<528000 1175000>,
<396000 1025000>,
<198000 950000>;
fsl,soc-operating-points =
/* KHz uV */
696000 1275000
528000 1175000
396000 1175000
198000 1175000
>;
<696000 1275000>,
<528000 1175000>,
<396000 1175000>,
<198000 1175000>;
clocks = <&clks IMX6UL_CLK_ARM>,
<&clks IMX6UL_CLK_PLL2_BUS>,
<&clks IMX6UL_CLK_PLL2_PFD2>,
@ -139,7 +137,7 @@
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@ -149,6 +147,9 @@
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
ranges = <0 0x00900000 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
};
intc: interrupt-controller@a01000 {
@ -543,7 +544,7 @@
};
kpp: keypad@20b8000 {
compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_KPP>;
@ -923,7 +924,6 @@
reg = <0x02198000 0x4000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_ADC1>;
num-channels = <2>;
clock-names = "adc";
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
@ -998,7 +998,7 @@
};
csi: csi@21c4000 {
compatible = "fsl,imx6ul-csi", "fsl,imx7-csi";
compatible = "fsl,imx6ul-csi";
reg = <0x021c4000 0x4000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_CSI>;
@ -1007,7 +1007,7 @@
};
lcdif: lcdif@21c8000 {
compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif";
reg = <0x021c8000 0x4000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
@ -1028,7 +1028,7 @@
qspi: spi@21e0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
compatible = "fsl,imx6ul-qspi";
reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;