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MIPS: add support for Broadcom MIPS BCM6348 SoC family
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Álvaro Fernández Rojas
Daniel Schwierzeck
parent
5a0efcf78a
commit
bf9012b808
6 changed files with 215 additions and 1 deletions
127
arch/mips/dts/brcm,bcm6348.dtsi
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127
arch/mips/dts/brcm,bcm6348.dtsi
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dt-bindings/clock/bcm6348-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/reset/bcm6348-reset.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "brcm,bcm6348";
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cpus {
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reg = <0xfffe0000 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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u-boot,dm-pre-reloc;
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cpu@0 {
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compatible = "brcm,bcm6348-cpu", "mips,mips4Kc";
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device_type = "cpu";
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reg = <0>;
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u-boot,dm-pre-reloc;
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};
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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u-boot,dm-pre-reloc;
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periph_osc: periph-osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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u-boot,dm-pre-reloc;
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};
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periph_clk: periph-clk {
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compatible = "brcm,bcm6345-clk";
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reg = <0xfffe0004 0x4>;
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#clock-cells = <1>;
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};
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};
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pflash: nor@1fc00000 {
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compatible = "cfi-flash";
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reg = <0x1fc00000 0x2000000>;
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bank-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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};
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ubus {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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u-boot,dm-pre-reloc;
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pll_cntl: syscon@fffe0008 {
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compatible = "syscon";
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reg = <0xfffe0008 0x4>;
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};
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syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&pll_cntl>;
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offset = <0x0>;
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mask = <0x1>;
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};
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periph_rst: reset-controller@fffe0028 {
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compatible = "brcm,bcm6345-reset";
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reg = <0xfffe0028 0x4>;
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#reset-cells = <1>;
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};
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wdt: watchdog@fffe021c {
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compatible = "brcm,bcm6345-wdt";
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reg = <0xfffe021c 0xc>;
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clocks = <&periph_osc>;
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdt>;
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};
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uart0: serial@fffe0300 {
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compatible = "brcm,bcm6345-uart";
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reg = <0xfffe0300 0x18>;
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clocks = <&periph_osc>;
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status = "disabled";
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};
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gpio1: gpio-controller@fffe0400 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0xfffe0400 0x4>, <0xfffe0408 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <5>;
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status = "disabled";
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};
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gpio0: gpio-controller@fffe0404 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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memory-controller@fffe2300 {
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compatible = "brcm,bcm6338-mc";
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reg = <0xfffe2300 0x38>;
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u-boot,dm-pre-reloc;
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};
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};
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};
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@ -3,6 +3,7 @@ menu "Broadcom MIPS platforms"
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config SYS_SOC
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default "bcm6328" if SOC_BMIPS_BCM6328
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default "bcm6348" if SOC_BMIPS_BCM6348
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default "bcm6358" if SOC_BMIPS_BCM6358
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default "bcm63268" if SOC_BMIPS_BCM63268
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@ -20,6 +21,17 @@ config SOC_BMIPS_BCM6328
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help
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This supports BMIPS BCM6328 family including BCM63281 and BCM63283.
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config SOC_BMIPS_BCM6348
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bool "BMIPS BCM6348 family"
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select MIPS_TUNE_4KC
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select MIPS_L1_CACHE_SHIFT_4
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select SWAP_IO_SPACE
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select SYSRESET_WATCHDOG
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help
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This supports BMIPS BCM6348 family.
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config SOC_BMIPS_BCM6358
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bool "BMIPS BCM6358 family"
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select SUPPORTS_BIG_ENDIAN
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@ -18,7 +18,8 @@ static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
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static inline int is_bmips_internal_registers(phys_addr_t offset)
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{
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#if defined(CONFIG_SOC_BMIPS_BCM6358)
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#if defined(CONFIG_SOC_BMIPS_BCM6348) || \
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defined(CONFIG_SOC_BMIPS_BCM6358)
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if (offset >= 0xfffe0000)
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return 1;
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#endif
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30
include/configs/bmips_bcm6348.h
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30
include/configs/bmips_bcm6348.h
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_BMIPS_BCM6348_H
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#define __CONFIG_BMIPS_BCM6348_H
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/* CPU */
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#define CONFIG_SYS_MIPS_TIMER_FREQ 128000000
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/* RAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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/* U-Boot */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
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#if defined(CONFIG_BMIPS_BOOT_RAM)
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
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#endif
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#define CONFIG_SYS_FLASH_BASE 0xbfc00000
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
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#endif /* __CONFIG_BMIPS_BCM6348_H */
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22
include/dt-bindings/clock/bcm6348-clock.h
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22
include/dt-bindings/clock/bcm6348-clock.h
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DT_BINDINGS_CLOCK_BCM6348_H
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#define __DT_BINDINGS_CLOCK_BCM6348_H
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#define BCM6348_CLK_ADSL 0
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#define BCM6348_CLK_MPI 1
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#define BCM6348_CLK_SDRAM 2
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#define BCM6348_CLK_M2M 3
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#define BCM6348_CLK_ENET 4
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#define BCM6348_CLK_SAR 5
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#define BCM6348_CLK_USBS 6
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#define BCM6348_CLK_USBH 8
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#define BCM6348_CLK_SPI 9
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#endif /* __DT_BINDINGS_CLOCK_BCM6348_H */
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22
include/dt-bindings/reset/bcm6348-reset.h
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22
include/dt-bindings/reset/bcm6348-reset.h
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DT_BINDINGS_RESET_BCM6348_H
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#define __DT_BINDINGS_RESET_BCM6348_H
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#define BCM6348_RST_SPI 0
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#define BCM6348_RST_ENET 2
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#define BCM6348_RST_USBH 3
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#define BCM6348_RST_USBS 4
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#define BCM6348_RST_ADSL 5
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#define BCM6348_RST_DMAMEM 6
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#define BCM6348_RST_SAR 7
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#define BCM6348_RST_ACLC 8
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#define BCM6348_RST_ADSL_MIPS 10
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#endif /* __DT_BINDINGS_RESET_BCM6348_H */
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