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Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

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This commit is contained in:
Tom Rini 2017-05-23 16:22:03 -04:00
commit be62fbf376
26 changed files with 8351 additions and 847 deletions
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18
arch/arm/mach-rmobile/Kconfig.64
View file

@ -1,7 +1,15 @@
if RCAR_GEN3
choice
prompt "Select Target SoC"
config R8A7795
bool
bool "Renesas SoC R8A7795"
config R8A7796
bool "Renesas SoC R8A7796"
endchoice
choice
prompt "Renesus ARM64 SoCs board select"
@ -9,20 +17,14 @@ choice
config TARGET_SALVATOR_X
bool "Salvator-X board"
select R8A7795
help
Support for Renesas R-Car Gen3 R8a7795 platform
Support for Renesas R-Car Gen3 platform
endchoice
config SYS_SOC
default "rmobile"
config RCAR_GEN3_EXTRAM_BOOT
bool "Enable boot from RAM"
depends on TARGET_SALVATOR_X
default n
source "board/renesas/salvator-x/Kconfig"
endif

1
arch/arm/mach-rmobile/Makefile
View file

@ -17,5 +17,6 @@ obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o
obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o memmap-r8a7795.o
obj-$(CONFIG_R8A7796) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7796.o memmap-r8a7796.o
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o

19
arch/arm/mach-rmobile/cpu_info-rcar.c
View file

@ -8,7 +8,10 @@
#include <common.h>
#include <asm/io.h>
#define PRR 0xFF000044
#define PRR 0xFF000044
#define PRR_MASK 0x7fff
#define R8A7796_REV_1_0 0x5200
#define R8A7796_REV_1_1 0x5210
u32 rmobile_get_cpu_type(void)
{
@ -17,10 +20,20 @@ u32 rmobile_get_cpu_type(void)
u32 rmobile_get_cpu_rev_integer(void)
{
return ((readl(PRR) & 0x000000F0) >> 4) + 1;
const u32 prr = readl(PRR);
if ((prr & PRR_MASK) == R8A7796_REV_1_1)
return 1;
else
return ((prr & 0x000000F0) >> 4) + 1;
}
u32 rmobile_get_cpu_rev_fraction(void)
{
return readl(PRR) & 0x0000000F;
const u32 prr = readl(PRR);
if ((prr & PRR_MASK) == R8A7796_REV_1_1)
return 1;
else
return prr & 0x0000000F;
}

2
arch/arm/mach-rmobile/cpu_info.c
View file

@ -56,6 +56,8 @@ static const struct {
{ 0x4A, "R8A7792" },
{ 0x4B, "R8A7793" },
{ 0x4C, "R8A7794" },
{ 0x4F, "R8A7795" },
{ 0x52, "R8A7796" },
{ 0x0, "CPU" },
};

3
arch/arm/mach-rmobile/include/mach/gpio.h
View file

@ -25,6 +25,9 @@ void r8a7794_pinmux_init(void);
#elif defined(CONFIG_R8A7795)
#include "r8a7795-gpio.h"
void r8a7795_pinmux_init(void);
#elif defined(CONFIG_R8A7796)
#include "r8a7796-gpio.h"
void r8a7796_pinmux_init(void);
#endif
#endif /* __ASM_ARCH_GPIO_H */

186
arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h
View file

@ -2,7 +2,7 @@
* arch/arm/include/asm/arch-rcar_gen3/r8a7795-gpio.h
* This file defines pin function control of gpio.
*
* Copyright (C) 2015 Renesas Electronics Corporation
* Copyright (C) 2015-2016 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -13,6 +13,8 @@
* GPIO_FN_xx - GPIO used to select pin function
* GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
*/
/* V2(ES2.0) */
enum {
GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
@ -26,6 +28,7 @@ enum {
GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
GPIO_GP_1_28,
GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
@ -81,6 +84,7 @@ enum {
GPIO_GFN_D0,
/* GPSR1 */
GPIO_GFN_CLKOUT,
GPIO_GFN_EX_WAIT0_A,
GPIO_GFN_WE1x,
GPIO_GFN_WE0x,
@ -146,23 +150,23 @@ enum {
GPIO_GFN_SD0_CLK,
/* GPSR4 */
GPIO_FN_SD3_DS,
GPIO_GFN_SD3_DS,
GPIO_GFN_SD3_DAT7,
GPIO_GFN_SD3_DAT6,
GPIO_GFN_SD3_DAT5,
GPIO_GFN_SD3_DAT4,
GPIO_FN_SD3_DAT3,
GPIO_FN_SD3_DAT2,
GPIO_FN_SD3_DAT1,
GPIO_FN_SD3_DAT0,
GPIO_FN_SD3_CMD,
GPIO_FN_SD3_CLK,
GPIO_GFN_SD3_DAT3,
GPIO_GFN_SD3_DAT2,
GPIO_GFN_SD3_DAT1,
GPIO_GFN_SD3_DAT0,
GPIO_GFN_SD3_CMD,
GPIO_GFN_SD3_CLK,
GPIO_GFN_SD2_DS,
GPIO_GFN_SD2_DAT3,
GPIO_GFN_SD2_DAT2,
GPIO_GFN_SD2_DAT1,
GPIO_GFN_SD2_DAT0,
GPIO_FN_SD2_CMD,
GPIO_GFN_SD2_CMD,
GPIO_GFN_SD2_CLK,
/* GPSR5 */
@ -194,8 +198,8 @@ enum {
GPIO_GFN_SCK0,
/* GPSR6 */
GPIO_GFN_USB31_OVC,
GPIO_GFN_USB31_PWEN,
GPIO_GFN_USB3_OVC,
GPIO_GFN_USB3_PWEN,
GPIO_GFN_USB30_OVC,
GPIO_GFN_USB30_PWEN,
GPIO_GFN_USB1_OVC,
@ -224,8 +228,8 @@ enum {
GPIO_GFN_SSI_SDATA2_A,
GPIO_GFN_SSI_SDATA1_A,
GPIO_GFN_SSI_SDATA0,
GPIO_GFN_SSI_WS0129,
GPIO_GFN_SSI_SCK0129,
GPIO_GFN_SSI_WS01239,
GPIO_GFN_SSI_SCK01239,
/* GPSR7 */
GPIO_FN_HDMI1_CEC,
@ -237,7 +241,7 @@ enum {
GPIO_IFN_AVB_MDC,
GPIO_FN_MSIOF2_SS2_C,
GPIO_IFN_AVB_MAGIC,
GPIO_FN_MSIOF2_S1_C,
GPIO_FN_MSIOF2_SS1_C,
GPIO_FN_SCK4_A,
GPIO_IFN_AVB_PHY_INT,
GPIO_FN_MSIOF2_SYNC_C,
@ -248,6 +252,7 @@ enum {
GPIO_IFN_AVB_AVTP_MATCH_A,
GPIO_FN_MSIOF2_RXD_C,
GPIO_FN_CTS4x_A,
GPIO_FN_FSCLKST2x_A,
GPIO_IFN_AVB_AVTP_CAPTURE_A,
GPIO_FN_MSIOF2_TXD_C,
GPIO_FN_RTS4x_TANS_A,
@ -257,50 +262,53 @@ enum {
GPIO_FN_VI4_DATA0_B,
GPIO_FN_CAN0_TX_B,
GPIO_FN_CANFD0_TX_B,
GPIO_FN_MSIOF3_SS2_E,
GPIO_IFN_IRQ1,
GPIO_FN_QPOLA,
GPIO_FN_DU_DISP,
GPIO_FN_VI4_DATA1_B,
GPIO_FN_CAN0_RX_B,
GPIO_FN_CANFD0_RX_B,
GPIO_FN_MSIOF3_SS1_E,
/* IPSR1 */
GPIO_IFN_IRQ2,
GPIO_FN_QCPV_QDE,
GPIO_FN_DU_EXODDF_DU_ODDF_DISP_CDE,
GPIO_FN_VI4_DATA2_B,
GPIO_FN_MSIOF3_SYNC_E,
GPIO_FN_PWM3_B,
GPIO_IFN_IRQ3,
GPIO_FN_QSTVB_QVE,
GPIO_FN_A25,
GPIO_FN_DU_DOTCLKOUT1,
GPIO_FN_VI4_DATA3_B,
GPIO_FN_MSIOF3_SCK_E,
GPIO_FN_PWM4_B,
GPIO_IFN_IRQ4,
GPIO_FN_QSTH_QHS,
GPIO_FN_A24,
GPIO_FN_DU_EXHSYNC_DU_HSYNC,
GPIO_FN_VI4_DATA4_B,
GPIO_FN_MSIOF3_RXD_E,
GPIO_FN_PWM5_B,
GPIO_IFN_IRQ5,
GPIO_FN_QSTB_QHE,
GPIO_FN_A23,
GPIO_FN_DU_EXVSYNC_DU_VSYNC,
GPIO_FN_VI4_DATA5_B,
GPIO_FN_FSCLKST2x_B,
GPIO_FN_MSIOF3_TXD_E,
GPIO_FN_PWM6_B,
GPIO_IFN_PWM0,
GPIO_FN_AVB_AVTP_PPS,
GPIO_FN_A22,
GPIO_FN_VI4_DATA6_B,
GPIO_FN_IECLK_B,
GPIO_IFN_PWM1_A,
GPIO_FN_A21,
GPIO_FN_HRX3_D,
GPIO_FN_VI4_DATA7_B,
GPIO_FN_IERX_B,
GPIO_IFN_PWM2_A,
GPIO_FN_PWMFSW0,
GPIO_FN_A20,
GPIO_FN_HTX3_D,
GPIO_FN_IETX_B,
GPIO_IFN_A0,
@ -382,7 +390,6 @@ enum {
GPIO_FN_SCL6_A,
GPIO_FN_AVB_AVTP_CAPTURE_B,
GPIO_FN_PWM2_B,
GPIO_FN_SPV_EVEN,
GPIO_IFN_A12,
GPIO_FN_LCDOUT12,
GPIO_FN_MSIOF3_SCK_C,
@ -588,67 +595,94 @@ enum {
GPIO_IFN_SD1_CLK,
GPIO_FN_MSIOF1_SCK_G,
GPIO_FN_SIM0_CLK_A,
GPIO_IFN_SD1_CMD,
GPIO_FN_MSIOF1_SYNC_G,
GPIO_FN_NFCEx_B,
GPIO_FN_SIM0_D_A,
GPIO_FN_STP_IVCXO27_1_B,
GPIO_IFN_SD1_DAT0,
GPIO_FN_SD2_DAT4,
GPIO_FN_MSIOF1_RXD_G,
GPIO_FN_NFWPx_B,
GPIO_FN_TS_SCK1_B,
GPIO_FN_STP_ISCLK_1_B,
GPIO_IFN_SD1_DAT1,
GPIO_FN_SD2_DAT5,
GPIO_FN_MSIOF1_TXD_G,
GPIO_FN_NFDATA14_B,
GPIO_FN_TS_SPSYNC1_B,
GPIO_FN_STP_ISSYNC_1_B,
GPIO_IFN_SD1_DAT2,
GPIO_FN_SD2_DAT6,
GPIO_FN_MSIOF1_SS1_G,
GPIO_FN_NFDATA15_B,
GPIO_FN_TS_SDAT1_B,
GPIO_FN_STP_IOD_1_B,
GPIO_IFN_SD1_DAT3,
GPIO_FN_SD2_DAT7,
GPIO_FN_MSIOF1_SS2_G,
GPIO_FN_NFRBx_B,
GPIO_FN_TS_SDEN1_B,
GPIO_FN_STP_ISEN_1_B,
/* IPSR9 */
GPIO_IFN_SD2_CLK,
GPIO_FN_SCKZ_A,
GPIO_FN_NFDATA8,
GPIO_IFN_SD2_CMD,
GPIO_FN_NFDATA9,
GPIO_IFN_SD2_DAT0,
GPIO_FN_MTSx_A,
GPIO_FN_NFDATA10,
GPIO_IFN_SD2_DAT1,
GPIO_FN_STMx_A,
GPIO_FN_NFDATA11,
GPIO_IFN_SD2_DAT2,
GPIO_FN_MDATA_A,
GPIO_FN_NFDATA12,
GPIO_IFN_SD2_DAT3,
GPIO_FN_SDATA_A,
GPIO_FN_NFDATA13,
GPIO_IFN_SD2_DS,
GPIO_FN_NFALE,
GPIO_FN_SATA_DEVSLP_B,
GPIO_FN_VSP_A,
GPIO_IFN_SD3_DAT4,
GPIO_FN_SD2_CD_A,
GPIO_IFN_SD3_DAT5,
GPIO_FN_SD2_WP_A,
GPIO_IFN_SD3_CLK,
GPIO_FN_NFWEx,
/* IPSR10 */
GPIO_IFN_SD3_CMD,
GPIO_FN_NFREx,
GPIO_IFN_SD3_DAT0,
GPIO_FN_NFDATA0,
GPIO_IFN_SD3_DAT1,
GPIO_FN_NFDATA1,
GPIO_IFN_SD3_DAT2,
GPIO_FN_NFDATA2,
GPIO_IFN_SD3_DAT3,
GPIO_FN_NFDATA3,
GPIO_IFN_SD3_DAT4,
GPIO_FN_SD2_CD_A,
GPIO_FN_NFDATA4,
GPIO_IFN_SD3_DAT5,
GPIO_FN_SD2_WP_A,
GPIO_FN_NFDATA5,
GPIO_IFN_SD3_DAT6,
GPIO_FN_SD3_CD,
GPIO_FN_NFDATA6,
/* IPSR11 */
GPIO_IFN_SD3_DAT7,
GPIO_FN_SD3_WP,
GPIO_FN_NFDATA7,
GPIO_IFN_SD3_DS,
GPIO_FN_NFCLE,
GPIO_IFN_SD0_CD,
GPIO_FN_NFDATA14_A,
GPIO_FN_SCL2_B,
GPIO_FN_SIM0_RST_A,
GPIO_IFN_SD0_WP,
GPIO_FN_NFDATA15_A,
GPIO_FN_SDA2_B,
GPIO_IFN_SD1_CD,
GPIO_FN_NFRBx_A,
GPIO_FN_SIM0_CLK_B,
GPIO_IFN_SD1_WP,
GPIO_FN_NFCEx_A,
GPIO_FN_SIM0_D_B,
GPIO_IFN_SCK0,
GPIO_FN_HSCK1_B,
@ -656,16 +690,17 @@ enum {
GPIO_FN_AUDIO_CLKC_B,
GPIO_FN_SDA2_A,
GPIO_FN_SIM0_RST_B,
GPIO_FN_STP_OPWM__C,
GPIO_FN_STP_OPWM_0_C,
GPIO_FN_RIF0_CLK_B,
GPIO_FN_ADICHS2,
GPIO_FN_SCK5_B,
GPIO_IFN_RX0,
GPIO_FN_HRX1_B,
GPIO_FN_TS_SCK0_C,
GPIO_FN_STP_ISCLK_0_C,
GPIO_FN_RIF0_D0_B,
/* IPSR11 */
/* IPSR12 */
GPIO_IFN_TX0,
GPIO_FN_HTX1_B,
GPIO_FN_TS_SPSYNC0_C,
@ -690,7 +725,7 @@ enum {
GPIO_IFN_RX1_A,
GPIO_FN_HRX1_A,
GPIO_FN_TS_SDAT0_C,
GPIO_FN_STP_IDS_0_C,
GPIO_FN_STP_ISD_0_C,
GPIO_FN_RIF1_CLK_C,
GPIO_IFN_TX1_A,
GPIO_FN_HTX1_A,
@ -719,21 +754,19 @@ enum {
GPIO_FN_RIF1_CLK_B,
GPIO_FN_ADICLK,
/* IPSR12 */
/* IPSR13 */
GPIO_IFN_TX2_A,
GPIO_FN_SD2_CD_B,
GPIO_FN_SCL1_A,
GPIO_FN_RSD_CLK_B,
GPIO_FN_FMCLK_A,
GPIO_FN_RIF1_D1_C,
GPIO_FN_FSO_CFE_0_B,
GPIO_FN_FSO_CFE_0x,
GPIO_IFN_RX2_A,
GPIO_FN_SD2_WP_B,
GPIO_FN_SDA1_A,
GPIO_FN_RDS_DATA_B,
GPIO_FN_RMIN_A,
GPIO_FN_FMIN_A,
GPIO_FN_RIF1_SYNC_C,
GPIO_FN_FSO_CEF_1_B,
GPIO_FN_FSO_CFE_1x,
GPIO_IFN_HSCK0,
GPIO_FN_MSIOF1_SCK_D,
GPIO_FN_AUDIO_CLKB_A,
@ -741,21 +774,19 @@ enum {
GPIO_FN_TS_SCK0_D,
GPIO_FN_STP_ISCLK_0_D,
GPIO_FN_RIF0_CLK_C,
GPIO_FN_AD_CLK,
GPIO_FN_RX5_B,
GPIO_IFN_HRX0,
GPIO_FN_MSIOF1_RXD_D,
GPIO_FN_SS1_SDATA2_B,
GPIO_FN_SSI_SDATA2_B,
GPIO_FN_TS_SDEN0_D,
GPIO_FN_STP_ISEN_0_D,
GPIO_FN_RIF0_D0_C,
GPIO_FN_AD_DI,
GPIO_IFN_HTX0,
GPIO_FN_MSIOF1_TXD_D,
GPIO_FN_SSI_SDATA9_B,
GPIO_FN_TS_SDAT0_D,
GPIO_FN_STP_ISD_0_D,
GPIO_FN_RIF0_D1_C,
GPIO_FN_AD_DO,
GPIO_IFN_HCTS0x,
GPIO_FN_RX2_B,
GPIO_FN_MSIOF1_SYNC_D,
@ -764,7 +795,6 @@ enum {
GPIO_FN_STP_ISSYNC_0_D,
GPIO_FN_RIF0_SYNC_C,
GPIO_FN_AUDIO_CLKOUT1_A,
GPIO_FN_AD_NSCx,
GPIO_IFN_HRTS0x,
GPIO_FN_TX2_B,
GPIO_FN_MSIOF1_SS1_D,
@ -774,22 +804,23 @@ enum {
GPIO_FN_AUDIO_CLKOUT2_A,
GPIO_IFN_MSIOF0_SYNC,
GPIO_FN_AUDIO_CLKOUT_A,
GPIO_FN_TX5_B,
GPIO_FN_BPFCLK_D,
/* IPSR13 */
/* IPSR14 */
GPIO_IFN_MSIOF0_SS1,
GPIO_FN_RX5,
GPIO_FN_RX5_A,
GPIO_FN_NFWPx_A,
GPIO_FN_AUDIO_CLKA_C,
GPIO_FN_SSI_SCK2_A,
GPIO_FN_RDS_CLK_A,
GPIO_FN_STP_IVCXO27_0_C,
GPIO_FN_AUDIO_CLKOUT3_A,
GPIO_FN_TCLK1_B,
GPIO_IFN_MSIOF0_SS2,
GPIO_FN_TX5,
GPIO_FN_TX5_A,
GPIO_FN_MSIOF1_SS2_D,
GPIO_FN_AUDIO_CLKC_A,
GPIO_FN_SSI_WS2_A,
GPIO_FN_RDS_DATA_A,
GPIO_FN_STP_OPWM_0_D,
GPIO_FN_AUDIO_CLKOUT_D,
GPIO_FN_SPEEDIN_B,
@ -803,17 +834,17 @@ enum {
GPIO_IFN_MLB_DAT,
GPIO_FN_TX1_B,
GPIO_FN_MSIOF1_RXD_F,
GPIO_IFN_SSI_SCK0129,
GPIO_IFN_SSI_SCK01239,
GPIO_FN_MSIOF1_TXD_F,
GPIO_FN_MOUT0,
GPIO_IFN_SSI_WS0129,
GPIO_IFN_SSI_WS01239,
GPIO_FN_MSIOF1_SS1_F,
GPIO_FN_MOUT1,
GPIO_IFN_SSI_SDATA0,
GPIO_FN_MSIOF1_SS2_F,
GPIO_FN_MOUT2,
/* IPSR14 */
/* IPSR15 */
GPIO_IFN_SSI_SDATA1_A,
GPIO_FN_MOUT5,
GPIO_IFN_SSI_SDATA2_A,
@ -855,17 +886,13 @@ enum {
GPIO_FN_RIF0_D0_A,
GPIO_FN_RIF2_D1_A,
/* IPSR15 */
/* IPSR16 */
GPIO_IFN_SSI_SCK6,
GPIO_FN_USB2_PWEN,
GPIO_FN_SIM0_RST_D,
GPIO_FN_RDS_CLK_C,
GPIO_IFN_SSI_WS6,
GPIO_FN_USB2_OVC,
GPIO_FN_SIM0_D_D,
GPIO_IFN_SSI_SDATA6,
GPIO_FN_SIM0_CLK_D,
GPIO_FN_RSD_DATA_C,
GPIO_FN_SATA_DEVSLP_A,
GPIO_IFN_SSI_SCK78,
GPIO_FN_HRX2_B,
@ -877,7 +904,7 @@ enum {
GPIO_IFN_SSI_WS78,
GPIO_FN_HTX2_B,
GPIO_FN_MSIOF1_SYNC_C,
GPIO_FN_TS_SDT1_A,
GPIO_FN_TS_SDAT1_A,
GPIO_FN_STP_ISD_1_A,
GPIO_FN_RIF1_SYNC_A,
GPIO_FN_RIF3_SYNC_A,
@ -885,7 +912,7 @@ enum {
GPIO_FN_HCTS2x_B,
GPIO_FN_MSIOF1_RXD_C,
GPIO_FN_TS_SDEN1_A,
GPIO_FN_STP_IEN_1_A,
GPIO_FN_STP_ISEN_1_A,
GPIO_FN_RIF1_D0_A,
GPIO_FN_RIF3_D0_A,
GPIO_FN_TCLK2_A,
@ -895,7 +922,7 @@ enum {
GPIO_FN_TS_SPSYNC1_A,
GPIO_FN_STP_ISSYNC_1_A,
GPIO_FN_RIF1_D1_A,
GPIO_FN_EIF3_D1_A,
GPIO_FN_RIF3_D1_A,
GPIO_IFN_SSI_SDATA9_A,
GPIO_FN_HSCK2_B,
GPIO_FN_MSIOF1_SS1_C,
@ -903,31 +930,29 @@ enum {
GPIO_FN_SSI_WS1_B,
GPIO_FN_SCK1,
GPIO_FN_STP_IVCXO27_1_A,
GPIO_FN_SCK5,
GPIO_FN_SCK5_A,
/* IPSR16 */
/* IPSR17 */
GPIO_IFN_AUDIO_CLKA_A,
GPIO_FN_CC5_OSCOUT,
GPIO_IFN_AUDIO_CLKB_B,
GPIO_FN_SCIF_CLK_A,
GPIO_FN_DVC_MUTE,
GPIO_FN_STP_IVCXO27_1_D,
GPIO_FN_REMOCON_A,
GPIO_FN_TCLK1_A,
GPIO_FN_VSP_B,
GPIO_IFN_USB0_PWEN,
GPIO_FN_SIM0_RST_C,
GPIO_FN_TS_SCK1_D,
GPIO_FN_STP_ISCLK_1_D,
GPIO_FN_BPFCLK_B,
GPIO_FN_RIF3_CLK_B,
GPIO_FN_SCKZ_B,
GPIO_FN_HSCK2_C,
GPIO_IFN_USB0_OVC,
GPIO_FN_SIM0_D_C,
GPIO_FN_TS_SDAT1_D,
GPIO_FN_STP_ISD_1_D,
GPIO_FN_RIF3_SYNC_B,
GPIO_FN_VSP_C,
GPIO_FN_HRX2_C,
GPIO_IFN_USB1_PWEN,
GPIO_FN_SIM0_CLK_C,
GPIO_FN_SSI_SCK1_A,
@ -935,9 +960,8 @@ enum {
GPIO_FN_STP_ISCLK_0_E,
GPIO_FN_FMCLK_B,
GPIO_FN_RIF2_CLK_B,
GPIO_FN_MTSx_B,
GPIO_FN_SPEEDIN_A,
GPIO_FN_VSP_D,
GPIO_FN_HTX2_C,
GPIO_IFN_USB1_OVC,
GPIO_FN_MSIOF1_SS2_C,
GPIO_FN_SSI_WS1_A,
@ -945,8 +969,8 @@ enum {
GPIO_FN_STP_ISD_0_E,
GPIO_FN_FMIN_B,
GPIO_FN_RIF2_SYNC_B,
GPIO_FN_STMx_B,
GPIO_FN_REMOCON_B,
GPIO_FN_HCTS2x_C,
GPIO_IFN_USB30_PWEN,
GPIO_FN_AUDIO_CLKOUT_B,
GPIO_FN_SSI_SCK2_B,
@ -954,9 +978,10 @@ enum {
GPIO_FN_STP_ISEN_1_D,
GPIO_FN_STP_OPWM_0_E,
GPIO_FN_RIF3_D0_B,
GPIO_FN_MDATA_B,
GPIO_FN_TCLK2_B,
GPIO_FN_TPU0TO0,
GPIO_FN_BPFCLK_C,
GPIO_FN_HRTS2x_C,
GPIO_IFN_USB30_OVC,
GPIO_FN_AUDIO_CLKOUT1_B,
GPIO_FN_SSI_WS2_B,
@ -964,25 +989,28 @@ enum {
GPIO_FN_STP_ISSYNC_1_D,
GPIO_FN_STP_IVCXO27_0_E,
GPIO_FN_RIF3_D1_B,
GPIO_FN_SDATA_B,
GPIO_FN_RSO_TOE_B,
GPIO_FN_FSO_TOEx,
GPIO_FN_TPU0TO1,
/* IPSR17 */
GPIO_IFN_USB31_PWEN,
/* IPSR18 */
GPIO_IFN_USB3_PWEN,
GPIO_FN_AUDIO_CLKOUT2_B,
GPIO_FN_SI_SCK9_B,
GPIO_FN_SSI_SCK9_B,
GPIO_FN_TS_SDEN0_E,
GPIO_FN_STP_ISEN_0_E,
GPIO_FN_RIF2_D0_B,
GPIO_FN_TPU0TO2,
GPIO_IFN_USB31_OVC,
GPIO_FN_FMCLK_C,
GPIO_FN_FMCLK_D,
GPIO_IFN_USB3_OVC,
GPIO_FN_AUDIO_CLKOUT3_B,
GPIO_FN_SSI_WS9_B,
GPIO_FN_TS_SPSYNC0_E,
GPIO_FN_STP_ISSYNC_0_E,
GPIO_FN_RIF2_D1_B,
GPIO_FN_TPU0TO3,
GPIO_FN_FMIN_C,
GPIO_FN_FMIN_D,
};
#endif /* __ASM_R8A7795_GPIO_H__ */

1084
arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h Normal file
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File diff suppressed because it is too large Load diff

36
arch/arm/mach-rmobile/include/mach/r8a7796.h Normal file
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@ -0,0 +1,36 @@
/*
* arch/arm/include/asm/arch-rcar_gen3/r8a7796.h
* This file defines registers and value for r8a7796.
*
* Copyright (C) 2016 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_R8A7796_H
#define __ASM_ARCH_R8A7796_H
#include "rcar-gen3-base.h"
/* Module stop control/status register bits */
#define MSTP0_BITS 0x00200000
#define MSTP1_BITS 0xFFFFFFFF
#define MSTP2_BITS 0x340E2FDC
#define MSTP3_BITS 0xFFFFFFDF
#define MSTP4_BITS 0x80000184
#define MSTP5_BITS 0xC3FFFFFF
#define MSTP6_BITS 0xFFFFFFFF
#define MSTP7_BITS 0xFFFFFFFF
#define MSTP8_BITS 0x01F1FFF7
#define MSTP9_BITS 0xFFFFFFFE
#define MSTP10_BITS 0xFFFEFFE0
#define MSTP11_BITS 0x000000B7
/* SDHI */
#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */
#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */
#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
#endif /* __ASM_ARCH_R8A7796_H */

3
arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
View file

@ -79,6 +79,9 @@
#define PUEN_USB1_OVC (1 << 2)
#define PUEN_USB1_PWEN (1 << 1)
/* IICDVFS (I2C) */
#define CONFIG_SYS_I2C_SH_BASE0 0xE60B0000
#ifndef __ASSEMBLY__
#include <asm/types.h>

2
arch/arm/mach-rmobile/include/mach/rmobile.h
View file

@ -18,6 +18,8 @@
#include <asm/arch/r8a7794.h>
#elif defined(CONFIG_R8A7795)
#include <asm/arch/r8a7795.h>
#elif defined(CONFIG_R8A7796)
#include <asm/arch/r8a7796.h>
#else
#error "SOC Name not defined"
#endif

30
arch/arm/mach-rmobile/memmap-r8a7796.c Normal file
View file

@ -0,0 +1,30 @@
/*
* Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/armv8/mmu.h>
static struct mm_region r8a7796_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0xe0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xe0000000UL,
.phys = 0xe0000000UL,
.size = 0xe0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = r8a7796_mem_map;

1549
arch/arm/mach-rmobile/pfc-r8a7795.c
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File diff suppressed because it is too large Load diff

5253
arch/arm/mach-rmobile/pfc-r8a7796.c Normal file
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File diff suppressed because it is too large Load diff

3
board/renesas/salvator-x/MAINTAINERS
View file

@ -3,4 +3,5 @@ M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
S: Maintained
F: board/renesas/salvator-x/
F: include/configs/salvator-x.h
F: configs/salvator-x_defconfig
F: configs/r8a7795_salvator-x_defconfig
F: configs/r8a7796_salvator-x_defconfig

225
board/renesas/salvator-x/salvator-x.c
View file

@ -1,8 +1,8 @@
/*
* board/renesas/salvator-x/salvator-x.c
* This file is Salvator-X board support.
* This file is Salvator-X/Salvator-XS board support.
*
* Copyright (C) 2015 Renesas Electronics Corporation
* Copyright (C) 2015-2017 Renesas Electronics Corporation
* Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
@ -22,6 +22,7 @@
#include <asm/arch/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/sh_sdhi.h>
#include <i2c.h>
#include <mmc.h>
@ -44,10 +45,21 @@ void s_init(void)
writel(0xFFFFFFFF, CPGWPR);
}
#define GSX_MSTP112 (1 << 12) /* 3DG */
#define TMU0_MSTP125 (1 << 25) /* secure */
#define TMU1_MSTP124 (1 << 24) /* non-secure */
#define SCIF2_MSTP310 (1 << 10) /* SCIF2 */
#define GSX_MSTP112 BIT(12) /* 3DG */
#define TMU0_MSTP125 BIT(25) /* secure */
#define TMU1_MSTP124 BIT(24) /* non-secure */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define ETHERAVB_MSTP812 BIT(12)
#define DVFS_MSTP926 BIT(26)
#define SD0_MSTP314 BIT(14)
#define SD1_MSTP313 BIT(13)
#define SD2_MSTP312 BIT(12) /* either MMC0 */
#define SD3_MSTP311 BIT(11) /* either MMC1 */
#define SD0CKCR 0xE6150074
#define SD1CKCR 0xE6150078
#define SD2CKCR 0xE6150268
#define SD3CKCR 0xE615026C
int board_early_init_f(void)
{
@ -55,7 +67,22 @@ int board_early_init_f(void)
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
/* SCIF2 */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
/* EHTERAVB */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
/* eMMC */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
/* SDHI0, 3 */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);
writel(0, SD0CKCR);
writel(0, SD1CKCR);
writel(0, SD2CKCR);
writel(0, SD3CKCR);
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
#endif
return 0;
}
@ -65,32 +92,206 @@ int board_early_init_f(void)
/* -/W 32 Power resume control register 2 (3DG) */
#define SYSC_PWRONCR2 0xE618010C
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
/* Init PFC controller */
#if defined(CONFIG_R8A7795)
r8a7795_pinmux_init();
#elif defined(CONFIG_R8A7796)
r8a7796_pinmux_init();
#endif
#if defined(CONFIG_R8A7795)
/* GSX: force power and clock supply */
writel(0x0000001F, SYSC_PWRONCR2);
while (readl(SYSC_PWRSR2) != 0x000003E0)
mdelay(20);
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
#endif
/* USB1 pull-up */
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
#ifdef CONFIG_RAVB
/* EtherAVB Enable */
/* GPSR2 */
gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
gpio_request(GPIO_GFN_AVB_LINK, NULL);
gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
gpio_request(GPIO_GFN_AVB_MDC, NULL);
/* IPSR0 */
gpio_request(GPIO_IFN_AVB_MDC, NULL);
gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
gpio_request(GPIO_IFN_AVB_LINK, NULL);
gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
/* IPSR1 */
gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
/* IPSR2 */
gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
/* IPSR3 */
gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
#if defined(CONFIG_R8A7795)
/* USB2_OVC */
gpio_request(GPIO_GP_6_15, NULL);
gpio_direction_input(GPIO_GP_6_15);
/* USB2_PWEN */
gpio_request(GPIO_GP_6_14, NULL);
gpio_direction_output(GPIO_GP_6_14, 1);
gpio_set_value(GPIO_GP_6_14, 1);
#endif
/* AVB_PHY_RST */
gpio_request(GPIO_GP_2_10, NULL);
gpio_direction_output(GPIO_GP_2_10, 0);
mdelay(20);
gpio_set_value(GPIO_GP_2_10, 1);
udelay(1);
#endif
return 0;
}
static struct eth_pdata salvator_x_ravb_platdata = {
.iobase = 0xE6800000,
.phy_interface = 0,
.max_speed = 1000,
};
U_BOOT_DEVICE(salvator_x_ravb) = {
.name = "ravb",
.platdata = &salvator_x_ravb_platdata,
};
#ifdef CONFIG_SH_SDHI
int board_mmc_init(bd_t *bis)
{
int ret = -ENODEV;
/* SDHI0 */
gpio_request(GPIO_GFN_SD0_DAT0, NULL);
gpio_request(GPIO_GFN_SD0_DAT1, NULL);
gpio_request(GPIO_GFN_SD0_DAT2, NULL);
gpio_request(GPIO_GFN_SD0_DAT3, NULL);
gpio_request(GPIO_GFN_SD0_CLK, NULL);
gpio_request(GPIO_GFN_SD0_CMD, NULL);
gpio_request(GPIO_GFN_SD0_CD, NULL);
gpio_request(GPIO_GFN_SD0_WP, NULL);
gpio_request(GPIO_GP_5_2, NULL);
gpio_request(GPIO_GP_5_1, NULL);
gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
SH_SDHI_QUIRK_64BIT_BUF);
if (ret)
return ret;
/* SDHI1/SDHI2 eMMC */
gpio_request(GPIO_GFN_SD1_DAT0, NULL);
gpio_request(GPIO_GFN_SD1_DAT1, NULL);
gpio_request(GPIO_GFN_SD1_DAT2, NULL);
gpio_request(GPIO_GFN_SD1_DAT3, NULL);
gpio_request(GPIO_GFN_SD2_DAT0, NULL);
gpio_request(GPIO_GFN_SD2_DAT1, NULL);
gpio_request(GPIO_GFN_SD2_DAT2, NULL);
gpio_request(GPIO_GFN_SD2_DAT3, NULL);
gpio_request(GPIO_GFN_SD2_CLK, NULL);
#if defined(CONFIG_R8A7795)
gpio_request(GPIO_GFN_SD2_CMD, NULL);
#elif defined(CONFIG_R8A7796)
gpio_request(GPIO_FN_SD2_CMD, NULL);
#else
#error Only R8A7795 and R87796 is supported
#endif
gpio_request(GPIO_GP_5_3, NULL);
gpio_request(GPIO_GP_5_9, NULL);
gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1,
SH_SDHI_QUIRK_64BIT_BUF);
if (ret)
return ret;
#if defined(CONFIG_R8A7795)
/* SDHI3 */
gpio_request(GPIO_GFN_SD3_DAT0, NULL); /* GP_4_9 */
gpio_request(GPIO_GFN_SD3_DAT1, NULL); /* GP_4_10 */
gpio_request(GPIO_GFN_SD3_DAT2, NULL); /* GP_4_11 */
gpio_request(GPIO_GFN_SD3_DAT3, NULL); /* GP_4_12 */
gpio_request(GPIO_GFN_SD3_CLK, NULL); /* GP_4_7 */
gpio_request(GPIO_GFN_SD3_CMD, NULL); /* GP_4_8 */
#elif defined(CONFIG_R8A7796)
gpio_request(GPIO_FN_SD3_DAT0, NULL); /* GP_4_9 */
gpio_request(GPIO_FN_SD3_DAT1, NULL); /* GP_4_10 */
gpio_request(GPIO_FN_SD3_DAT2, NULL); /* GP_4_11 */
gpio_request(GPIO_FN_SD3_DAT3, NULL); /* GP_4_12 */
gpio_request(GPIO_FN_SD3_CLK, NULL); /* GP_4_7 */
gpio_request(GPIO_FN_SD3_CMD, NULL); /* GP_4_8 */
#else
#error Only R8A7795 and R87796 is supported
#endif
/* IPSR10 */
gpio_request(GPIO_FN_SD3_CD, NULL);
gpio_request(GPIO_FN_SD3_WP, NULL);
gpio_request(GPIO_GP_3_15, NULL);
gpio_request(GPIO_GP_3_14, NULL);
gpio_direction_output(GPIO_GP_3_15, 1); /* power on */
gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI3_BASE, 2,
SH_SDHI_QUIRK_64BIT_BUF);
return ret;
}
#endif
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
gd->ram_size = PHYS_SDRAM_1_SIZE;
#if (CONFIG_NR_DRAM_BANKS >= 2)
gd->ram_size += PHYS_SDRAM_2_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
gd->ram_size += PHYS_SDRAM_3_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 4)
gd->ram_size += PHYS_SDRAM_4_SIZE;
#endif
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#if (CONFIG_NR_DRAM_BANKS >= 2)
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 4)
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
#endif
return 0;
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_RCAR_BOARD_STRING
};
@ -103,15 +304,19 @@ const struct rmobile_sysinfo sysinfo = {
void reset_cpu(ulong addr)
{
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
#else
/* only CA57 ? */
writel(RST_CODE, RST_CA57RESCNT);
#endif
}
static const struct sh_serial_platdata serial_platdata = {
.base = SCIF2_BASE,
.type = PORT_SCIF,
.clk = 14745600, /* 0xE10000 */
.clk_mode = EXT_CLK,
.clk = CONFIG_SH_SCIF_CLK_FREQ,
.clk_mode = INT_CLK,
};
U_BOOT_DEVICE(salvator_x_scif2) = {

31
configs/r8a7795_salvator-x_defconfig Normal file
View file

@ -0,0 +1,31 @@
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
CONFIG_DEFAULT_FDT_FILE=r8a7795-salvator-x.dtb
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_FDT=y
CONFIG_R8A7795=y
CONFIG_SH_SDHI=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_EDITENV=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_NET=y
CONFIG_CMD_NFS=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_EHCI_RCAR_GEN3=y
CONFIG_DOS_PARTITION=y
CONFIG_MMC=y
CONFIG_GENERIC_MMC=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y

31
configs/r8a7796_salvator-x_defconfig Normal file
View file

@ -0,0 +1,31 @@
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
CONFIG_DEFAULT_FDT_FILE=r8a7796-salvator-x.dtb
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_FDT=y
CONFIG_R8A7796=y
CONFIG_SH_SDHI=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_EDITENV=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_NET=y
CONFIG_CMD_NFS=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_EHCI_RCAR_GEN3=y
CONFIG_DOS_PARTITION=y
CONFIG_MMC=y
CONFIG_GENERIC_MMC=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y

12
configs/salvator-x_defconfig
View file

@ -1,12 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
CONFIG_DOS_PARTITION=y
# CONFIG_MMC is not set

17
drivers/gpio/sh_pfc.c
View file

@ -66,17 +66,18 @@ static void gpio_write_raw_reg(void *mapped_reg,
}
static int gpio_read_bit(struct pinmux_data_reg *dr,
unsigned long offset,
unsigned long in_pos)
{
unsigned long pos;
pos = dr->reg_width - (in_pos + 1);
debug("read_bit: addr = %lx, pos = %ld, "
"r_width = %ld\n", dr->reg, pos, dr->reg_width);
debug("read_bit: addr = %lx, pos = %ld, r_width = %ld\n",
dr->reg + offset, pos, dr->reg_width);
return
(gpio_read_raw_reg(dr->mapped_reg + 0x4, dr->reg_width) >> pos) & 1;
return (gpio_read_raw_reg(dr->mapped_reg + offset,
dr->reg_width) >> pos) & 1;
}
static void gpio_write_bit(struct pinmux_data_reg *dr,
@ -559,12 +560,16 @@ static int sh_gpio_direction_output(unsigned offset, int value)
static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
{
struct pinmux_data_reg *dr = NULL;
int bit = 0;
int bit = 0, offset = 0;
if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
return -1;
#if defined(CONFIG_RCAR_GEN3)
if ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_INPUT)
offset += 4;
#endif
return gpio_read_bit(dr, bit);
return gpio_read_bit(dr, offset, bit);
}
static int sh_gpio_get(unsigned offset)

8
drivers/net/Kconfig
View file

@ -225,4 +225,12 @@ config GMAC_ROCKCHIP
This driver provides Rockchip SoCs network support based on the
Synopsys Designware driver.
config RENESAS_RAVB
bool "Renesas Ethernet AVB MAC"
depends on DM_ETH && RCAR_GEN3
select PHYLIB
help
This driver implements support for the Ethernet AVB block in
Renesas M3 and H3 SoCs.
endif # NETDEVICES

1
drivers/net/Makefile
View file

@ -56,6 +56,7 @@ obj-$(CONFIG_RTL8169) += rtl8169.o
obj-$(CONFIG_ETH_SANDBOX) += sandbox.o
obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o
obj-$(CONFIG_SH_ETHER) += sh_eth.o
obj-$(CONFIG_RENESAS_RAVB) += ravb.o
obj-$(CONFIG_SMC91111) += smc91111.o
obj-$(CONFIG_SMC911X) += smc911x.o
obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o

601
drivers/net/ravb.c Normal file
View file

@ -0,0 +1,601 @@
/*
* drivers/net/ravb.c
* This file is driver for Renesas Ethernet AVB.
*
* Copyright (C) 2015-2017 Renesas Electronics Corporation
*
* Based on the SuperH Ethernet driver.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <miiphy.h>
#include <malloc.h>
#include <linux/mii.h>
#include <wait_bit.h>
#include <asm/io.h>
/* Registers */
#define RAVB_REG_CCC 0x000
#define RAVB_REG_DBAT 0x004
#define RAVB_REG_CSR 0x00C
#define RAVB_REG_APSR 0x08C
#define RAVB_REG_RCR 0x090
#define RAVB_REG_TGC 0x300
#define RAVB_REG_TCCR 0x304
#define RAVB_REG_RIC0 0x360
#define RAVB_REG_RIC1 0x368
#define RAVB_REG_RIC2 0x370
#define RAVB_REG_TIC 0x378
#define RAVB_REG_ECMR 0x500
#define RAVB_REG_RFLR 0x508
#define RAVB_REG_ECSIPR 0x518
#define RAVB_REG_PIR 0x520
#define RAVB_REG_GECMR 0x5b0
#define RAVB_REG_MAHR 0x5c0
#define RAVB_REG_MALR 0x5c8
#define CCC_OPC_CONFIG BIT(0)
#define CCC_OPC_OPERATION BIT(1)
#define CCC_BOC BIT(20)
#define CSR_OPS 0x0000000F
#define CSR_OPS_CONFIG BIT(1)
#define TCCR_TSRQ0 BIT(0)
#define RFLR_RFL_MIN 0x05EE
#define PIR_MDI BIT(3)
#define PIR_MDO BIT(2)
#define PIR_MMD BIT(1)
#define PIR_MDC BIT(0)
#define ECMR_TRCCM BIT(26)
#define ECMR_RZPF BIT(20)
#define ECMR_PFR BIT(18)
#define ECMR_RXF BIT(17)
#define ECMR_RE BIT(6)
#define ECMR_TE BIT(5)
#define ECMR_DM BIT(1)
#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)
/* DMA Descriptors */
#define RAVB_NUM_BASE_DESC 16
#define RAVB_NUM_TX_DESC 8
#define RAVB_NUM_RX_DESC 8
#define RAVB_TX_QUEUE_OFFSET 0
#define RAVB_RX_QUEUE_OFFSET 4
#define RAVB_DESC_DT(n) ((n) << 28)
#define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7)
#define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9)
#define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa)
#define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc)
#define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3)
#define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf)
#define RAVB_DESC_DS(n) (((n) & 0xfff) << 0)
#define RAVB_DESC_DS_MASK 0xfff
#define RAVB_RX_DESC_MSC_MC BIT(23)
#define RAVB_RX_DESC_MSC_CEEF BIT(22)
#define RAVB_RX_DESC_MSC_CRL BIT(21)
#define RAVB_RX_DESC_MSC_FRE BIT(20)
#define RAVB_RX_DESC_MSC_RTLF BIT(19)
#define RAVB_RX_DESC_MSC_RTSF BIT(18)
#define RAVB_RX_DESC_MSC_RFE BIT(17)
#define RAVB_RX_DESC_MSC_CRC BIT(16)
#define RAVB_RX_DESC_MSC_MASK (0xff << 16)
#define RAVB_RX_DESC_MSC_RX_ERR_MASK \
(RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \
RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF)
#define RAVB_TX_TIMEOUT_MS 1000
struct ravb_desc {
u32 ctrl;
u32 dptr;
};
struct ravb_rxdesc {
struct ravb_desc data;
struct ravb_desc link;
u8 __pad[48];
u8 packet[PKTSIZE_ALIGN];
};
struct ravb_priv {
struct ravb_desc base_desc[RAVB_NUM_BASE_DESC];
struct ravb_desc tx_desc[RAVB_NUM_TX_DESC];
struct ravb_rxdesc rx_desc[RAVB_NUM_RX_DESC];
u32 rx_desc_idx;
u32 tx_desc_idx;
struct phy_device *phydev;
struct mii_dev *bus;
void __iomem *iobase;
};
static inline void ravb_flush_dcache(u32 addr, u32 len)
{
flush_dcache_range(addr, addr + len);
}
static inline void ravb_invalidate_dcache(u32 addr, u32 len)
{
u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
invalidate_dcache_range(start, end);
}
static int ravb_send(struct udevice *dev, void *packet, int len)
{
struct ravb_priv *eth = dev_get_priv(dev);
struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx];
unsigned int start;
/* Update TX descriptor */
ravb_flush_dcache((uintptr_t)packet, len);
memset(desc, 0x0, sizeof(*desc));
desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len);
desc->dptr = (uintptr_t)packet;
ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
/* Restart the transmitter if disabled */
if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);
/* Wait until packet is transmitted */
start = get_timer(0);
while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
break;
udelay(10);
};
if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
return -ETIMEDOUT;
eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
return 0;
}
static int ravb_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct ravb_priv *eth = dev_get_priv(dev);
struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
int len;
u8 *packet;
/* Check if the rx descriptor is ready */
ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
return -EAGAIN;
/* Check for errors */
if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
return -EAGAIN;
}
len = desc->data.ctrl & RAVB_DESC_DS_MASK;
packet = (u8 *)(uintptr_t)desc->data.dptr;
ravb_invalidate_dcache((uintptr_t)packet, len);
*packetp = packet;
return len;
}
static int ravb_free_pkt(struct udevice *dev, uchar *packet, int length)
{
struct ravb_priv *eth = dev_get_priv(dev);
struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
/* Make current descriptor available again */
desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN);
ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
/* Point to the next descriptor */
eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
desc = &eth->rx_desc[eth->rx_desc_idx];
ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
return 0;
}
static int ravb_reset(struct udevice *dev)
{
struct ravb_priv *eth = dev_get_priv(dev);
/* Set config mode */
writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
/* Check the operating mode is changed to the config mode. */
return wait_for_bit(dev->name, (void *)eth->iobase + RAVB_REG_CSR,
CSR_OPS_CONFIG, true, 100, true);
}
static void ravb_base_desc_init(struct ravb_priv *eth)
{
const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
int i;
/* Initialize all descriptors */
memset(eth->base_desc, 0x0, desc_size);
for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;
ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);
/* Register the descriptor base address table */
writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
}
static void ravb_tx_desc_init(struct ravb_priv *eth)
{
const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
int i;
/* Initialize all descriptors */
memset(eth->tx_desc, 0x0, desc_size);
eth->tx_desc_idx = 0;
for (i = 0; i < RAVB_NUM_TX_DESC; i++)
eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;
/* Mark the end of the descriptors */
eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);
/* Point the controller to the TX descriptor list. */
eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_TX_QUEUE_OFFSET],
sizeof(struct ravb_desc));
}
static void ravb_rx_desc_init(struct ravb_priv *eth)
{
const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
int i;
/* Initialize all descriptors */
memset(eth->rx_desc, 0x0, desc_size);
eth->rx_desc_idx = 0;
for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY |
RAVB_DESC_DS(PKTSIZE_ALIGN);
eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;
eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
eth->rx_desc[i].link.dptr = (uintptr_t)&eth->rx_desc[i + 1];
}
/* Mark the end of the descriptors */
eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);
/* Point the controller to the rx descriptor list */
eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_RX_QUEUE_OFFSET],
sizeof(struct ravb_desc));
}
static int ravb_phy_config(struct udevice *dev)
{
struct ravb_priv *eth = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
struct phy_device *phydev;
int reg;
phydev = phy_connect(eth->bus, pdata->phy_interface,
dev, PHY_INTERFACE_MODE_RGMII_ID);
if (!phydev)
return -ENODEV;
eth->phydev = phydev;
/* 10BASE is not supported for Ethernet AVB MAC */
phydev->supported &= ~(SUPPORTED_10baseT_Full
| SUPPORTED_10baseT_Half);
if (pdata->max_speed != 1000) {
phydev->supported &= ~(SUPPORTED_1000baseT_Half
| SUPPORTED_1000baseT_Full);
reg = phy_read(phydev, -1, MII_CTRL1000);
reg &= ~(BIT(9) | BIT(8));
phy_write(phydev, -1, MII_CTRL1000, reg);
}
phy_config(phydev);
return 0;
}
/* Set Mac address */
static int ravb_write_hwaddr(struct udevice *dev)
{
struct ravb_priv *eth = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
unsigned char *mac = pdata->enetaddr;
writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
eth->iobase + RAVB_REG_MAHR);
writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);
return 0;
}
/* E-MAC init function */
static int ravb_mac_init(struct ravb_priv *eth)
{
/* Disable MAC Interrupt */
writel(0, eth->iobase + RAVB_REG_ECSIPR);
/* Recv frame limit set register */
writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);
return 0;
}
/* AVB-DMAC init function */
static int ravb_dmac_init(struct udevice *dev)
{
struct ravb_priv *eth = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
int ret = 0;
/* Set CONFIG mode */
ret = ravb_reset(dev);
if (ret)
return ret;
/* Disable all interrupts */
writel(0, eth->iobase + RAVB_REG_RIC0);
writel(0, eth->iobase + RAVB_REG_RIC1);
writel(0, eth->iobase + RAVB_REG_RIC2);
writel(0, eth->iobase + RAVB_REG_TIC);
/* Set little endian */
clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);
/* AVB rx set */
writel(0x18000001, eth->iobase + RAVB_REG_RCR);
/* FIFO size set */
writel(0x00222210, eth->iobase + RAVB_REG_TGC);
/* Delay CLK: 2ns */
if (pdata->max_speed == 1000)
writel(BIT(14), eth->iobase + RAVB_REG_APSR);
return 0;
}
static int ravb_config(struct udevice *dev)
{
struct ravb_priv *eth = dev_get_priv(dev);
struct phy_device *phy;
u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
int ret;
/* Configure AVB-DMAC register */
ravb_dmac_init(dev);
/* Configure E-MAC registers */
ravb_mac_init(eth);
ravb_write_hwaddr(dev);
/* Configure phy */
ret = ravb_phy_config(dev);
if (ret)
return ret;
phy = eth->phydev;
ret = phy_startup(phy);
if (ret)
return ret;
/* Set the transfer speed */
if (phy->speed == 100)
writel(0, eth->iobase + RAVB_REG_GECMR);
else if (phy->speed == 1000)
writel(1, eth->iobase + RAVB_REG_GECMR);
/* Check if full duplex mode is supported by the phy */
if (phy->duplex)
mask |= ECMR_DM;
writel(mask, eth->iobase + RAVB_REG_ECMR);
phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19);
return 0;
}
int ravb_start(struct udevice *dev)
{
struct ravb_priv *eth = dev_get_priv(dev);
int ret;
ret = ravb_reset(dev);
if (ret)
return ret;
ravb_base_desc_init(eth);
ravb_tx_desc_init(eth);
ravb_rx_desc_init(eth);
ret = ravb_config(dev);
if (ret)
return ret;
/* Setting the control will start the AVB-DMAC process. */
writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
return 0;
}
static void ravb_stop(struct udevice *dev)
{
ravb_reset(dev);
}
static int ravb_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct ravb_priv *eth = dev_get_priv(dev);
struct mii_dev *mdiodev;
void __iomem *iobase;
int ret;
iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
eth->iobase = iobase;
mdiodev = mdio_alloc();
if (!mdiodev) {
ret = -ENOMEM;
goto err_mdio_alloc;
}
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
bb_miiphy_buses[0].priv = eth;
snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
ret = mdio_register(mdiodev);
if (ret < 0)
goto err_mdio_register;
eth->bus = miiphy_get_dev_by_name(dev->name);
return 0;
err_mdio_register:
mdio_free(mdiodev);
err_mdio_alloc:
unmap_physmem(eth->iobase, MAP_NOCACHE);
return ret;
}
static int ravb_remove(struct udevice *dev)
{
struct ravb_priv *eth = dev_get_priv(dev);
free(eth->phydev);
mdio_unregister(eth->bus);
mdio_free(eth->bus);
unmap_physmem(eth->iobase, MAP_NOCACHE);
return 0;
}
int ravb_bb_init(struct bb_miiphy_bus *bus)
{
return 0;
}
int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
{
struct ravb_priv *eth = bus->priv;
setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
return 0;
}
int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
struct ravb_priv *eth = bus->priv;
clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
return 0;
}
int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
struct ravb_priv *eth = bus->priv;
if (v)
setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
else
clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
return 0;
}
int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
struct ravb_priv *eth = bus->priv;
*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
return 0;
}
int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
struct ravb_priv *eth = bus->priv;
if (v)
setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
else
clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
return 0;
}
int ravb_bb_delay(struct bb_miiphy_bus *bus)
{
udelay(10);
return 0;
}
struct bb_miiphy_bus bb_miiphy_buses[] = {
{
.name = "ravb",
.init = ravb_bb_init,
.mdio_active = ravb_bb_mdio_active,
.mdio_tristate = ravb_bb_mdio_tristate,
.set_mdio = ravb_bb_set_mdio,
.get_mdio = ravb_bb_get_mdio,
.set_mdc = ravb_bb_set_mdc,
.delay = ravb_bb_delay,
},
};
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
static const struct eth_ops ravb_ops = {
.start = ravb_start,
.send = ravb_send,
.recv = ravb_recv,
.free_pkt = ravb_free_pkt,
.stop = ravb_stop,
.write_hwaddr = ravb_write_hwaddr,
};
U_BOOT_DRIVER(eth_ravb) = {
.name = "ravb",
.id = UCLASS_ETH,
.probe = ravb_probe,
.remove = ravb_remove,
.ops = &ravb_ops,
.priv_auto_alloc_size = sizeof(struct ravb_priv),
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};

3
drivers/serial/serial_sh.h
View file

@ -226,7 +226,8 @@ struct uart_port {
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7792) || defined(CONFIG_R8A7793) || \
defined(CONFIG_R8A7794) || defined(CONFIG_R8A7795)
defined(CONFIG_R8A7794) || defined(CONFIG_R8A7795) || \
defined(CONFIG_R8A7796)
# if defined(CONFIG_SCIF_A)
# define SCIF_ORER 0x0200
# else

37
include/configs/rcar-gen3-common.h
View file

@ -2,7 +2,7 @@
* include/configs/rcar-gen3-common.h
* This file is R-Car Gen3 common configuration file.
*
* Copyright (C) 2015 Renesas Electronics Corporation
* Copyright (C) 2015-2017 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -17,7 +17,6 @@
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FDT
#define CONFIG_REMAKE_ELF
@ -34,7 +33,6 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_EDITING
#define CONFIG_OF_LIBFDT
#undef CONFIG_SHOW_BOOT_PROGRESS
@ -52,13 +50,34 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 }
/* MEMORY */
#define CONFIG_SYS_TEXT_BASE 0x49000000
#define CONFIG_SYS_TEXT_BASE 0x50000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7fff0)
#define CONFIG_SYS_SDRAM_BASE (0x48000000)
#define CONFIG_SYS_SDRAM_SIZE (1024u * 1024 * 1024 - 0x08000000)
#define CONFIG_SYS_LOAD_ADDR (0x48080000)
#define CONFIG_NR_DRAM_BANKS 1
#define DRAM_RSV_SIZE 0x08000000
#if defined(CONFIG_R8A7795)
#define CONFIG_NR_DRAM_BANKS 4
#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE)
#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE)
#define PHYS_SDRAM_2 0x500000000
#define PHYS_SDRAM_2_SIZE 0x40000000u
#define PHYS_SDRAM_3 0x600000000
#define PHYS_SDRAM_3_SIZE 0x40000000u
#define PHYS_SDRAM_4 0x700000000
#define PHYS_SDRAM_4_SIZE 0x40000000u
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
#elif defined(CONFIG_R8A7796)
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE)
#define PHYS_SDRAM_1_SIZE (0x80000000u - DRAM_RSV_SIZE)
#define PHYS_SDRAM_2 0x0600000000
#define PHYS_SDRAM_2_SIZE 0x80000000u
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
#endif
#define CONFIG_SYS_LOAD_ADDR 0x48080000
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_SDRAM_SIZE
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
@ -81,7 +100,7 @@
#define CONFIG_BOOTCOMMAND \
"tftp 0x48080000 Image; " \
"tftp 0x48000000 Image-r8a7795-salvator-x.dtb; " \
"tftp 0x48000000 Image-"CONFIG_DEFAULT_FDT_FILE"; " \
"booti 0x48080000 - 0x48000000"
#endif /* __RCAR_GEN3_COMMON_H */

42
include/configs/salvator-x.h
View file

@ -20,21 +20,27 @@
#define CONFIG_SCIF_CONSOLE
#define CONFIG_CONS_SCIF2
#define CONFIG_CONS_INDEX 2
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
/* [A] Hyper Flash */
/* use to RPC(SPI Multi I/O Bus Controller) */
#define CONFIG_ENV_IS_NOWHERE
/* Ethernet RAVB */
#define CONFIG_NET_MULTI
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define RCAR_XTAL_CLK 33333333u
#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK
/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
/* CPclk 16.66MHz, S3D2 133.33MHz */
/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */
#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2)
#define CONFIG_S3D2_CLK_FREQ (266666666u/2)
#define CONFIG_S3D4_CLK_FREQ (266666666u/4)
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
@ -44,9 +50,39 @@
#define GICD_BASE 0xF1010000
#define GICC_BASE 0xF1020000
/* i2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SH
#define CONFIG_SYS_I2C_SLAVE 0x60
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1
#define CONFIG_SYS_I2C_SH_SPEED0 400000
#define CONFIG_SH_I2C_DATA_HIGH 4
#define CONFIG_SH_I2C_DATA_LOW 5
#define CONFIG_SH_I2C_CLOCK 10000000
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30
/* USB */
#ifdef CONFIG_R8A7795
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#else
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
/* SDHI */
#define CONFIG_SH_SDHI_FREQ 200000000
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
/* Module stop status bits */
/* MFIS, SCIF1 */
#define CONFIG_SMSTP2_ENA 0x00002040
/* SCIF2 */
#define CONFIG_SMSTP3_ENA 0x00000400
/* INTC-AP, IRQC */
#define CONFIG_SMSTP4_ENA 0x00000180

1
scripts/config_whitelist.txt
View file

@ -2310,6 +2310,7 @@ CONFIG_S3C24XX_TACLS
CONFIG_S3C24XX_TWRPH0
CONFIG_S3C24XX_TWRPH1
CONFIG_S3D2_CLK_FREQ
CONFIG_S3D4_CLK_FREQ
CONFIG_S5P
CONFIG_S5PC100
CONFIG_S5PC110