mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
Migrate esd 405EP boards to new NAND subsystem
Migrate esd 405EP boards to new NAND subsystem -cleanup -use correct io accessors (in/out_be32()) Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This commit is contained in:
Matthias Fuchs
Stefan Roese
parent
e09f7ab574
commit
bd84ee4c20
21 changed files with 114 additions and 450 deletions
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@ -28,7 +28,9 @@ endif
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o flash.o ../common/misc.o
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COBJS = $(BOARD).o flash.o \
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../common/misc.o \
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../common/esd405ep_nand.o \
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -23,6 +23,7 @@
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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@ -33,6 +34,7 @@
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#endif
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extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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extern void lxt971_no_sleep(void);
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/* fpga configuration data - gzip compressed and generated by bin2c */
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const unsigned char fpgadata[] =
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@ -164,17 +166,11 @@ int misc_init_r (void)
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/*
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* Reset external DUARTs
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
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udelay(10); /* wait 10us */
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
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udelay(1000); /* wait 1ms */
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/*
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* Set NAND-FLASH GPIO signals to default
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
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/*
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* Enable interrupts in exar duart mcr[3]
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*/
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@ -218,35 +214,18 @@ long int initdram (int board_type)
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mtdcr(memcfga, mem_mb0cf);
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val = mfdcr(memcfgd);
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#if 0
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printf("\nmb0cf=%x\n", val); /* test-only */
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printf("strap=%x\n", mfdcr(strap)); /* test-only */
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#endif
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return (4*1024*1024 << ((val & 0x000e0000) >> 17));
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}
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/* ------------------------------------------------------------------------- */
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int testdram (void)
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void reset_phy(void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: 16 MB - ok\n");
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#ifdef CONFIG_LXT971_NO_SLEEP
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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#include <linux/mtd/nand_legacy.h>
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extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
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void nand_init(void)
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{
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nand_probe(CFG_NAND_BASE);
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if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
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print_size(nand_dev_desc[0].totlen, "\n");
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}
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}
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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#endif
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}
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@ -33,7 +33,10 @@ CPLD = ../common/xilinx_jtag/lenval.o \
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../common/xilinx_jtag/micro.o \
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../common/xilinx_jtag/ports.o
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COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD)
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COBJS = $(BOARD).o flash.o \
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../common/misc.o \
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$(CPLD) \
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../common/esd405ep_nand.o \
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2005
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* (C) Copyright 2005-2007
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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@ -23,6 +23,7 @@
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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@ -68,9 +69,9 @@ int board_early_init_f (void)
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/*
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* Reset CPLD via GPIO12 (CS3) pin
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET);
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udelay(1000); /* wait 1ms */
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET);
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udelay(1000); /* wait 1ms */
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return 0;
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@ -94,13 +95,7 @@ int misc_init_r (void)
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/*
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* Setup and enable EEPROM write protection
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
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/*
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* Set NAND-FLASH GPIO signals to default
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
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return (0);
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}
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@ -153,11 +148,6 @@ long int initdram (int board_type)
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mtdcr(memcfga, mem_mb0cf);
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val = mfdcr(memcfgd);
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#if 0
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printf("\nmb0cf=%x\n", val); /* test-only */
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printf("strap=%x\n", mfdcr(strap)); /* test-only */
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#endif
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return (4*1024*1024 << ((val & 0x000e0000) >> 17));
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}
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@ -180,17 +170,17 @@ int eeprom_write_enable (unsigned dev_addr, int state)
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switch (state) {
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case 1:
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/* Enable write access, clear bit GPIO_SINT2. */
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP);
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state = 0;
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break;
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case 0:
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/* Disable write access, set bit GPIO_SINT2. */
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
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state = 0;
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break;
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default:
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/* Read current status back. */
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state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
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state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP));
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break;
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}
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}
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@ -235,19 +225,6 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
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/* ------------------------------------------------------------------------- */
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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#include <linux/mtd/nand_legacy.h>
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extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
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void nand_init(void)
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{
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nand_probe(CFG_NAND_BASE);
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if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
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print_size(nand_dev_desc[0].totlen, "\n");
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}
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}
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#endif
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void reset_phy(void)
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{
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#ifdef CONFIG_LXT971_NO_SLEEP
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@ -28,7 +28,10 @@ endif
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
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COBJS = $(BOARD).o flash.o \
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../common/misc.o \
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../common/esd405ep_nand.o \
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../common/auto_update.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -5,7 +5,7 @@
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2006
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* (C) Copyright 2006-2007
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* Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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@ -476,12 +476,6 @@ int misc_init_r (void)
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
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/*
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* Set NAND-FLASH GPIO signals to default
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
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/*
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* Reset touch-screen controller
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*/
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@ -690,20 +684,6 @@ void ide_set_reset(int on)
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#endif /* CONFIG_IDE_RESET */
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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#include <linux/mtd/nand_legacy.h>
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extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
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void nand_init(void)
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{
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nand_probe(CFG_NAND_BASE);
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if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
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print_size(nand_dev_desc[0].totlen, "\n");
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}
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}
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#endif
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#if defined(CFG_EEPROM_WREN)
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/* Input: <dev_addr> I2C address of EEPROM device to enable.
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* <state> -1: deliver current state
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@ -28,7 +28,9 @@ endif
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o flash.o ../common/misc.o
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COBJS = $(BOARD).o flash.o \
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../common/misc.o \
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../common/esd405ep_nand.o \
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -152,12 +152,6 @@ int misc_init_r (void)
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out32(GPIO0_OR, val);
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/*
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* Set NAND-FLASH GPIO signals to default
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
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/*
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* check board type and setup AP power
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*/
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@ -242,33 +236,5 @@ long int initdram (int board_type)
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mtdcr(memcfga, mem_mb0cf);
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val = mfdcr(memcfgd);
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#if 0
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printf("\nmb0cf=%x\n", val); /* test-only */
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printf("strap=%x\n", mfdcr(strap)); /* test-only */
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#endif
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return (4*1024*1024 << ((val & 0x000e0000) >> 17));
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}
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: 16 MB - ok\n");
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return (0);
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}
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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#include <linux/mtd/nand_legacy.h>
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extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
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void nand_init(void)
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{
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nand_probe(CFG_NAND_BASE);
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if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
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print_size(nand_dev_desc[0].totlen, "\n");
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}
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}
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#endif
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@ -28,7 +28,10 @@ endif
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
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COBJS = $(BOARD).o flash.o \
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../common/misc.o \
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../common/esd405ep_nand.o \
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../common/auto_update.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -23,6 +23,7 @@
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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@ -31,6 +32,8 @@
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#define FPGA_DEBUG
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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extern void lxt971_no_sleep(void);
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@ -114,6 +117,10 @@ int misc_init_r (void)
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int index;
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int i;
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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dst = malloc(CFG_FPGA_MAX_SIZE);
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if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
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printf ("GUNZIP ERROR - must RESET board to recover\n");
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@ -177,17 +184,11 @@ int misc_init_r (void)
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/*
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* Reset external DUARTs
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
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udelay(10); /* wait 10us */
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
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udelay(1000); /* wait 1ms */
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/*
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* Set NAND-FLASH GPIO signals to default
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
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/*
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* Enable interrupts in exar duart mcr[3]
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*/
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@ -226,24 +227,10 @@ long int initdram (int board_type)
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mtdcr(memcfga, mem_mb0cf);
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val = mfdcr(memcfgd);
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#if 0
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printf("\nmb0cf=%x\n", val); /* test-only */
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printf("strap=%x\n", mfdcr(strap)); /* test-only */
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#endif
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return (4*1024*1024 << ((val & 0x000e0000) >> 17));
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}
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: 16 MB - ok\n");
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return (0);
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}
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#ifdef CONFIG_IDE_RESET
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void ide_set_reset(int on)
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{
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@ -262,31 +249,6 @@ void ide_set_reset(int on)
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#endif /* CONFIG_IDE_RESET */
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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#include <linux/mtd/nand_legacy.h>
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extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
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void nand_init(void)
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{
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nand_probe(CFG_NAND_BASE);
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if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
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print_size(nand_dev_desc[0].totlen, "\n");
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}
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}
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#endif
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#ifdef CONFIG_AUTO_UPDATE_SHOW
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void board_auto_update_show(int au_active)
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{
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if (au_active) {
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printf("\n Dies ist die board-funktion: Updating!!!\n");
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} else {
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printf("\n Dies ist die board-funktion: Updating done!!!\n");
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}
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}
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#endif
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void reset_phy(void)
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{
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#ifdef CONFIG_LXT971_NO_SLEEP
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|
@ -28,7 +28,9 @@ endif
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o ../common/misc.o
|
||||
COBJS = $(BOARD).o flash.o \
|
||||
../common/misc.o \
|
||||
../common/esd405ep_nand.o \
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
|
|
@ -194,12 +194,6 @@ int misc_init_r (void)
|
|||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
|
||||
udelay(1000); /* wait 1ms */
|
||||
|
||||
/*
|
||||
* Set NAND-FLASH GPIO signals to default
|
||||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
|
||||
|
||||
/*
|
||||
* Enable interrupts in exar duart mcr[3]
|
||||
*/
|
||||
|
|
@ -340,17 +334,3 @@ void ide_set_reset(int on)
|
|||
}
|
||||
}
|
||||
#endif /* CONFIG_IDE_RESET */
|
||||
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
|
||||
#include <linux/mtd/nand_legacy.h>
|
||||
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
|
||||
|
||||
void nand_init(void)
|
||||
{
|
||||
nand_probe(CFG_NAND_BASE);
|
||||
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
|
||||
print_size(nand_dev_desc[0].totlen, "\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -28,7 +28,9 @@ endif
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o ../common/misc.o
|
||||
COBJS = $(BOARD).o flash.o \
|
||||
../common/misc.o \
|
||||
../common/esd405ep_nand.o \
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
|
|
@ -169,12 +169,6 @@ int misc_init_r (void)
|
|||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
|
||||
udelay(1000); /* wait 1ms */
|
||||
|
||||
/*
|
||||
* Set NAND-FLASH GPIO signals to default
|
||||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
|
||||
|
||||
/*
|
||||
* Enable interrupts in exar duart mcr[3]
|
||||
*/
|
||||
|
|
@ -218,35 +212,8 @@ long int initdram (int board_type)
|
|||
mtdcr(memcfga, mem_mb0cf);
|
||||
val = mfdcr(memcfgd);
|
||||
|
||||
#if 0
|
||||
printf("\nmb0cf=%x\n", val); /* test-only */
|
||||
printf("strap=%x\n", mfdcr(strap)); /* test-only */
|
||||
#endif
|
||||
|
||||
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
int testdram (void)
|
||||
{
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf ("test: 16 MB - ok\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
|
||||
#include <linux/mtd/nand_legacy.h>
|
||||
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
|
||||
|
||||
void nand_init(void)
|
||||
{
|
||||
nand_probe(CFG_NAND_BASE);
|
||||
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
|
||||
print_size(nand_dev_desc[0].totlen, "\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -53,9 +53,13 @@
|
|||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#undef CONFIG_HAS_ETH1
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0 /* PHY address */
|
||||
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
|
||||
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
|
||||
|
||||
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
|
||||
|
||||
|
|
@ -132,39 +136,16 @@
|
|||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_BIG_DELAY_US 25
|
||||
|
||||
#define CFG_NAND_LEGACY
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define SECTORSIZE 512
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
|
||||
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
|
||||
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
|
||||
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
|
||||
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
|
||||
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
|
||||
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
|
||||
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -81,8 +81,6 @@
|
|||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CFG_NAND_LEGACY
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
|
||||
|
|
@ -148,34 +146,15 @@
|
|||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define SECTORSIZE 512
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_BIG_DELAY_US 25
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
|
||||
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
|
||||
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
|
||||
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
|
||||
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
|
||||
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
|
||||
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
|
||||
|
||||
|
|
|
|||
|
|
@ -130,8 +130,6 @@
|
|||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CFG_NAND_LEGACY
|
||||
|
||||
#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
|
|
@ -198,34 +196,15 @@
|
|||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define SECTORSIZE 512
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_BIG_DELAY_US 25
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
|
||||
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
|
||||
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
|
||||
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
|
||||
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
|
||||
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
|
||||
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
|
||||
|
||||
|
|
|
|||
|
|
@ -135,36 +135,15 @@
|
|||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_NAND_LEGACY
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_BIG_DELAY_US 25
|
||||
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define SECTORSIZE 512
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
|
||||
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
|
||||
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
|
||||
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
|
||||
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
|
||||
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
|
||||
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
|
||||
|
||||
|
|
|
|||
|
|
@ -81,7 +81,6 @@
|
|||
#define CONFIG_SUPPORT_VFAT
|
||||
|
||||
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
|
||||
#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
|
@ -156,36 +155,15 @@
|
|||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_NAND_LEGACY
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_BIG_DELAY_US 25
|
||||
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define SECTORSIZE 512
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
|
||||
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
|
||||
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
|
||||
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
|
||||
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
|
||||
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
|
||||
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
|
||||
|
||||
|
|
@ -264,11 +242,6 @@
|
|||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#if 0 /* test-only */
|
||||
#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
|
||||
#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
|
|
@ -294,9 +267,6 @@
|
|||
#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
|
||||
/* total size of a CAT24WC16 is 2048 bytes */
|
||||
|
||||
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
|
||||
#define CFG_NVRAM_SIZE 242 /* NVRAM size */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (CAT24WC16) for environment
|
||||
*/
|
||||
|
|
@ -305,7 +275,7 @@
|
|||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
|
||||
#if 1 /* test-only */
|
||||
|
||||
/* CAT24WC08/16... */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
|
|
@ -313,15 +283,6 @@
|
|||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
|
||||
/* 16 byte page write mode using*/
|
||||
/* last 4 bits of the address */
|
||||
#else
|
||||
/* CAT24WC32/64... */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
|
||||
/* 32 byte page write mode using*/
|
||||
/* last 5 bits of the address */
|
||||
#endif
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE
|
||||
|
||||
|
|
|
|||
|
|
@ -141,36 +141,15 @@
|
|||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_NAND_LEGACY
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_BIG_DELAY_US 25
|
||||
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define SECTORSIZE 512
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
|
||||
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
|
||||
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
|
||||
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
|
||||
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
|
||||
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
|
||||
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
|
||||
|
||||
|
|
|
|||
|
|
@ -133,38 +133,16 @@
|
|||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_NAND_LEGACY
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_BIG_DELAY_US 25
|
||||
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define SECTORSIZE 512
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
|
||||
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
|
||||
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
|
||||
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
|
||||
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
|
||||
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
|
||||
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
|
||||
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
|
|
|
|||
Loading…
Reference in a new issue