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doc: board: Add Google Chromebook Samus board doc
This extracts Google Chromebook Samus board specific information from README.x86, converts plain text documentation to reST format and adds it to Sphinx TOC tree. No essential content change. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Bin Meng
Tom Rini
parent
c9bfc02a4a
commit
bd0d9d3ddb
3 changed files with 102 additions and 97 deletions
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@ -65,103 +65,6 @@ Both tell the Makefile to build u-boot.rom as a target.
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---
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Chromebook Samus (2015 Pixel) instructions for bare mode:
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First, you need the following binary blobs:
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* descriptor.bin - Intel flash descriptor
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* me.bin - Intel Management Engine
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* mrc.bin - Memory Reference Code, which sets up SDRAM
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* refcode.elf - Additional Reference code
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* vga.bin - video ROM, which sets up the display
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If you have a samus you can obtain them from your flash, for example, in
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developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and
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log in as 'root'):
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cd /tmp
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flashrom -w samus.bin
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scp samus.bin username@ip_address:/path/to/somewhere
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If not see the coreboot tree [4] where you can use:
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bash crosfirmware.sh samus
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to get the image. There is also an 'extract_blobs.sh' scripts that you can use
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on the 'coreboot-Google_Samus.*' file to short-circuit some of the below.
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Then 'ifdtool -x samus.bin' on your development machine will produce:
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flashregion_0_flashdescriptor.bin
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flashregion_1_bios.bin
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flashregion_2_intel_me.bin
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Rename flashregion_0_flashdescriptor.bin to descriptor.bin
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Rename flashregion_2_intel_me.bin to me.bin
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You can ignore flashregion_1_bios.bin - it is not used.
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To get the rest, use 'cbfstool samus.bin print':
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samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000
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alignment: 64 bytes, architecture: x86
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Name Offset Type Size
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cmos_layout.bin 0x700000 cmos_layout 1164
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pci8086,0406.rom 0x7004c0 optionrom 65536
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spd.bin 0x710500 (unknown) 4096
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cpu_microcode_blob.bin 0x711540 microcode 70720
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fallback/romstage 0x722a00 stage 54210
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fallback/ramstage 0x72fe00 stage 96382
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config 0x7476c0 raw 6075
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fallback/vboot 0x748ec0 stage 15980
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fallback/refcode 0x74cd80 stage 75578
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fallback/payload 0x75f500 payload 62878
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u-boot.dtb 0x76eb00 (unknown) 5318
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(empty) 0x770000 null 196504
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mrc.bin 0x79ffc0 (unknown) 222876
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(empty) 0x7d66c0 null 167320
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You can extract what you need:
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cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
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cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod
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cbfstool samus.bin extract -n mrc.bin -f mrc.bin
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cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U
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Note that the -U flag is only supported by the latest cbfstool. It unpacks
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and decompresses the stage to produce a coreboot rmodule. This is a simple
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representation of an ELF file. You need the patch "Support decoding a stage
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with compression".
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Put all 5 files into board/google/chromebook_samus.
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Now you can build U-Boot and obtain u-boot.rom:
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$ make chromebook_link_defconfig
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$ make all
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If you are using em100, then this command will flash write -Boot:
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em100 -s -d filename.rom -c W25Q64CV -r
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Flash map for samus / broadwell:
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fffff800 SYS_X86_START16
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ffff0000 RESET_SEG_START
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fffd8000 TPL_TEXT_BASE
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fffa0000 X86_MRC_ADDR
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fff90000 VGA_BIOS_ADDR
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ffed0000 SYS_TEXT_BASE
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ffea0000 X86_REFCODE_ADDR
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ffe70000 SPL_TEXT_BASE
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ffbf8000 CONFIG_ENV_OFFSET (environemnt offset)
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ffbe0000 rw-mrc-cache (Memory-reference-code cache)
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ffa00000 <spare>
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ff801000 intel-me (address set by descriptor.bin)
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ff800000 intel-descriptor
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---
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QEMU x86 target instructions for bare mode:
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To build u-boot.rom for QEMU x86 targets, just simply run
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101
doc/board/google/chromebook_samus.rst
Normal file
101
doc/board/google/chromebook_samus.rst
Normal file
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@ -0,0 +1,101 @@
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.. SPDX-License-Identifier: GPL-2.0+
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.. sectionauthor:: Simon Glass <sjg@chromium.org>
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Chromebook Samus
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================
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First, you need the following binary blobs:
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* descriptor.bin - Intel flash descriptor
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* me.bin - Intel Management Engine
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* mrc.bin - Memory Reference Code, which sets up SDRAM
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* refcode.elf - Additional Reference code
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* vga.bin - video ROM, which sets up the display
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If you have a samus you can obtain them from your flash, for example, in
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developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and
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log in as 'root')::
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cd /tmp
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flashrom -w samus.bin
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scp samus.bin username@ip_address:/path/to/somewhere
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If not see the coreboot tree where you can use::
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bash crosfirmware.sh samus
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to get the image. There is also an 'extract_blobs.sh' scripts that you can use
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on the 'coreboot-Google_Samus.*' file to short-circuit some of the below.
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Then 'ifdtool -x samus.bin' on your development machine will produce::
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flashregion_0_flashdescriptor.bin
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flashregion_1_bios.bin
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flashregion_2_intel_me.bin
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Rename flashregion_0_flashdescriptor.bin to descriptor.bin
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Rename flashregion_2_intel_me.bin to me.bin
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You can ignore flashregion_1_bios.bin - it is not used.
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To get the rest, use 'cbfstool samus.bin print'::
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samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000
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alignment: 64 bytes, architecture: x86
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============================ ======== =========== ======
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Name Offset Type Size
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============================ ======== =========== ======
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cmos_layout.bin 0x700000 cmos_layout 1164
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pci8086,0406.rom 0x7004c0 optionrom 65536
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spd.bin 0x710500 (unknown) 4096
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cpu_microcode_blob.bin 0x711540 microcode 70720
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fallback/romstage 0x722a00 stage 54210
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fallback/ramstage 0x72fe00 stage 96382
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config 0x7476c0 raw 6075
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fallback/vboot 0x748ec0 stage 15980
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fallback/refcode 0x74cd80 stage 75578
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fallback/payload 0x75f500 payload 62878
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u-boot.dtb 0x76eb00 (unknown) 5318
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(empty) 0x770000 null 196504
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mrc.bin 0x79ffc0 (unknown) 222876
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(empty) 0x7d66c0 null 167320
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============================ ======== =========== ======
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You can extract what you need::
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cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
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cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod
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cbfstool samus.bin extract -n mrc.bin -f mrc.bin
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cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U
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Note that the -U flag is only supported by the latest cbfstool. It unpacks
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and decompresses the stage to produce a coreboot rmodule. This is a simple
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representation of an ELF file. You need the patch "Support decoding a stage
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with compression".
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Put all 5 files into board/google/chromebook_samus.
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Now you can build U-Boot and obtain u-boot.rom::
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$ make chromebook_samus_defconfig
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$ make all
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If you are using em100, then this command will flash write -Boot::
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em100 -s -d filename.rom -c W25Q64CV -r
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Flash map for samus / broadwell:
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:fffff800: SYS_X86_START16
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:ffff0000: RESET_SEG_START
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:fffd8000: TPL_TEXT_BASE
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:fffa0000: X86_MRC_ADDR
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:fff90000: VGA_BIOS_ADDR
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:ffed0000: SYS_TEXT_BASE
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:ffea0000: X86_REFCODE_ADDR
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:ffe70000: SPL_TEXT_BASE
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:ffbf8000: CONFIG_ENV_OFFSET (environemnt offset)
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:ffbe0000: rw-mrc-cache (Memory-reference-code cache)
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:ffa00000: <spare>
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:ff801000: intel-me (address set by descriptor.bin)
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:ff800000: intel-descriptor
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@ -7,3 +7,4 @@ Google
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:maxdepth: 2
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chromebook_link
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chromebook_samus
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