mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-20 03:38:43 +00:00
Added PCI support for MPC8349ADS board
Patch by Kumar Gala 11 Jan 2006
This commit is contained in:
Kumar Gala
parent
c7428d49ac
commit
bc680b12d0
6 changed files with 404 additions and 48 deletions
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@ -2,6 +2,9 @@
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Changes since U-Boot 1.1.4:
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Changes since U-Boot 1.1.4:
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======================================================================
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======================================================================
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* Added PCI support for MPC8349ADS board
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Patch by Kumar Gala 11 Jan 2006
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* Add support for 28F256J3A flah (=> 64 MB) on PM520 board
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* Add support for 28F256J3A flah (=> 64 MB) on PM520 board
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* Fix compiler problem with at91rm9200dk board.
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* Fix compiler problem with at91rm9200dk board.
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@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o
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OBJS := $(BOARD).o pci.o
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$(LIB): $(OBJS) $(SOBJS)
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS)
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$(AR) crv $@ $(OBJS)
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@ -147,47 +147,6 @@ int checkboard (void)
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return 0;
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return 0;
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}
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}
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#if defined(CONFIG_PCI)
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/*
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* Initialize PCI Devices, report devices found
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*/
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_mpc83xxads_config_table[] = {
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{PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
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pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
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} },
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{}
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}
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#endif
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volatile static struct pci_controller hose[] = {
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{
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#ifndef CONFIG_PCI_PNP
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config_table:pci_mpc83xxads_config_table,
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#endif
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},
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{
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#ifndef CONFIG_PCI_PNP
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config_table:pci_mpc83xxads_config_table,
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#endif
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}
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};
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#endif /* CONFIG_PCI */
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void
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pci_init_board(void)
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{
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#ifdef CONFIG_PCI
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extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
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pci_mpc83xx_init(hose);
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#endif /* CONFIG_PCI */
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}
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/*
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/*
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* if MPC8349ADS is soldered with SDRAM
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* if MPC8349ADS is soldered with SDRAM
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*/
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*/
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387
board/mpc8349ads/pci.c
Normal file
387
board/mpc8349ads/pci.c
Normal file
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@ -0,0 +1,387 @@
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/*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <asm/mmu.h>
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#include <common.h>
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#include <asm/global_data.h>
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#include <pci.h>
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#include <asm/mpc8349_pci.h>
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#include <i2c.h>
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#ifdef CONFIG_PCI
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/* System RAM mapped to PCI space */
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#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_mpc83xxads_config_table[] = {
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{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_IDSEL_NUMBER, PCI_ANY_ID,
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pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
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}
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},
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{}
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};
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#endif
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static struct pci_controller pci_hose[] = {
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{
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#ifndef CONFIG_PCI_PNP
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config_table:pci_mpc83xxads_config_table,
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#endif
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},
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{
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#ifndef CONFIG_PCI_PNP
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config_table:pci_mpc83xxads_config_table,
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#endif
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}
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};
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/**************************************************************************
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*
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* pib_init() -- initialize the PCA9555PW IO expander on the PIB board
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*
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*/
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void
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pib_init(void)
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{
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u8 val8;
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/*
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* Assign PIB PMC slot to desired PCI bus
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*/
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mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
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i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
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val8 = 0;
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i2c_write(0x23, 0x6, 1, &val8, 1);
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i2c_write(0x23, 0x7, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x23, 0x2, 1, &val8, 1);
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i2c_write(0x23, 0x3, 1, &val8, 1);
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val8 = 0;
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i2c_write(0x26, 0x6, 1, &val8, 1);
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val8 = 0x34;
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i2c_write(0x26, 0x7, 1, &val8, 1);
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#if defined(PCI_64BIT)
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val8 = 0xf4; /* PMC2:PCI1/64-bit */
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#elif defined(PCI_ALL_PCI1)
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val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
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#elif defined(PCI_ONE_PCI1)
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val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
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#else
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val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
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#endif
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i2c_write(0x26, 0x2, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x26, 0x3, 1, &val8, 1);
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val8 = 0;
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i2c_write(0x27, 0x6, 1, &val8, 1);
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i2c_write(0x27, 0x7, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x27, 0x2, 1, &val8, 1);
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val8 = 0xef;
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i2c_write(0x27, 0x3, 1, &val8, 1);
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asm("eieio");
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#if defined(PCI_64BIT)
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printf("PCI1: 64-bit on PMC2\n");
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#elif defined(PCI_ALL_PCI1)
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printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
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#elif defined(PCI_ONE_PCI1)
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printf("PCI1: 32-bit on PMC1\n");
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printf("PCI2: 32-bit on PMC2, PMC3\n");
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#else
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printf("PCI1: 32-bit on PMC1, PMC2\n");
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printf("PCI2: 32-bit on PMC3\n");
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#endif
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}
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/**************************************************************************
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* pci_init_board()
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*
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* NOTICE: PCI2 is not currently supported
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*
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*/
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void
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pci_init_board(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile immap_t * immr;
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volatile clk8349_t * clk;
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volatile law8349_t * pci_law;
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volatile pot8349_t * pci_pot;
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volatile pcictrl8349_t * pci_ctrl;
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volatile pciconf8349_t * pci_conf;
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u16 reg16;
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u32 reg32;
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struct pci_controller * hose;
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immr = (immap_t *)CFG_IMMRBAR;
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clk = (clk8349_t *)&immr->clk;
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pci_law = immr->sysconf.pcilaw;
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pci_pot = immr->ios.pot;
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pci_ctrl = immr->pci_ctrl;
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pci_conf = immr->pci_conf;
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hose = &pci_hose[0];
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pib_init();
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/*
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* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
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*/
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reg32 = clk->occr;
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udelay(2000);
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clk->occr = 0xff000000;
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udelay(2000);
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/*
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* Release PCI RST Output signal
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*/
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pci_ctrl[0].gcr = 0;
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udelay(2000);
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pci_ctrl[0].gcr = 1;
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#ifdef CONFIG_MPC83XX_PCI2
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pci_ctrl[1].gcr = 0;
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udelay(2000);
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pci_ctrl[1].gcr = 1;
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#endif
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/* We need to wait at least a 1sec based on PCI specs */
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{
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int i;
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for (i = 0; i < 1000; ++i)
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udelay (1000);
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}
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/*
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* Configure PCI Local Access Windows
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*/
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pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
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pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
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/*
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* Configure PCI Outbound Translation Windows
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*/
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/* PCI1 mem space - prefetch */
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pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
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/* PCI1 IO space */
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pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
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/* PCI1 mmio - non-prefetch mem space */
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pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
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/*
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* Configure PCI Inbound Translation Windows
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*/
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/* we need RAM mapped to PCI space for the devices to
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* access main memory */
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pci_ctrl[0].pitar1 = 0x0;
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pci_ctrl[0].pibar1 = 0x0;
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pci_ctrl[0].piebar1 = 0x0;
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pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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/* PCI memory prefetch space */
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pci_set_region(hose->regions + 0,
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CFG_PCI1_MEM_BASE,
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CFG_PCI1_MEM_PHYS,
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CFG_PCI1_MEM_SIZE,
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PCI_REGION_MEM|PCI_REGION_PREFETCH);
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/* PCI memory space */
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pci_set_region(hose->regions + 1,
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CFG_PCI1_MMIO_BASE,
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CFG_PCI1_MMIO_PHYS,
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CFG_PCI1_MMIO_SIZE,
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PCI_REGION_MEM);
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/* PCI IO space */
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pci_set_region(hose->regions + 2,
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CFG_PCI1_IO_BASE,
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CFG_PCI1_IO_PHYS,
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CFG_PCI1_IO_SIZE,
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PCI_REGION_IO);
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/* System memory space */
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pci_set_region(hose->regions + 3,
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CONFIG_PCI_SYS_MEM_BUS,
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CONFIG_PCI_SYS_MEM_PHYS,
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gd->ram_size,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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hose->region_count = 4;
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pci_setup_indirect(hose,
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(CFG_IMMRBAR+0x8300),
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(CFG_IMMRBAR+0x8304));
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pci_register_hose(hose);
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/*
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* Write to Command register
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*/
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reg16 = 0xff;
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pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
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®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
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reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
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0xffff);
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pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
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0x80);
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pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_CACHE_LINE_SIZE,
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0x08);
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#ifdef CONFIG_PCI_SCAN_SHOW
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printf("PCI: Bus Dev VenId DevId Class Int\n");
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#endif
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/*
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* Hose scan.
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*/
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hose->last_busno = pci_hose_scan(hose);
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#ifdef CONFIG_MPC83XX_PCI2
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hose = &pci_hose[1];
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/*
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* Configure PCI Outbound Translation Windows
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*/
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/* PCI2 mem space - prefetch */
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pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
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||||||
|
pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
|
||||||
|
pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
|
||||||
|
|
||||||
|
/* PCI2 IO space */
|
||||||
|
pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
|
||||||
|
pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
|
||||||
|
pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
|
||||||
|
|
||||||
|
/* PCI2 mmio - non-prefetch mem space */
|
||||||
|
pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
|
||||||
|
pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
|
||||||
|
pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configure PCI Inbound Translation Windows
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* we need RAM mapped to PCI space for the devices to
|
||||||
|
* access main memory */
|
||||||
|
pci_ctrl[1].pitar1 = 0x0;
|
||||||
|
pci_ctrl[1].pibar1 = 0x0;
|
||||||
|
pci_ctrl[1].piebar1 = 0x0;
|
||||||
|
pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
|
||||||
|
|
||||||
|
hose->first_busno = pci_hose[0].last_busno + 1;
|
||||||
|
hose->last_busno = 0xff;
|
||||||
|
|
||||||
|
/* PCI memory prefetch space */
|
||||||
|
pci_set_region(hose->regions + 0,
|
||||||
|
CFG_PCI2_MEM_BASE,
|
||||||
|
CFG_PCI2_MEM_PHYS,
|
||||||
|
CFG_PCI2_MEM_SIZE,
|
||||||
|
PCI_REGION_MEM|PCI_REGION_PREFETCH);
|
||||||
|
|
||||||
|
/* PCI memory space */
|
||||||
|
pci_set_region(hose->regions + 1,
|
||||||
|
CFG_PCI2_MMIO_BASE,
|
||||||
|
CFG_PCI2_MMIO_PHYS,
|
||||||
|
CFG_PCI2_MMIO_SIZE,
|
||||||
|
PCI_REGION_MEM);
|
||||||
|
|
||||||
|
/* PCI IO space */
|
||||||
|
pci_set_region(hose->regions + 2,
|
||||||
|
CFG_PCI2_IO_BASE,
|
||||||
|
CFG_PCI2_IO_PHYS,
|
||||||
|
CFG_PCI2_IO_SIZE,
|
||||||
|
PCI_REGION_IO);
|
||||||
|
|
||||||
|
/* System memory space */
|
||||||
|
pci_set_region(hose->regions + 3,
|
||||||
|
CONFIG_PCI_SYS_MEM_BUS,
|
||||||
|
CONFIG_PCI_SYS_MEM_PHYS,
|
||||||
|
gd->ram_size,
|
||||||
|
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||||
|
|
||||||
|
hose->region_count = 4;
|
||||||
|
|
||||||
|
pci_setup_indirect(hose,
|
||||||
|
(CFG_IMMRBAR+0x8380),
|
||||||
|
(CFG_IMMRBAR+0x8384));
|
||||||
|
|
||||||
|
pci_register_hose(hose);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Write to Command register
|
||||||
|
*/
|
||||||
|
reg16 = 0xff;
|
||||||
|
pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
|
||||||
|
®16);
|
||||||
|
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
||||||
|
pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
|
||||||
|
reg16);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Clear non-reserved bits in status register.
|
||||||
|
*/
|
||||||
|
pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
|
||||||
|
0xffff);
|
||||||
|
pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
|
||||||
|
0x80);
|
||||||
|
pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_CACHE_LINE_SIZE,
|
||||||
|
0x08);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Hose scan.
|
||||||
|
*/
|
||||||
|
hose->last_busno = pci_hose_scan(hose);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_PCI */
|
||||||
|
|
@ -77,6 +77,7 @@
|
||||||
#define POCMR_ENABLE 0x80000000
|
#define POCMR_ENABLE 0x80000000
|
||||||
#define POCMR_PCI_IO 0x40000000
|
#define POCMR_PCI_IO 0x40000000
|
||||||
#define POCMR_PREFETCH_EN 0x20000000
|
#define POCMR_PREFETCH_EN 0x20000000
|
||||||
|
#define POCMR_PCI2 0x10000000
|
||||||
|
|
||||||
/* Soft PCI reset */
|
/* Soft PCI reset */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -41,9 +41,8 @@
|
||||||
#define CONFIG_MPC8349 1 /* MPC8349 specific */
|
#define CONFIG_MPC8349 1 /* MPC8349 specific */
|
||||||
#define CONFIG_MPC8349ADS 1 /* MPC8349ADS board specific */
|
#define CONFIG_MPC8349ADS 1 /* MPC8349ADS board specific */
|
||||||
|
|
||||||
/* FIXME: Real PCI support will come in a follow-up update. */
|
#define CONFIG_PCI
|
||||||
#undef CONFIG_PCI
|
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
|
||||||
|
|
||||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
|
|
@ -324,16 +323,23 @@
|
||||||
* General PCI
|
* General PCI
|
||||||
* Addresses are mapped 1-1.
|
* Addresses are mapped 1-1.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define CFG_PCI1_MEM_BASE 0x80000000
|
#define CFG_PCI1_MEM_BASE 0x80000000
|
||||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
|
||||||
|
#define CFG_PCI1_MMIO_BASE 0x90000000
|
||||||
|
#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
|
||||||
|
#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
|
||||||
#define CFG_PCI1_IO_BASE 0x00000000
|
#define CFG_PCI1_IO_BASE 0x00000000
|
||||||
#define CFG_PCI1_IO_PHYS 0xe2000000
|
#define CFG_PCI1_IO_PHYS 0xe2000000
|
||||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||||
|
|
||||||
#define CFG_PCI2_MEM_BASE 0xA0000000
|
#define CFG_PCI2_MEM_BASE 0xa0000000
|
||||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
|
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
|
||||||
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
|
#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
|
||||||
|
#define CFG_PCI2_MMIO_BASE 0xb0000000
|
||||||
|
#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE
|
||||||
|
#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */
|
||||||
#define CFG_PCI2_IO_BASE 0x00000000
|
#define CFG_PCI2_IO_BASE 0x00000000
|
||||||
#define CFG_PCI2_IO_PHYS 0xe3000000
|
#define CFG_PCI2_IO_PHYS 0xe3000000
|
||||||
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
|
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue