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armv8/ls1043a: Implement workaround for erratum A009660
Memory controller performance is not optimal with default internal target queue register value, write required value for optimal DDR performance. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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2 changed files with 20 additions and 0 deletions
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@ -213,6 +213,24 @@ static void erratum_a009929(void)
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#endif
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#endif
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}
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}
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/*
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* This erratum requires setting a value to eddrtqcr1 to optimal
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* the DDR performance. The eddrtqcr1 register is in SCFG space
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* of LS1043A and the offset is 0x157_020c.
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*/
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#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
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&& defined(CONFIG_SYS_FSL_ERRATUM_A008514)
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#error A009660 and A008514 can not be both enabled.
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#endif
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static void erratum_a009660(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
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u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
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out_be32(eddrtqcr1, 0x63b20042);
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#endif
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}
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void fsl_lsch2_early_init_f(void)
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void fsl_lsch2_early_init_f(void)
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{
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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@ -238,6 +256,7 @@ void fsl_lsch2_early_init_f(void)
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/* Erratum */
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/* Erratum */
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erratum_a009929();
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erratum_a009929();
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erratum_a009660();
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}
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}
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#endif
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#endif
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@ -178,6 +178,7 @@
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#define CONFIG_SYS_FSL_ERRATUM_A009663
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#define CONFIG_SYS_FSL_ERRATUM_A009663
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#define CONFIG_SYS_FSL_ERRATUM_A009929
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#define CONFIG_SYS_FSL_ERRATUM_A009929
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#define CONFIG_SYS_FSL_ERRATUM_A009942
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#define CONFIG_SYS_FSL_ERRATUM_A009942
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#define CONFIG_SYS_FSL_ERRATUM_A009660
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#else
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#else
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#error SoC not defined
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#error SoC not defined
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#endif
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#endif
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