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Changed PPC405GPr version from A to B.

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This commit is contained in:
stroese 2003-04-04 16:00:33 +00:00
parent c1551ea817
commit baa3d528fe
4 changed files with 6 additions and 6 deletions
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6
cpu/ppc4xx/cpu.c
View file

@ -67,7 +67,7 @@ int checkcpu (void)
#if CONFIG_405GP
puts("IBM PowerPC 405GP");
if (pvr == PVR_405GPR_RA) {
if (pvr == PVR_405GPR_RB) {
putc('r');
}
puts(" Rev. ");
@ -77,6 +77,7 @@ int checkcpu (void)
#endif
switch (pvr) {
case PVR_405GP_RB:
case PVR_405GPR_RB:
putc('B');
break;
case PVR_405GP_RC:
@ -94,7 +95,6 @@ int checkcpu (void)
break;
#endif
case PVR_405CR_RA:
case PVR_405GPR_RA:
putc('A');
break;
case PVR_405CR_RB:
@ -122,7 +122,7 @@ int checkcpu (void)
printf("external PCI arbiter enabled\n");
#endif
if ((pvr | 0x00000001) == PVR_405GPR_RA) {
if ((pvr | 0x00000001) == PVR_405GPR_RB) {
printf(" 16 kB I-Cache 16 kB D-Cache");
} else {
printf(" 16 kB I-Cache 8 kB D-Cache");

2
cpu/ppc4xx/cpu_init.c
View file

@ -149,7 +149,7 @@ int cpu_init_r (void)
* Set edge conditioning circuitry on PPC405GPr
* for compatibility to existing PPC405GP designs.
*/
if ((pvr & 0xfffffff0) == (PVR_405GPR_RA & 0xfffffff0)) {
if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
mtdcr(ecr, 0x60606000);
}

2
cpu/ppc4xx/speed.c
View file

@ -87,7 +87,7 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo)
/*
* Check if PPC405GPr used (mask minor revision field)
*/
if ((pvr & 0xfffffff0) == (PVR_405GPR_RA & 0xfffffff0)) {
if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
/*
* Determine FWD_DIV B (only PPC405GPr with new mode strapping).
*/

2
include/asm-ppc/processor.h
View file

@ -462,7 +462,7 @@
#define PVR_405CR_RA 0x40110041
#define PVR_405CR_RB 0x401100C5
#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
#define PVR_405GPR_RA 0x50910951
#define PVR_405GPR_RB 0x50910951
#define PVR_440GP_RB 0x40120440
#define PVR_440GP_RC 0x40120481
#define PVR_601 0x00010000