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https://github.com/AsahiLinux/u-boot
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i2c: designware_i2c: Add support for PCI(e) based I2C cores (x86)
This patch adds support for the PCI(e) based I2C cores. Which can be found for example on the Intel Bay Trail SoC. It has 7 I2C controllers implemented as PCI devices. This patch also adds the fixed values for the timing registers for BayTrail which are taken from the Linux designware I2C driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Stefan Roese
Heiko Schocher
parent
334b9b004c
commit
ba5da550ae
1 changed files with 106 additions and 12 deletions
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@ -8,11 +8,32 @@
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#include <common.h>
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#include <dm.h>
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#include <i2c.h>
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#include <pci.h>
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#include <asm/io.h>
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#include "designware_i2c.h"
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struct dw_scl_sda_cfg {
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u32 ss_hcnt;
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u32 fs_hcnt;
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u32 ss_lcnt;
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u32 fs_lcnt;
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u32 sda_hold;
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};
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#ifdef CONFIG_X86
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/* BayTrail HCNT/LCNT/SDA hold time */
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static struct dw_scl_sda_cfg byt_config = {
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.ss_hcnt = 0x200,
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.fs_hcnt = 0x55,
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.ss_lcnt = 0x200,
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.fs_lcnt = 0x99,
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.sda_hold = 0x6,
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};
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#endif
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struct dw_i2c {
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struct i2c_regs *regs;
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struct dw_scl_sda_cfg *scl_sda_cfg;
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};
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static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
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@ -43,6 +64,7 @@ static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
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* Set the i2c speed.
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*/
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static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
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struct dw_scl_sda_cfg *scl_sda_cfg,
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unsigned int speed)
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{
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unsigned int cntl;
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@ -62,34 +84,55 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
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cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
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switch (i2c_spd) {
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#ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
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case IC_SPEED_MODE_MAX:
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cntl |= IC_CON_SPD_HS;
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hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
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cntl |= IC_CON_SPD_SS;
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if (scl_sda_cfg) {
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hcnt = scl_sda_cfg->fs_hcnt;
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lcnt = scl_sda_cfg->fs_lcnt;
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} else {
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hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
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lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
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}
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writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
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lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
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writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
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break;
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#endif
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case IC_SPEED_MODE_STANDARD:
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cntl |= IC_CON_SPD_SS;
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hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
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if (scl_sda_cfg) {
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hcnt = scl_sda_cfg->ss_hcnt;
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lcnt = scl_sda_cfg->ss_lcnt;
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} else {
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hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
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lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
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}
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writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
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lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
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writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
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break;
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case IC_SPEED_MODE_FAST:
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default:
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cntl |= IC_CON_SPD_FS;
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hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
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if (scl_sda_cfg) {
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hcnt = scl_sda_cfg->fs_hcnt;
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lcnt = scl_sda_cfg->fs_lcnt;
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} else {
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hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
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lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
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}
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writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
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lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
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writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
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break;
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}
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writel(cntl, &i2c_base->ic_con);
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/* Configure SDA Hold Time if required */
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if (scl_sda_cfg)
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writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
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/* Enable back i2c now speed set */
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dw_i2c_enable(i2c_base, true);
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@ -316,7 +359,7 @@ static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
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writel(IC_TX_TL, &i2c_base->ic_tx_tl);
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writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
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#ifndef CONFIG_DM_I2C
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__dw_i2c_set_bus_speed(i2c_base, speed);
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__dw_i2c_set_bus_speed(i2c_base, NULL, speed);
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writel(slaveaddr, &i2c_base->ic_sar);
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#endif
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@ -357,7 +400,7 @@ static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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{
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adap->speed = speed;
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return __dw_i2c_set_bus_speed(i2c_get_base(adap), speed);
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return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
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}
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static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
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@ -448,7 +491,7 @@ static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
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{
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struct dw_i2c *i2c = dev_get_priv(bus);
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return __dw_i2c_set_bus_speed(i2c->regs, speed);
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return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
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}
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static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
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@ -471,14 +514,48 @@ static int designware_i2c_probe(struct udevice *bus)
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{
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struct dw_i2c *priv = dev_get_priv(bus);
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/* Save base address from device-tree */
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priv->regs = (struct i2c_regs *)dev_get_addr(bus);
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if (device_is_on_pci_bus(bus)) {
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#ifdef CONFIG_DM_PCI
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/* Save base address from PCI BAR */
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priv->regs = (struct i2c_regs *)
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dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
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#ifdef CONFIG_X86
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/* Use BayTrail specific timing values */
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priv->scl_sda_cfg = &byt_config;
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#endif
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#endif
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} else {
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priv->regs = (struct i2c_regs *)dev_get_addr_ptr(bus);
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}
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__dw_i2c_init(priv->regs, 0, 0);
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return 0;
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}
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static int designware_i2c_bind(struct udevice *dev)
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{
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static int num_cards;
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char name[20];
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/* Create a unique device name for PCI type devices */
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if (device_is_on_pci_bus(dev)) {
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/*
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* ToDo:
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* Setting req_seq in the driver is probably not recommended.
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* But without a DT alias the number is not configured. And
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* using this driver is impossible for PCIe I2C devices.
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* This can be removed, once a better (correct) way for this
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* is found and implemented.
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*/
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dev->req_seq = num_cards;
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sprintf(name, "i2c_designware#%u", num_cards++);
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device_set_name(dev, name);
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}
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return 0;
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}
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static const struct dm_i2c_ops designware_i2c_ops = {
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.xfer = designware_i2c_xfer,
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.probe_chip = designware_i2c_probe_chip,
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@ -494,9 +571,26 @@ U_BOOT_DRIVER(i2c_designware) = {
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.name = "i2c_designware",
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.id = UCLASS_I2C,
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.of_match = designware_i2c_ids,
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.bind = designware_i2c_bind,
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.probe = designware_i2c_probe,
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.priv_auto_alloc_size = sizeof(struct dw_i2c),
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.ops = &designware_i2c_ops,
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};
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#ifdef CONFIG_X86
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static struct pci_device_id designware_pci_supported[] = {
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/* Intel BayTrail has 7 I2C controller located on the PCI bus */
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{ PCI_VDEVICE(INTEL, 0x0f41) },
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{ PCI_VDEVICE(INTEL, 0x0f42) },
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{ PCI_VDEVICE(INTEL, 0x0f43) },
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{ PCI_VDEVICE(INTEL, 0x0f44) },
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{ PCI_VDEVICE(INTEL, 0x0f45) },
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{ PCI_VDEVICE(INTEL, 0x0f46) },
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{ PCI_VDEVICE(INTEL, 0x0f47) },
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{},
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};
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U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
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#endif
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#endif /* CONFIG_DM_I2C */
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