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clk: stm32f7: cleanup clocks unused definitions
clean the code by removing unused enums, structs and defines related to clocks Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
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4 changed files with 0 additions and 46 deletions
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@ -13,41 +13,19 @@
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/*
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/*
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* RCC AHB1ENR specific definitions
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* RCC AHB1ENR specific definitions
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*/
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*/
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#define RCC_AHB1ENR_GPIO_A_EN BIT(0)
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#define RCC_AHB1ENR_GPIO_B_EN BIT(1)
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#define RCC_AHB1ENR_GPIO_C_EN BIT(2)
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#define RCC_AHB1ENR_GPIO_D_EN BIT(3)
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#define RCC_AHB1ENR_GPIO_E_EN BIT(4)
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#define RCC_AHB1ENR_GPIO_F_EN BIT(5)
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#define RCC_AHB1ENR_GPIO_G_EN BIT(6)
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#define RCC_AHB1ENR_GPIO_H_EN BIT(7)
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#define RCC_AHB1ENR_GPIO_I_EN BIT(8)
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#define RCC_AHB1ENR_GPIO_J_EN BIT(9)
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#define RCC_AHB1ENR_GPIO_K_EN BIT(10)
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#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
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#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
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#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
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#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
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#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
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#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
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#define RCC_AHB1ENR_ETHMAC_PTP_EN BIT(28)
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/*
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* RCC AHB3ENR specific definitions
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*/
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#define RCC_AHB3ENR_FMC_EN BIT(0)
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#define RCC_AHB3ENR_QSPI_EN BIT(1)
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/*
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/*
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* RCC APB1ENR specific definitions
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* RCC APB1ENR specific definitions
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*/
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*/
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#define RCC_APB1ENR_TIM2EN BIT(0)
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#define RCC_APB1ENR_TIM2EN BIT(0)
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#define RCC_APB1ENR_USART2EN BIT(17)
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#define RCC_APB1ENR_USART3EN BIT(18)
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#define RCC_APB1ENR_PWREN BIT(28)
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#define RCC_APB1ENR_PWREN BIT(28)
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/*
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/*
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* RCC APB2ENR specific definitions
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* RCC APB2ENR specific definitions
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*/
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*/
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#define RCC_APB2ENR_USART1EN BIT(4)
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#define RCC_APB2ENR_USART6EN BIT(5)
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#define RCC_APB2ENR_SYSCFGEN BIT(14)
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#define RCC_APB2ENR_SYSCFGEN BIT(14)
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#endif
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#endif
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@ -58,7 +58,6 @@ static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
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};
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};
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enum clock {
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enum clock {
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CLOCK_CORE,
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CLOCK_AHB,
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CLOCK_AHB,
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CLOCK_APB1,
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CLOCK_APB1,
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CLOCK_APB2
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CLOCK_APB2
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@ -101,11 +100,6 @@ struct stm32_rcc_regs {
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};
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};
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#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
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#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
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struct stm32_rcc_ext_f7_regs {
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u32 dckcfgr2; /* dedicated clocks configuration register */
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};
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#define STM32_RCC_EXT_F7 ((struct stm32_rcc_ext_f7_regs *) (RCC_BASE + sizeof(struct stm32_rcc_regs)))
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struct stm32_pwr_regs {
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struct stm32_pwr_regs {
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u32 cr1; /* power control register 1 */
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u32 cr1; /* power control register 1 */
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u32 csr1; /* power control/status register 2 */
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u32 csr1; /* power control/status register 2 */
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@ -21,24 +21,9 @@ enum periph_id {
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};
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};
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enum periph_clock {
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enum periph_clock {
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USART1_CLOCK_CFG = 0,
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USART2_CLOCK_CFG,
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GPIO_A_CLOCK_CFG,
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GPIO_B_CLOCK_CFG,
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GPIO_C_CLOCK_CFG,
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GPIO_D_CLOCK_CFG,
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GPIO_E_CLOCK_CFG,
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GPIO_F_CLOCK_CFG,
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GPIO_G_CLOCK_CFG,
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GPIO_H_CLOCK_CFG,
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GPIO_I_CLOCK_CFG,
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GPIO_J_CLOCK_CFG,
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GPIO_K_CLOCK_CFG,
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SYSCFG_CLOCK_CFG,
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SYSCFG_CLOCK_CFG,
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TIMER2_CLOCK_CFG,
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TIMER2_CLOCK_CFG,
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FMC_CLOCK_CFG,
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STMMAC_CLOCK_CFG,
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STMMAC_CLOCK_CFG,
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QSPI_CLOCK_CFG,
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};
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};
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#endif /* __ASM_ARM_ARCH_PERIPH_H */
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#endif /* __ASM_ARM_ARCH_PERIPH_H */
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@ -195,9 +195,6 @@ unsigned long clock_get(enum clock clck)
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}
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}
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switch (clck) {
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switch (clck) {
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case CLOCK_CORE:
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return sysclk;
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break;
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case CLOCK_AHB:
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case CLOCK_AHB:
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shift = ahb_psc_table[(
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shift = ahb_psc_table[(
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(readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
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(readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
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