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Merge branch 'master' of git://git.denx.de/u-boot

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This commit is contained in:
Stefano Babic 2015-03-02 09:42:53 +01:00
commit b9cb64825b
877 changed files with 9895 additions and 10843 deletions
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3
.travis.yml
View file

@ -106,9 +106,6 @@ matrix:
- env:
- TEST_CMD="tools/buildman/buildman mpc512x"
INSTALL_TOOLCHAIN="ppc"
- env:
- TEST_CMD="tools/buildman/buildman mpc824x"
INSTALL_TOOLCHAIN="ppc"
- env:
- TEST_CMD="tools/buildman/buildman mpc8260"
INSTALL_TOOLCHAIN="ppc"

55
Kconfig
View file

@ -8,15 +8,13 @@ config UBOOTVERSION
string
option env="UBOOTVERSION"
config KCONFIG_OBJDIR
string
option env="KCONFIG_OBJDIR"
# Allow defaults in arch-specific code to override any given here
source "arch/Kconfig"
menu "General setup"
config LOCALVERSION
string "Local version - append to U-Boot release"
depends on !SPL_BUILD
help
Append an extra string to the end of your U-Boot version.
This will show up on your boot log, for example.
@ -27,7 +25,6 @@ config LOCALVERSION
config LOCALVERSION_AUTO
bool "Automatically append version information to the version string"
depends on !SPL_BUILD
default y
help
This will try to automatically determine if the current tree is a
@ -48,7 +45,6 @@ config LOCALVERSION_AUTO
config CC_OPTIMIZE_FOR_SIZE
bool "Optimize for size"
depends on !SPL_BUILD
default y
help
Enabling this option will pass "-Os" instead of "-O2" to gcc
@ -56,6 +52,25 @@ config CC_OPTIMIZE_FOR_SIZE
This option is enabled by default for U-Boot.
config SYS_MALLOC_F
bool "Enable malloc() pool before relocation"
default 0x400
help
Before relocation memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
config SYS_MALLOC_F_LEN
hex "Size of malloc() pool before relocation"
depends on SYS_MALLOC_F
default 0x400
help
Before relocation memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
menuconfig EXPERT
bool "Configure standard U-Boot features (expert users)"
help
@ -68,16 +83,6 @@ endmenu # General setup
menu "Boot images"
config SPL_BUILD
bool
depends on $KCONFIG_OBJDIR="spl" || $KCONFIG_OBJDIR="tpl"
default y
config TPL_BUILD
bool
depends on $KCONFIG_OBJDIR="tpl"
default y
config SUPPORT_SPL
bool
@ -87,23 +92,19 @@ config SUPPORT_TPL
config SPL
bool
depends on SUPPORT_SPL
prompt "Enable SPL" if !SPL_BUILD
default y if SPL_BUILD
prompt "Enable SPL"
help
If you want to build SPL as well as the normal image, say Y.
config TPL
bool
depends on SPL && SUPPORT_TPL
prompt "Enable TPL" if !SPL_BUILD
default y if TPL_BUILD
default n
prompt "Enable TPL"
help
If you want to build TPL as well as the normal image and SPL, say Y.
config FIT
bool "Support Flattened Image Tree"
depends on !SPL_BUILD
help
This option allows to boot the new uImage structrure,
Flattened Image Tree. FIT is formally a FDT, which can include
@ -118,15 +119,17 @@ config FIT_VERBOSE
config FIT_SIGNATURE
bool "Enable signature verification of FIT uImages"
depends on FIT
depends on DM
select RSA
help
This option enables signature verification of FIT uImages,
using a hash signed and verified using RSA.
using a hash signed and verified using RSA. If
CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
hashing is available using hardware, RSA library will use it.
See doc/uImage.FIT/signature.txt for more details.
config SYS_EXTRA_OPTIONS
string "Extra Options (DEPRECATED)"
depends on !SPL_BUILD
help
The old configuration infrastructure (= mkconfig + boards.cfg)
provided the extra options field. If you have something like
@ -152,8 +155,6 @@ config SYS_CLK_FREQ
endmenu # Boot images
source "arch/Kconfig"
source "common/Kconfig"
source "dts/Kconfig"
@ -165,3 +166,5 @@ source "drivers/Kconfig"
source "fs/Kconfig"
source "lib/Kconfig"
source "test/Kconfig"

11
MAINTAINERS
View file

@ -76,9 +76,7 @@ ARM ATMEL AT91
M: Andreas Bießmann <andreas.devel@googlemail.com>
S: Maintained
T: git git://git.denx.de/u-boot-atmel.git
F: arch/arm/cpu/armv7/at91/
F: arch/arm/cpu/at91-common/
F: arch/arm/include/asm/arch-at91/
F: arch/arm/mach-at91/
ARM FREESCALE IMX
M: Stefano Babic <sbabic@denx.de>
@ -100,8 +98,7 @@ M: Prafulla Wadaskar <prafulla@marvell.com>
M: Luka Perkov <luka.perkov@sartura.hr>
S: Maintained
T: git git://git.denx.de/u-boot-marvell.git
F: arch/arm/cpu/arm926ejs/kirkwood/
F: arch/arm/include/asm/arch-kirkwood/
F: arch/arm/mach-kirkwood/
ARM MARVELL PXA
M: Marek Vasut <marex@denx.de>
@ -147,9 +144,7 @@ ARM TEGRA
M: Tom Warren <twarren@nvidia.com>
S: Maintained
T: git git://git.denx.de/u-boot-tegra.git
F: arch/arm/cpu/arm720t/tegra*/
F: arch/arm/cpu/armv7/tegra*/
F: arch/arm/cpu/tegra*/
F: arch/arm/mach-tegra/
F: arch/arm/include/asm/arch-tegra*/
ARM TI

7
Makefile
View file

@ -1,7 +1,7 @@
VERSION = 2015
PATCHLEVEL = 04
SUBLEVEL =
EXTRAVERSION = -rc1
EXTRAVERSION = -rc2
NAME =
# *DOCUMENTATION*
@ -281,6 +281,11 @@ os_x_before = $(shell if [ $(DARWIN_MAJOR_VERSION) -le $(1) -a \
HOSTCC = $(call os_x_before, 10, 5, "cc", "gcc")
HOSTCFLAGS += $(call os_x_before, 10, 4, "-traditional-cpp")
HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress")
# since Lion (10.7) ASLR is on by default, but we use linker generated lists
# in some host tools which is a problem then ... so disable ASLR for these
# tools
HOSTLDFLAGS += $(call os_x_before, 10, 7, "", "-Xlinker -no_pie")
endif
# Decide whether to build built-in, modular, or both.

23
README
View file

@ -3152,8 +3152,18 @@ CBFS (Coreboot Filesystem) support
Enable the hash verify command (hash -v). This adds to code
size a little.
CONFIG_SHA1 - support SHA1 hashing
CONFIG_SHA256 - support SHA256 hashing
CONFIG_SHA1 - This option enables support of hashing using SHA1
algorithm. The hash is calculated in software.
CONFIG_SHA256 - This option enables support of hashing using
SHA256 algorithm. The hash is calculated in software.
CONFIG_SHA_HW_ACCEL - This option enables hardware acceleration
for SHA1/SHA256 hashing.
This affects the 'hash' command and also the
hash_lookup_algo() function.
CONFIG_SHA_PROG_HW_ACCEL - This option enables
hardware-acceleration for SHA1/SHA256 progressive hashing.
Data can be streamed in a block at a time and the hashing
is performed in hardware.
Note: There is also a sha1sum command, which should perhaps
be deprecated in favour of 'hash sha1'.
@ -3447,8 +3457,10 @@ FIT uImage format:
CONFIG_FIT_SIGNATURE
This option enables signature verification of FIT uImages,
using a hash signed and verified using RSA. See
doc/uImage.FIT/signature.txt for more details.
using a hash signed and verified using RSA. If
CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
hashing is available using hardware, RSA library will use it.
See doc/uImage.FIT/signature.txt for more details.
WARNING: When relying on signed FIT images with required
signature check the legacy image format is default
@ -4919,6 +4931,9 @@ Low Level (hardware related) configuration options:
- CONFIG_FSL_DDR_INTERACTIVE
Enable interactive DDR debugging. See doc/README.fsl-ddr.
- CONFIG_FSL_DDR_SYNC_REFRESH
Enable sync of refresh for multiple controllers.
- CONFIG_SYS_83XX_DDR_USES_CS0
Only for 83xx systems. If specified, then DDR should
be configured using CS0 and CS1 instead of CS2 and CS3.

1
arch/Kconfig
View file

@ -40,6 +40,7 @@ config OPENRISC
config PPC
bool "PowerPC architecture"
select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
config SANDBOX
bool "Sandbox"

59
arch/arc/Kconfig
View file

@ -8,30 +8,79 @@ config USE_PRIVATE_LIBGCC
default y
config SYS_CPU
default "arcv1"
default "arcv1" if ISA_ARCOMPACT
default "arcv2" if ISA_ARCV2
choice
prompt "ARC Instruction Set"
default ISA_ARCOMPACT
config ISA_ARCOMPACT
bool "ARCompact ISA"
help
The original ARC ISA of ARC600/700 cores
config ISA_ARCV2
bool "ARC ISA v2"
help
ISA for the Next Generation ARC-HS cores
endchoice
choice
prompt "CPU selection"
default CPU_ARC770D
default CPU_ARC770D if ISA_ARCOMPACT
default CPU_ARCHS38 if ISA_ARCV2
config CPU_ARC750D
bool "ARC 750D"
select ARC_MMU_V2
depends on ISA_ARCOMPACT
help
Choose this option to build an U-Boot for ARC750D CPU.
config CPU_ARC770D
bool "ARC 770D"
select ARC_MMU_V3
depends on ISA_ARCOMPACT
help
Choose this option to build an U-Boot for ARC770D CPU.
config CPU_ARCEM6
bool "ARC EM6"
select ARC_MMU_ABSENT
depends on ISA_ARCV2
help
Next Generation ARC Core based on ISA-v2 ISA without MMU.
config CPU_ARCHS36
bool "ARC HS36"
select ARC_MMU_ABSENT
depends on ISA_ARCV2
help
Next Generation ARC Core based on ISA-v2 ISA without MMU.
config CPU_ARCHS38
bool "ARC HS38"
select ARC_MMU_V4
depends on ISA_ARCV2
help
Next Generation ARC Core based on ISA-v2 ISA with MMU.
endchoice
choice
prompt "MMU Version"
default ARC_MMU_V3 if CPU_ARC770D
default ARC_MMU_V2 if CPU_ARC750D
default ARC_MMU_ABSENT if CPU_ARCEM6
default ARC_MMU_ABSENT if CPU_ARCHS36
default ARC_MMU_V4 if CPU_ARCHS38
config ARC_MMU_ABSENT
bool "No MMU"
help
No MMU
config ARC_MMU_V2
bool "MMU v2"
@ -48,6 +97,12 @@ config ARC_MMU_V3
Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
Shared Address Spaces (SASID)
config ARC_MMU_V4
bool "MMU v4"
depends on CPU_ARCHS38
help
Introduced as a part of ARC HS38 release.
endchoice
config CPU_BIG_ENDIAN

12
arch/arc/config.mk
View file

@ -38,6 +38,18 @@ ifdef CONFIG_CPU_ARC770D
PLATFORM_CPPFLAGS += -marc700 -mlock -mswape
endif
ifdef CONFIG_CPU_ARCEM6
PLATFORM_CPPFLAGS += -marcem
endif
ifdef CONFIG_CPU_ARCHS34
PLATFORM_CPPFLAGS += -marchs
endif
ifdef CONFIG_CPU_ARCHS38
PLATFORM_CPPFLAGS += -marchs
endif
PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
# Needed for relocation

7
arch/arc/cpu/arcv2/Makefile Normal file
View file

@ -0,0 +1,7 @@
#
# Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += start.o

254
arch/arc/cpu/arcv2/start.S Normal file
View file

@ -0,0 +1,254 @@
/*
* Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/arcregs.h>
/*
* Note on the LD/ST addressing modes with address register write-back
*
* LD.a same as LD.aw
*
* LD.a reg1, [reg2, x] => Pre Incr
* Eff Addr for load = [reg2 + x]
*
* LD.ab reg1, [reg2, x] => Post Incr
* Eff Addr for load = [reg2]
*/
.macro PUSH reg
st.a \reg, [%sp, -4]
.endm
.macro PUSHAX aux
lr %r9, [\aux]
PUSH %r9
.endm
.macro SAVE_R1_TO_R24
PUSH %r1
PUSH %r2
PUSH %r3
PUSH %r4
PUSH %r5
PUSH %r6
PUSH %r7
PUSH %r8
PUSH %r9
PUSH %r10
PUSH %r11
PUSH %r12
PUSH %r13
PUSH %r14
PUSH %r15
PUSH %r16
PUSH %r17
PUSH %r18
PUSH %r19
PUSH %r20
PUSH %r21
PUSH %r22
PUSH %r23
PUSH %r24
.endm
.macro SAVE_ALL_SYS
/* saving %r0 to reg->r0 in advance since weread %ecr into it */
st %r0, [%sp, -8]
lr %r0, [%ecr] /* all stack addressing is manual so far */
st %r0, [%sp]
st %sp, [%sp, -4]
/* now move %sp to reg->r0 position so we can do "push" automatically */
sub %sp, %sp, 8
SAVE_R1_TO_R24
PUSH %r25
PUSH %gp
PUSH %fp
PUSH %blink
PUSHAX %eret
PUSHAX %erstatus
PUSH %lp_count
PUSHAX %lp_end
PUSHAX %lp_start
PUSHAX %erbta
.endm
.macro SAVE_EXCEPTION_SOURCE
#ifdef CONFIG_MMU
/* If MMU exists exception faulting address is loaded in EFA reg */
lr %r0, [%efa]
#else
/* Otherwise in ERET (exception return) reg */
lr %r0, [%eret]
#endif
.endm
.section .ivt, "a",@progbits
.align 4
/* Critical system events */
.word _start /* 0 - 0x000 */
.word memory_error /* 1 - 0x008 */
.word instruction_error /* 2 - 0x010 */
/* Exceptions */
.word EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */
.word EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */
.word EV_TLBMissD /* 0x110, Data TLB miss (0x22) */
.word EV_TLBProtV /* 0x118, Protection Violation (0x23)
or Misaligned Access */
.word EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */
.word EV_Trap /* 0x128, Trap exception (0x25) */
.word EV_Extension /* 0x130, Extn Intruction Excp (0x26) */
/* Device interrupts */
.rept 29
j interrupt_handler /* 3:31 - 0x018:0xF8 */
.endr
.text
.globl _start
_start:
/* Setup interrupt vector base that matches "__text_start" */
sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
/* Setup stack pointer */
mov %sp, CONFIG_SYS_INIT_SP_ADDR
mov %fp, %sp
/* Clear bss */
mov %r0, __bss_start
mov %r1, __bss_end
clear_bss:
st.ab 0, [%r0, 4]
brlt %r0, %r1, clear_bss
/* Zero the one and only argument of "board_init_f" */
mov_s %r0, 0
j board_init_f
memory_error:
SAVE_ALL_SYS
SAVE_EXCEPTION_SOURCE
mov %r1, %sp
j do_memory_error
instruction_error:
SAVE_ALL_SYS
SAVE_EXCEPTION_SOURCE
mov %r1, %sp
j do_instruction_error
interrupt_handler:
/* Todo - save and restore CPU context when interrupts will be in use */
bl do_interrupt_handler
rtie
EV_MachineCheck:
SAVE_ALL_SYS
SAVE_EXCEPTION_SOURCE
mov %r1, %sp
j do_machine_check_fault
EV_TLBMissI:
SAVE_ALL_SYS
mov %r0, %sp
j do_itlb_miss
EV_TLBMissD:
SAVE_ALL_SYS
mov %r0, %sp
j do_dtlb_miss
EV_TLBProtV:
SAVE_ALL_SYS
SAVE_EXCEPTION_SOURCE
mov %r1, %sp
j do_tlb_prot_violation
EV_PrivilegeV:
SAVE_ALL_SYS
mov %r0, %sp
j do_privilege_violation
EV_Trap:
SAVE_ALL_SYS
mov %r0, %sp
j do_trap
EV_Extension:
SAVE_ALL_SYS
mov %r0, %sp
j do_extension
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r0 = start_addr_sp
* r1 = new__gd
* r2 = relocaddr
*/
.align 4
.globl relocate_code
relocate_code:
/*
* r0-r12 might be clobbered by C functions
* so we use r13-r16 for storage here
*/
mov %r13, %r0 /* save addr_sp */
mov %r14, %r1 /* save addr of gd */
mov %r15, %r2 /* save addr of destination */
mov %r16, %r2 /* %r9 - relocation offset */
sub %r16, %r16, __image_copy_start
/* Set up the stack */
stack_setup:
mov %sp, %r13
mov %fp, %sp
/* Check if monitor is loaded right in place for relocation */
mov %r0, __image_copy_start
cmp %r0, %r15 /* skip relocation if code loaded */
bz do_board_init_r /* in target location already */
/* Copy data (__image_copy_start - __image_copy_end) to new location */
mov %r1, %r15
mov %r2, __image_copy_end
sub %r2, %r2, %r0 /* r3 <- amount of bytes to copy */
asr %r2, %r2, 2 /* r3 <- amount of words to copy */
mov %lp_count, %r2
lp copy_end
ld.ab %r2,[%r0,4]
st.ab %r2,[%r1,4]
copy_end:
/* Fix relocations related issues */
bl do_elf_reloc_fixups
#ifndef CONFIG_SYS_ICACHE_OFF
bl invalidate_icache_all
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
bl flush_dcache_all
#endif
/* Update position of intterupt vector table */
lr %r0, [ARC_AUX_INTR_VEC_BASE] /* Read current position */
add %r0, %r0, %r16 /* Update address */
sr %r0, [ARC_AUX_INTR_VEC_BASE] /* Write new position */
do_board_init_r:
/* Prepare for exection of "board_init_r" in relocated monitor */
mov %r2, board_init_r /* old address of "board_init_r()" */
add %r2, %r2, %r16 /* new address of "board_init_r()" */
mov %r0, %r14 /* 1-st parameter: gd_t */
mov %r1, %r15 /* 2-nd parameter: dest_addr */
j [%r2]

6
arch/arc/include/asm/cache.h
View file

@ -17,10 +17,14 @@
#define ARCH_DMA_MINALIGN 128
#endif
#if defined(CONFIG_ARC_MMU_V2)
#if defined(ARC_MMU_ABSENT)
#define CONFIG_ARC_MMU_VER 0
#elif defined(CONFIG_ARC_MMU_V2)
#define CONFIG_ARC_MMU_VER 2
#elif defined(CONFIG_ARC_MMU_V3)
#define CONFIG_ARC_MMU_VER 3
#elif defined(CONFIG_ARC_MMU_V4)
#define CONFIG_ARC_MMU_VER 4
#endif
#endif /* __ASM_ARC_CACHE_H */

217
arch/arm/Kconfig
View file

@ -73,21 +73,8 @@ config TARGET_INTEGRATORCP_CM920T
bool "Support integratorcp_cm920t"
select CPU_ARM920T
config TARGET_A320EVB
bool "Support a320evb"
select CPU_ARM920T
config TARGET_AT91RM9200EK
bool "Support at91rm9200ek"
select CPU_ARM920T
config TARGET_EB_CPUX9K2
bool "Support eb_cpux9k2"
select CPU_ARM920T
config TARGET_CPUAT91
bool "Support cpuat91"
select CPU_ARM920T
config ARCH_AT91
bool "Atmel AT91"
config TARGET_EDB93XX
bool "Support edb93xx"
@ -97,14 +84,6 @@ config TARGET_SCB9328
bool "Support scb9328"
select CPU_ARM920T
config TARGET_CM4008
bool "Support cm4008"
select CPU_ARM920T
config TARGET_CM41XX
bool "Support cm41xx"
select CPU_ARM920T
config TARGET_VCMA9
bool "Support VCMA9"
select CPU_ARM920T
@ -129,100 +108,6 @@ config TARGET_GPLUGD
bool "Support gplugd"
select CPU_ARM926EJS
config TARGET_AFEB9260
bool "Support afeb9260"
select CPU_ARM926EJS
config TARGET_AT91SAM9260EK
bool "Support at91sam9260ek"
select CPU_ARM926EJS
config TARGET_AT91SAM9261EK
bool "Support at91sam9261ek"
select CPU_ARM926EJS
config TARGET_AT91SAM9263EK
bool "Support at91sam9263ek"
select CPU_ARM926EJS
config TARGET_AT91SAM9M10G45EK
bool "Support at91sam9m10g45ek"
select CPU_ARM926EJS
config TARGET_AT91SAM9N12EK
bool "Support at91sam9n12ek"
select CPU_ARM926EJS
config TARGET_AT91SAM9RLEK
bool "Support at91sam9rlek"
select CPU_ARM926EJS
config TARGET_AT91SAM9X5EK
bool "Support at91sam9x5ek"
select CPU_ARM926EJS
config TARGET_SNAPPER9260
bool "Support snapper9260"
select CPU_ARM926EJS
config TARGET_VL_MA2SC
bool "Support vl_ma2sc"
select CPU_ARM926EJS
config TARGET_SBC35_A9G20
bool "Support sbc35_a9g20"
select CPU_ARM926EJS
config TARGET_TNY_A9260
bool "Support tny_a9260"
select CPU_ARM926EJS
config TARGET_USB_A9263
bool "Support usb_a9263"
select CPU_ARM926EJS
config TARGET_ETHERNUT5
bool "Support ethernut5"
select CPU_ARM926EJS
config TARGET_MEESC
bool "Support meesc"
select CPU_ARM926EJS
config TARGET_OTC570
bool "Support otc570"
select CPU_ARM926EJS
config TARGET_CPU9260
bool "Support cpu9260"
select CPU_ARM926EJS
config TARGET_PM9261
bool "Support pm9261"
select CPU_ARM926EJS
config TARGET_PM9263
bool "Support pm9263"
select CPU_ARM926EJS
config TARGET_PM9G45
bool "Support pm9g45"
select CPU_ARM926EJS
config TARGET_CORVUS
select SUPPORT_SPL
bool "Support corvus"
select CPU_ARM926EJS
config TARGET_TAURUS
select SUPPORT_SPL
bool "Support taurus"
select CPU_ARM926EJS
config TARGET_STAMP9G20
bool "Support stamp9g20"
select CPU_ARM926EJS
config ARCH_DAVINCI
bool "TI DaVinci"
select CPU_ARM926EJS
@ -247,10 +132,6 @@ config TARGET_DEVKIT3250
bool "Support devkit3250"
select CPU_ARM926EJS
config TARGET_JADECPU
bool "Support jadecpu"
select CPU_ARM926EJS
config TARGET_MX25PDK
bool "Support mx25pdk"
select CPU_ARM926EJS
@ -330,10 +211,6 @@ config ORION5X
bool "Marvell Orion"
select CPU_ARM926EJS
config TARGET_DKB
bool "Support dkb"
select CPU_ARM926EJS
config TARGET_SPEAR300
bool "Support spear300"
select CPU_ARM926EJS
@ -413,9 +290,9 @@ config TARGET_RPI
bool "Support rpi"
select CPU_ARM1176
config TARGET_TNETV107X_EVM
bool "Support tnetv107x_evm"
select CPU_ARM1176
config TARGET_RPI_2
bool "Support rpi_2"
select CPU_V7
config TARGET_INTEGRATORAP_CM946ES
bool "Support integratorap_cm946es"
@ -514,26 +391,6 @@ config TARGET_TI816X_EVM
select CPU_V7
select SUPPORT_SPL
config TARGET_SAMA5D3_XPLAINED
bool "Support sama5d3_xplained"
select CPU_V7
select SUPPORT_SPL
config TARGET_SAMA5D3XEK
bool "Support sama5d3xek"
select CPU_V7
select SUPPORT_SPL
config TARGET_SAMA5D4_XPLAINED
bool "Support sama5d4_xplained"
select CPU_V7
select SUPPORT_SPL
config TARGET_SAMA5D4EK
bool "Support sama5d4ek"
select CPU_V7
select SUPPORT_SPL
config TARGET_BCM28155_AP
bool "Support bcm28155_ap"
select CPU_V7
@ -743,9 +600,8 @@ config TEGRA
bool "NVIDIA Tegra"
select SUPPORT_SPL
select SPL
select OF_CONTROL if !SPL_BUILD
select CPU_ARM720T if SPL_BUILD
select CPU_V7 if !SPL_BUILD
select OF_CONTROL
select CPU_V7
config TARGET_VEXPRESS64_AEMV8A
bool "Support vexpress_aemv8a"
@ -837,21 +693,25 @@ config ARCH_UNIPHIER
select CPU_V7
select SUPPORT_SPL
select SPL
select OF_CONTROL if !SPL_BUILD
select OF_CONTROL
endchoice
source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
source "arch/arm/mach-at91/Kconfig"
source "arch/arm/mach-davinci/Kconfig"
source "arch/arm/cpu/arm1176/bcm2835/Kconfig"
source "arch/arm/cpu/armv7/exynos/Kconfig"
source "arch/arm/cpu/armv7/highbank/Kconfig"
source "arch/arm/mach-highbank/Kconfig"
source "arch/arm/cpu/armv7/keystone/Kconfig"
source "arch/arm/mach-keystone/Kconfig"
source "arch/arm/cpu/arm926ejs/kirkwood/Kconfig"
source "arch/arm/mach-kirkwood/Kconfig"
source "arch/arm/cpu/arm926ejs/nomadik/Kconfig"
source "arch/arm/mach-nomadik/Kconfig"
source "arch/arm/cpu/armv7/omap3/Kconfig"
@ -859,17 +719,17 @@ source "arch/arm/cpu/armv7/omap4/Kconfig"
source "arch/arm/cpu/armv7/omap5/Kconfig"
source "arch/arm/cpu/arm926ejs/orion5x/Kconfig"
source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/cpu/armv7/rmobile/Kconfig"
source "arch/arm/cpu/armv7/s5pc1xx/Kconfig"
source "arch/arm/cpu/armv7/tegra-common/Kconfig"
source "arch/arm/mach-tegra/Kconfig"
source "arch/arm/cpu/armv7/uniphier/Kconfig"
source "arch/arm/cpu/arm926ejs/versatile/Kconfig"
source "arch/arm/mach-versatile/Kconfig"
source "arch/arm/cpu/armv7/zynq/Kconfig"
@ -878,47 +738,25 @@ source "arch/arm/cpu/armv7/Kconfig"
source "board/aristainetos/Kconfig"
source "board/BuR/kwb/Kconfig"
source "board/BuR/tseries/Kconfig"
source "board/BuS/eb_cpux9k2/Kconfig"
source "board/BuS/vl_ma2sc/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/db-mv784mp-gp/Kconfig"
source "board/Marvell/dkb/Kconfig"
source "board/Marvell/gplugd/Kconfig"
source "board/afeb9260/Kconfig"
source "board/altera/socfpga/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/integrator/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/atmel/at91rm9200ek/Kconfig"
source "board/atmel/at91sam9260ek/Kconfig"
source "board/atmel/at91sam9261ek/Kconfig"
source "board/atmel/at91sam9263ek/Kconfig"
source "board/atmel/at91sam9m10g45ek/Kconfig"
source "board/atmel/at91sam9n12ek/Kconfig"
source "board/atmel/at91sam9rlek/Kconfig"
source "board/atmel/at91sam9x5ek/Kconfig"
source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"
source "board/atmel/sama5d4_xplained/Kconfig"
source "board/atmel/sama5d4ek/Kconfig"
source "board/bachmann/ot1200/Kconfig"
source "board/balloon3/Kconfig"
source "board/barco/platinum/Kconfig"
source "board/barco/titanium/Kconfig"
source "board/bluegiga/apx4devkit/Kconfig"
source "board/bluewater/snapper9260/Kconfig"
source "board/boundary/nitrogen6x/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
source "board/calao/sbc35_a9g20/Kconfig"
source "board/calao/tny_a9260/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
source "board/cm4008/Kconfig"
source "board/cm41xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
@ -926,14 +764,8 @@ source "board/creative/xfi3/Kconfig"
source "board/davedenx/qong/Kconfig"
source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/embest/mx6boards/Kconfig"
source "board/esd/meesc/Kconfig"
source "board/esd/otc570/Kconfig"
source "board/esg/ima3-mx53/Kconfig"
source "board/eukrea/cpu9260/Kconfig"
source "board/eukrea/cpuat91/Kconfig"
source "board/faraday/a320evb/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
@ -977,18 +809,14 @@ source "board/phytec/pcm051/Kconfig"
source "board/ppcag/bg0900/Kconfig"
source "board/pxa255_idp/Kconfig"
source "board/raspberrypi/rpi/Kconfig"
source "board/ronetix/pm9261/Kconfig"
source "board/ronetix/pm9263/Kconfig"
source "board/ronetix/pm9g45/Kconfig"
source "board/raspberrypi/rpi_2/Kconfig"
source "board/samsung/smdk2410/Kconfig"
source "board/sandisk/sansa_fuze_plus/Kconfig"
source "board/scb9328/Kconfig"
source "board/schulercontrol/sc_sps_1/Kconfig"
source "board/siemens/corvus/Kconfig"
source "board/siemens/draco/Kconfig"
source "board/siemens/pxm2/Kconfig"
source "board/siemens/rut/Kconfig"
source "board/siemens/taurus/Kconfig"
source "board/silica/pengwyn/Kconfig"
source "board/solidrun/hummingboard/Kconfig"
source "board/spear/spear300/Kconfig"
@ -1000,15 +828,12 @@ source "board/st-ericsson/snowball/Kconfig"
source "board/st-ericsson/u8500/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/sunxi/Kconfig"
source "board/syteco/jadecpu/Kconfig"
source "board/syteco/zmx25/Kconfig"
source "board/taskit/stamp9g20/Kconfig"
source "board/tbs/tbs2910/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
source "board/ti/tnetv107xevm/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/tqc/tqma6/Kconfig"

24
arch/arm/Makefile
View file

@ -2,6 +2,27 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
machine-$(CONFIG_ARCH_AT91) += at91
machine-$(CONFIG_ARCH_DAVINCI) += davinci
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
machine-$(CONFIG_KIRKWOOD) += kirkwood
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
machine-$(CONFIG_TEGRA) += tegra
machine-$(CONFIG_ARCH_VERSATILE) += versatile
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
libs-y += $(machdirs)
head-y := arch/arm/cpu/$(CPU)/start.o
ifeq ($(CONFIG_SPL_BUILD),y)
@ -27,3 +48,6 @@ endif
ifneq (,$(filter $(SOC), armada-xp kirkwood))
libs-y += arch/arm/mvebu-common/
endif
# deprecated
-include $(machdirs)/config.mk

7
arch/arm/cpu/Makefile
View file

@ -1,6 +1 @@
obj-$(CONFIG_AT91FAMILY) += at91-common/
obj-$(CONFIG_TEGRA20) += tegra20-common/
obj-$(CONFIG_TEGRA30) += tegra30-common/
obj-$(CONFIG_TEGRA114) += tegra114-common/
obj-$(CONFIG_TEGRA124) += tegra124-common/
obj-$(CONFIG_TEGRA) += tegra-common/
obj- += dummy.o

1
arch/arm/cpu/arm1176/Makefile
View file

@ -12,4 +12,3 @@ extra-y = start.o
obj-y = cpu.o
obj-$(CONFIG_BCM2835) += bcm2835/
obj-$(CONFIG_TNETV107X) += tnetv107x/

12
arch/arm/cpu/arm1176/bcm2835/Kconfig Normal file
View file

@ -0,0 +1,12 @@
if TARGET_RPI || TARGET_RPI_2
config DM
default y
config DM_SERIAL
default y
config DM_GPIO
default y
endif

12
arch/arm/cpu/arm1176/bcm2835/Makefile
View file

@ -1,15 +1,7 @@
#
# See file CREDITS for list of people who contributed to this
# project.
# (C) Copyright 2012 Stephen Warren
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License
# version 2 as published by the Free Software Foundation.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
# SPDX-License-Identifier: GPL-2.0
#
obj-y := lowlevel_init.o

22
arch/arm/cpu/arm1176/start.S
View file

@ -96,28 +96,6 @@ mmu_disable:
mov pc, r2
mmu_disable_phys:
#ifdef CONFIG_DISABLE_TCM
/*
* Disable the TCMs
*/
mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
cmp r0, #0
beq skip_tcmdisable
mov r1, #0
mov r2, #1
tst r0, r2
mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
tst r0, r2, LSL #16
mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
skip_tcmdisable:
#endif
#endif
#ifdef CONFIG_PERIPORT_REMAP
/* Peri port setup */
ldr r0, =CONFIG_PERIPORT_BASE
orr r0, r0, #CONFIG_PERIPORT_SIZE
mcr p15,0,r0,c15,c2,4
#endif
/*

6
arch/arm/cpu/arm1176/tnetv107x/Makefile
View file

@ -1,6 +0,0 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += aemif.o clock.o init.o mux.o timer.o
obj-y += lowlevel_init.o

78
arch/arm/cpu/arm1176/tnetv107x/aemif.c
View file

@ -1,78 +0,0 @@
/*
* TNETV107X: Asynchronous EMIF Configuration
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/mux.h>
#define ASYNC_EMIF_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
#define ASYNC_EMIF_CONFIG(cs) (ASYNC_EMIF_BASE+0x10+(cs)*4)
#define ASYNC_EMIF_ONENAND_CONTROL (ASYNC_EMIF_BASE+0x5c)
#define ASYNC_EMIF_NAND_CONTROL (ASYNC_EMIF_BASE+0x60)
#define ASYNC_EMIF_WAITCYCLE_CONFIG (ASYNC_EMIF_BASE+0x4)
#define CONFIG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
#define CONFIG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
#define CONFIG_WR_SETUP(v) (((v) & 0x0f) << 26)
#define CONFIG_WR_STROBE(v) (((v) & 0x3f) << 20)
#define CONFIG_WR_HOLD(v) (((v) & 0x07) << 17)
#define CONFIG_RD_SETUP(v) (((v) & 0x0f) << 13)
#define CONFIG_RD_STROBE(v) (((v) & 0x3f) << 7)
#define CONFIG_RD_HOLD(v) (((v) & 0x07) << 4)
#define CONFIG_TURN_AROUND(v) (((v) & 0x03) << 2)
#define CONFIG_WIDTH(v) (((v) & 0x03) << 0)
#define NUM_CS 4
#define set_config_field(reg, field, val) \
do { \
if (val != -1) { \
reg &= ~CONFIG_##field(0xffffffff); \
reg |= CONFIG_##field(val); \
} \
} while (0)
void configure_async_emif(int cs, struct async_emif_config *cfg)
{
unsigned long tmp;
if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL);
tmp |= (1 << cs);
__raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL);
} else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL);
tmp |= (1 << cs);
__raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL);
}
tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs));
set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
set_config_field(tmp, WR_SETUP, cfg->wr_setup);
set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
set_config_field(tmp, WR_HOLD, cfg->wr_hold);
set_config_field(tmp, RD_SETUP, cfg->rd_setup);
set_config_field(tmp, RD_STROBE, cfg->rd_strobe);
set_config_field(tmp, RD_HOLD, cfg->rd_hold);
set_config_field(tmp, TURN_AROUND, cfg->turn_around);
set_config_field(tmp, WIDTH, cfg->width);
__raw_writel(tmp, ASYNC_EMIF_CONFIG(cs));
}
void init_async_emif(int num_cs, struct async_emif_config *config)
{
int cs;
clk_enable(TNETV107X_LPSC_AEMIF);
for (cs = 0; cs < num_cs; cs++)
configure_async_emif(cs, config + cs);
}

432
arch/arm/cpu/arm1176/tnetv107x/clock.c
View file

@ -1,432 +0,0 @@
/*
* TNETV107X: Clock management APIs
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm-generic/errno.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/arch/clock.h>
#define CLOCK_BASE TNETV107X_CLOCK_CONTROL_BASE
#define PSC_BASE TNETV107X_PSC_BASE
#define BIT(x) (1 << (x))
#define MAX_PREDIV 64
#define MAX_POSTDIV 8UL
#define MAX_MULT 512
#define MAX_DIV (MAX_PREDIV * MAX_POSTDIV)
/* LPSC registers */
#define PSC_PTCMD 0x120
#define PSC_PTSTAT 0x128
#define PSC_MDSTAT(n) (0x800 + (n) * 4)
#define PSC_MDCTL(n) (0xA00 + (n) * 4)
#define PSC_MDCTL_LRSTZ BIT(8)
#define psc_reg_read(reg) __raw_readl((u32 *)(PSC_BASE + (reg)))
#define psc_reg_write(reg, val) __raw_writel(val, (u32 *)(PSC_BASE + (reg)))
/* SSPLL registers */
struct sspll_regs {
u32 modes;
u32 postdiv;
u32 prediv;
u32 mult_factor;
u32 divider_range;
u32 bw_divider;
u32 spr_amount;
u32 spr_rate_div;
u32 diag;
};
/* SSPLL base addresses */
static struct sspll_regs *sspll_regs[] = {
(struct sspll_regs *)(CLOCK_BASE + 0x040),
(struct sspll_regs *)(CLOCK_BASE + 0x080),
(struct sspll_regs *)(CLOCK_BASE + 0x0c0),
};
#define sspll_reg(pll, reg) (&(sspll_regs[pll]->reg))
#define sspll_reg_read(pll, reg) __raw_readl(sspll_reg(pll, reg))
#define sspll_reg_write(pll, reg, val) __raw_writel(val, sspll_reg(pll, reg))
/* PLL Control Registers */
struct pllctl_regs {
u32 ctl; /* 00 */
u32 ocsel; /* 04 */
u32 secctl; /* 08 */
u32 __pad0;
u32 mult; /* 10 */
u32 prediv; /* 14 */
u32 div1; /* 18 */
u32 div2; /* 1c */
u32 div3; /* 20 */
u32 oscdiv1; /* 24 */
u32 postdiv; /* 28 */
u32 bpdiv; /* 2c */
u32 wakeup; /* 30 */
u32 __pad1;
u32 cmd; /* 38 */
u32 stat; /* 3c */
u32 alnctl; /* 40 */
u32 dchange; /* 44 */
u32 cken; /* 48 */
u32 ckstat; /* 4c */
u32 systat; /* 50 */
u32 ckctl; /* 54 */
u32 __pad2[2];
u32 div4; /* 60 */
u32 div5; /* 64 */
u32 div6; /* 68 */
u32 div7; /* 6c */
u32 div8; /* 70 */
};
struct lpsc_map {
int pll, div;
};
static struct pllctl_regs *pllctl_regs[] = {
(struct pllctl_regs *)(CLOCK_BASE + 0x700),
(struct pllctl_regs *)(CLOCK_BASE + 0x300),
(struct pllctl_regs *)(CLOCK_BASE + 0x500),
};
#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
#define pllctl_reg_rmw(pll, reg, mask, val) \
pllctl_reg_write(pll, reg, \
(pllctl_reg_read(pll, reg) & ~(mask)) | val)
#define pllctl_reg_setbits(pll, reg, mask) \
pllctl_reg_rmw(pll, reg, 0, mask)
#define pllctl_reg_clrbits(pll, reg, mask) \
pllctl_reg_rmw(pll, reg, mask, 0)
/* PLLCTL Bits */
#define PLLCTL_CLKMODE BIT(8)
#define PLLCTL_PLLSELB BIT(7)
#define PLLCTL_PLLENSRC BIT(5)
#define PLLCTL_PLLDIS BIT(4)
#define PLLCTL_PLLRST BIT(3)
#define PLLCTL_PLLPWRDN BIT(1)
#define PLLCTL_PLLEN BIT(0)
#define PLLDIV_ENABLE BIT(15)
static int pll_div_offset[] = {
#define div_offset(reg) offsetof(struct pllctl_regs, reg)
div_offset(div1), div_offset(div2), div_offset(div3),
div_offset(div4), div_offset(div5), div_offset(div6),
div_offset(div7), div_offset(div8),
};
static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
/* Mappings from PLL+DIV to subsystem clocks */
#define sys_arm1176_clk {SYS_PLL, 0}
#define sys_dsp_clk {SYS_PLL, 1}
#define sys_ddr_clk {SYS_PLL, 2}
#define sys_full_clk {SYS_PLL, 3}
#define sys_lcd_clk {SYS_PLL, 4}
#define sys_vlynq_ref_clk {SYS_PLL, 5}
#define sys_tsc_clk {SYS_PLL, 6}
#define sys_half_clk {SYS_PLL, 7}
#define eth_clk_5 {ETH_PLL, 0}
#define eth_clk_50 {ETH_PLL, 1}
#define eth_clk_125 {ETH_PLL, 2}
#define eth_clk_250 {ETH_PLL, 3}
#define eth_clk_25 {ETH_PLL, 4}
#define tdm_clk {TDM_PLL, 0}
#define tdm_extra_clk {TDM_PLL, 1}
#define tdm1_clk {TDM_PLL, 2}
static const struct lpsc_map lpsc_clk_map[] = {
[TNETV107X_LPSC_ARM] = sys_arm1176_clk,
[TNETV107X_LPSC_GEM] = sys_dsp_clk,
[TNETV107X_LPSC_DDR2_PHY] = sys_ddr_clk,
[TNETV107X_LPSC_TPCC] = sys_full_clk,
[TNETV107X_LPSC_TPTC0] = sys_full_clk,
[TNETV107X_LPSC_TPTC1] = sys_full_clk,
[TNETV107X_LPSC_RAM] = sys_full_clk,
[TNETV107X_LPSC_MBX_LITE] = sys_arm1176_clk,
[TNETV107X_LPSC_LCD] = sys_lcd_clk,
[TNETV107X_LPSC_ETHSS] = eth_clk_125,
[TNETV107X_LPSC_AEMIF] = sys_full_clk,
[TNETV107X_LPSC_CHIP_CFG] = sys_half_clk,
[TNETV107X_LPSC_TSC] = sys_tsc_clk,
[TNETV107X_LPSC_ROM] = sys_half_clk,
[TNETV107X_LPSC_UART2] = sys_half_clk,
[TNETV107X_LPSC_PKTSEC] = sys_half_clk,
[TNETV107X_LPSC_SECCTL] = sys_half_clk,
[TNETV107X_LPSC_KEYMGR] = sys_half_clk,
[TNETV107X_LPSC_KEYPAD] = sys_half_clk,
[TNETV107X_LPSC_GPIO] = sys_half_clk,
[TNETV107X_LPSC_MDIO] = sys_half_clk,
[TNETV107X_LPSC_SDIO0] = sys_half_clk,
[TNETV107X_LPSC_UART0] = sys_half_clk,
[TNETV107X_LPSC_UART1] = sys_half_clk,
[TNETV107X_LPSC_TIMER0] = sys_half_clk,
[TNETV107X_LPSC_TIMER1] = sys_half_clk,
[TNETV107X_LPSC_WDT_ARM] = sys_half_clk,
[TNETV107X_LPSC_WDT_DSP] = sys_half_clk,
[TNETV107X_LPSC_SSP] = sys_half_clk,
[TNETV107X_LPSC_TDM0] = tdm_clk,
[TNETV107X_LPSC_VLYNQ] = sys_vlynq_ref_clk,
[TNETV107X_LPSC_MCDMA] = sys_half_clk,
[TNETV107X_LPSC_USB0] = sys_half_clk,
[TNETV107X_LPSC_TDM1] = tdm1_clk,
[TNETV107X_LPSC_DEBUGSS] = sys_half_clk,
[TNETV107X_LPSC_ETHSS_RGMII] = eth_clk_250,
[TNETV107X_LPSC_SYSTEM] = sys_half_clk,
[TNETV107X_LPSC_IMCOP] = sys_dsp_clk,
[TNETV107X_LPSC_SPARE] = sys_half_clk,
[TNETV107X_LPSC_SDIO1] = sys_half_clk,
[TNETV107X_LPSC_USB1] = sys_half_clk,
[TNETV107X_LPSC_USBSS] = sys_half_clk,
[TNETV107X_LPSC_DDR2_EMIF1_VRST] = sys_ddr_clk,
[TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST] = sys_ddr_clk,
};
static const unsigned long pll_ext_freq[] = {
[SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
[ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
[TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
};
static unsigned long pll_freq_get(int pll)
{
unsigned long mult = 1, prediv = 1, postdiv = 1;
unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
unsigned long ret;
u32 bypass;
bypass = __raw_readl((u32 *)(CLOCK_BASE));
if (!(bypass & pll_bypass_mask[pll])) {
mult = sspll_reg_read(pll, mult_factor);
prediv = sspll_reg_read(pll, prediv) + 1;
postdiv = sspll_reg_read(pll, postdiv) + 1;
}
if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
ref = pll_ext_freq[pll];
if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
return ref;
ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
ret /= (prediv * postdiv);
return ret;
}
static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
int div)
{
int divider = 1;
unsigned long divreg;
divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
if (divreg & PLLDIV_ENABLE)
divider = (divreg & pll_div_mask[pll]) + 1;
return fpll / divider;
}
static unsigned long pll_div_freq_get(int pll, int div)
{
unsigned int fpll = pll_freq_get(pll);
return __pll_div_freq_get(pll, fpll, div);
}
static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
unsigned long hz)
{
int divider = (fpll / hz - 1);
divider &= pll_div_mask[pll];
divider |= PLLDIV_ENABLE;
__raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
pllctl_reg_setbits(pll, alnctl, (1 << div));
pllctl_reg_setbits(pll, dchange, (1 << div));
}
static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
{
unsigned int fpll = pll_freq_get(pll);
__pll_div_freq_set(pll, fpll, div, hz);
pllctl_reg_write(pll, cmd, 1);
/* Wait until new divider takes effect */
while (pllctl_reg_read(pll, stat) & 0x01);
return __pll_div_freq_get(pll, fpll, div);
}
unsigned long clk_get_rate(unsigned int clk)
{
return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
}
unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
{
unsigned long fpll, divider, pll;
pll = lpsc_clk_map[clk].pll;
fpll = pll_freq_get(pll);
divider = (fpll / hz - 1);
divider &= pll_div_mask[pll];
return fpll / (divider + 1);
}
int clk_set_rate(unsigned int clk, unsigned long _hz)
{
unsigned long hz;
hz = clk_round_rate(clk, _hz);
if (hz != _hz)
return -EINVAL; /* Cannot set to target freq */
pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
return 0;
}
void lpsc_control(int mod, unsigned long state, int lrstz)
{
u32 mdctl;
mdctl = psc_reg_read(PSC_MDCTL(mod));
mdctl &= ~0x1f;
mdctl |= state;
if (lrstz == 0)
mdctl &= ~PSC_MDCTL_LRSTZ;
else if (lrstz == 1)
mdctl |= PSC_MDCTL_LRSTZ;
psc_reg_write(PSC_MDCTL(mod), mdctl);
psc_reg_write(PSC_PTCMD, 1);
/* wait for power domain transition to end */
while (psc_reg_read(PSC_PTSTAT) & 1);
/* Wait for module state change */
while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
}
int lpsc_status(unsigned int id)
{
return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
}
static void init_pll(const struct pll_init_data *data)
{
unsigned long fpll;
unsigned long best_pre = 0, best_post = 0, best_mult = 0;
unsigned long div, prediv, postdiv, mult;
unsigned long delta, actual;
long best_delta = -1;
int i;
u32 tmp;
if (data->pll == SYS_PLL)
return; /* cannot reconfigure system pll on the fly */
tmp = pllctl_reg_read(data->pll, ctl);
if (data->internal_osc) {
tmp &= ~PLLCTL_CLKMODE;
fpll = CONFIG_SYS_INT_OSC_FREQ;
} else {
tmp |= PLLCTL_CLKMODE;
fpll = pll_ext_freq[data->pll];
}
pllctl_reg_write(data->pll, ctl, tmp);
mult = data->pll_freq / fpll;
for (mult = max(mult, 1UL); mult <= MAX_MULT; mult++) {
div = (fpll * mult) / data->pll_freq;
if (div < 1 || div > MAX_DIV)
continue;
for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
prediv = div / postdiv;
if (prediv < 1 || prediv > MAX_PREDIV)
continue;
actual = (fpll / prediv) * (mult / postdiv);
delta = (actual - data->pll_freq);
if (delta < 0)
delta = -delta;
if ((delta < best_delta) || (best_delta == -1)) {
best_delta = delta;
best_mult = mult;
best_pre = prediv;
best_post = postdiv;
if (delta == 0)
goto done;
}
}
}
done:
if (best_delta == -1) {
printf("pll cannot derive %lu from %lu\n",
data->pll_freq, fpll);
return;
}
fpll = fpll * best_mult;
fpll /= best_pre * best_post;
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
sspll_reg_write(data->pll, mult_factor, (best_mult - 1) << 8);
sspll_reg_write(data->pll, prediv, best_pre - 1);
sspll_reg_write(data->pll, postdiv, best_post - 1);
for (i = 0; i < 10; i++)
if (data->div_freq[i])
__pll_div_freq_set(data->pll, fpll, i,
data->div_freq[i]);
pllctl_reg_write(data->pll, cmd, 1);
/* Wait until pll "go" operation completes */
while (pllctl_reg_read(data->pll, stat) & 0x01);
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
}
void init_plls(int num_pll, struct pll_init_data *config)
{
int i;
for (i = 0; i < num_pll; i++)
init_pll(&config[i]);
}

22
arch/arm/cpu/arm1176/tnetv107x/init.c
View file

@ -1,22 +0,0 @@
/*
* TNETV107X: Architecture initialization
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
void chip_configuration_unlock(void)
{
__raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0);
__raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1);
}
int arch_cpu_init(void)
{
icache_enable();
chip_configuration_unlock();
return 0;
}

10
arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
View file

@ -1,10 +0,0 @@
/*
* TNETV107X: Low-level pre-relocation initialization
*
* SPDX-License-Identifier: GPL-2.0+
*/
.globl lowlevel_init
lowlevel_init:
/* nothing for now, maybe needed for more exotic boot modes */
mov pc, lr

319
arch/arm/cpu/arm1176/tnetv107x/mux.c
View file

@ -1,319 +0,0 @@
/*
* TNETV107X: Pinmux configuration
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/mux.h>
#define MUX_MODE_1 0x00
#define MUX_MODE_2 0x04
#define MUX_MODE_3 0x0c
#define MUX_MODE_4 0x1c
#define MUX_DEBUG 0
static const struct pin_config pin_table[] = {
/* reg shift mode */
TNETV107X_MUX_CFG(0, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(0, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(0, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(0, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(0, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(0, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(0, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(0, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(0, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(0, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(0, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(0, 25, MUX_MODE_2),
TNETV107X_MUX_CFG(1, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(1, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(1, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(1, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(1, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(1, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(1, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(1, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(1, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(1, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(1, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(1, 25, MUX_MODE_2),
TNETV107X_MUX_CFG(2, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(2, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(2, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(2, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(2, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(2, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(2, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(2, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(2, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(2, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(2, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(2, 25, MUX_MODE_2),
TNETV107X_MUX_CFG(3, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(3, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(3, 0, MUX_MODE_4),
TNETV107X_MUX_CFG(3, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(3, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(3, 5, MUX_MODE_4),
TNETV107X_MUX_CFG(3, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(3, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(3, 10, MUX_MODE_4),
TNETV107X_MUX_CFG(3, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(3, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(3, 15, MUX_MODE_4),
TNETV107X_MUX_CFG(3, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(3, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(3, 20, MUX_MODE_4),
TNETV107X_MUX_CFG(3, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(3, 25, MUX_MODE_2),
TNETV107X_MUX_CFG(3, 25, MUX_MODE_4),
TNETV107X_MUX_CFG(4, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(4, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(4, 0, MUX_MODE_4),
TNETV107X_MUX_CFG(4, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(4, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(4, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(4, 15, MUX_MODE_4),
TNETV107X_MUX_CFG(4, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(4, 20, MUX_MODE_3),
TNETV107X_MUX_CFG(4, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(4, 25, MUX_MODE_4),
TNETV107X_MUX_CFG(5, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(5, 0, MUX_MODE_4),
TNETV107X_MUX_CFG(5, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(5, 5, MUX_MODE_4),
TNETV107X_MUX_CFG(5, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(5, 10, MUX_MODE_4),
TNETV107X_MUX_CFG(5, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(5, 15, MUX_MODE_4),
TNETV107X_MUX_CFG(5, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(5, 20, MUX_MODE_4),
TNETV107X_MUX_CFG(5, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(5, 25, MUX_MODE_4),
TNETV107X_MUX_CFG(6, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(6, 0, MUX_MODE_4),
TNETV107X_MUX_CFG(6, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(6, 5, MUX_MODE_4),
TNETV107X_MUX_CFG(6, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(6, 10, MUX_MODE_4),
TNETV107X_MUX_CFG(6, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(6, 15, MUX_MODE_4),
TNETV107X_MUX_CFG(6, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(6, 20, MUX_MODE_4),
TNETV107X_MUX_CFG(6, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(6, 25, MUX_MODE_4),
TNETV107X_MUX_CFG(7, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(7, 0, MUX_MODE_4),
TNETV107X_MUX_CFG(7, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(7, 5, MUX_MODE_4),
TNETV107X_MUX_CFG(7, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(7, 10, MUX_MODE_4),
TNETV107X_MUX_CFG(7, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(7, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(7, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(7, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(7, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(7, 25, MUX_MODE_2),
TNETV107X_MUX_CFG(8, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(8, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(8, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(8, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(8, 5, MUX_MODE_4),
TNETV107X_MUX_CFG(8, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(8, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(9, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(9, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(9, 0, MUX_MODE_4),
TNETV107X_MUX_CFG(9, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(9, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(9, 5, MUX_MODE_4),
TNETV107X_MUX_CFG(9, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(9, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(9, 10, MUX_MODE_4),
TNETV107X_MUX_CFG(9, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(9, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(9, 15, MUX_MODE_4),
TNETV107X_MUX_CFG(9, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(9, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(9, 20, MUX_MODE_4),
TNETV107X_MUX_CFG(10, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(10, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(10, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(10, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(10, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(10, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(10, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(10, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(10, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(10, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(10, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(10, 25, MUX_MODE_2),
TNETV107X_MUX_CFG(11, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(11, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(12, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(12, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(12, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(12, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(12, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(12, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(13, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(13, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(13, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(13, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(14, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(14, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(14, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(14, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(14, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(14, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(15, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(15, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(15, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(15, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(15, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(15, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(15, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(15, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(16, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(16, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(16, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(16, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(16, 10, MUX_MODE_3),
TNETV107X_MUX_CFG(16, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(16, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(17, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(17, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(17, 0, MUX_MODE_3),
TNETV107X_MUX_CFG(17, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(17, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(17, 5, MUX_MODE_3),
TNETV107X_MUX_CFG(17, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(17, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(17, 10, MUX_MODE_3),
TNETV107X_MUX_CFG(17, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(17, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(17, 15, MUX_MODE_3),
TNETV107X_MUX_CFG(18, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(18, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(18, 0, MUX_MODE_3),
TNETV107X_MUX_CFG(18, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(18, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(18, 5, MUX_MODE_3),
TNETV107X_MUX_CFG(18, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(18, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(18, 10, MUX_MODE_3),
TNETV107X_MUX_CFG(18, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(18, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(18, 15, MUX_MODE_3),
TNETV107X_MUX_CFG(19, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(19, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(19, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(19, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(19, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(19, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(20, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(20, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(20, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(20, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(20, 15, MUX_MODE_3),
TNETV107X_MUX_CFG(20, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(20, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(21, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(21, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(21, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(21, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(21, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(21, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(22, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(22, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(22, 5, MUX_MODE_3),
TNETV107X_MUX_CFG(22, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(22, 10, MUX_MODE_3),
TNETV107X_MUX_CFG(22, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(22, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(22, 15, MUX_MODE_3),
TNETV107X_MUX_CFG(22, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(22, 20, MUX_MODE_3),
TNETV107X_MUX_CFG(22, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(22, 25, MUX_MODE_3),
TNETV107X_MUX_CFG(23, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(23, 0, MUX_MODE_3),
TNETV107X_MUX_CFG(23, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(23, 5, MUX_MODE_3),
TNETV107X_MUX_CFG(23, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(23, 10, MUX_MODE_3),
TNETV107X_MUX_CFG(24, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(24, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(24, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(24, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(24, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(24, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(24, 10, MUX_MODE_3),
TNETV107X_MUX_CFG(24, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(24, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(24, 15, MUX_MODE_3),
TNETV107X_MUX_CFG(24, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(24, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(24, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(24, 25, MUX_MODE_2),
TNETV107X_MUX_CFG(25, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(25, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(25, 0, MUX_MODE_3),
TNETV107X_MUX_CFG(25, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(25, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(25, 5, MUX_MODE_3),
TNETV107X_MUX_CFG(25, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(25, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(25, 10, MUX_MODE_3),
TNETV107X_MUX_CFG(25, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(25, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(25, 15, MUX_MODE_3),
TNETV107X_MUX_CFG(25, 15, MUX_MODE_4),
TNETV107X_MUX_CFG(26, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(26, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(26, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(26, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(26, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(26, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(26, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(26, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(26, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(26, 25, MUX_MODE_2),
};
const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
int mux_select_pin(short index)
{
const struct pin_config *cfg;
unsigned long mask, mode, reg;
if (index >= pin_table_size)
return 0;
cfg = &pin_table[index];
mask = 0x1f << cfg->mask_offset;
mode = cfg->mode << cfg->mask_offset;
reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
reg = (reg & ~mask) | mode;
__raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
return 1;
}
int mux_select_pins(const short *pins)
{
int i, ret = 1;
for (i = 0; pins[i] >= 0; i++)
ret &= mux_select_pin(pins[i]);
return ret;
}

93
arch/arm/cpu/arm1176/tnetv107x/timer.c
View file

@ -1,93 +0,0 @@
/*
* TNETV107X: Timer implementation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
struct timer_regs {
u_int32_t pid12;
u_int32_t pad[3];
u_int32_t tim12;
u_int32_t tim34;
u_int32_t prd12;
u_int32_t prd34;
u_int32_t tcr;
u_int32_t tgcr;
u_int32_t wdtcr;
};
#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE)
#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
#define TIM_CLK_DIV 16
static ulong timestamp;
static ulong lastinc;
int timer_init(void)
{
clk_enable(TNETV107X_LPSC_TIMER0);
lastinc = timestamp = 0;
/* We are using timer34 in unchained 32-bit mode, full speed */
__raw_writel(0x0, &regs->tcr);
__raw_writel(0x0, &regs->tgcr);
__raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &regs->tgcr);
__raw_writel(0x0, &regs->tim34);
__raw_writel(TIMER_LOAD_VAL, &regs->prd34);
__raw_writel(2 << 22, &regs->tcr);
return 0;
}
static ulong get_timer_raw(void)
{
ulong now = __raw_readl(&regs->tim34);
if (now >= lastinc)
timestamp += now - lastinc;
else
timestamp += now + TIMER_LOAD_VAL - lastinc;
lastinc = now;
return timestamp;
}
ulong get_timer(ulong base)
{
return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
}
unsigned long long get_ticks(void)
{
return get_timer(0);
}
void __udelay(unsigned long usec)
{
ulong tmo;
ulong endtime;
signed long diff;
tmo = CONFIG_SYS_HZ_CLOCK / 1000;
tmo *= usec;
tmo /= (1000 * TIM_CLK_DIV);
endtime = get_timer_raw() + tmo;
do {
ulong now = get_timer_raw();
diff = endtime - now;
} while (diff >= 0);
}
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}

6
arch/arm/cpu/arm720t/Makefile
View file

@ -7,9 +7,3 @@
extra-y = start.o
obj-y = interrupts.o cpu.o
obj-$(CONFIG_TEGRA) += tegra-common/
obj-$(CONFIG_TEGRA20) += tegra20/
obj-$(CONFIG_TEGRA30) += tegra30/
obj-$(CONFIG_TEGRA114) += tegra114/
obj-$(CONFIG_TEGRA124) += tegra124/

11
arch/arm/cpu/arm720t/tegra-common/Makefile
View file

@ -1,11 +0,0 @@
#
# (C) Copyright 2010,2011 Nvidia Corporation.
#
# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-y += cpu.o

21
arch/arm/cpu/arm720t/tegra114/Makefile
View file

@ -1,21 +0,0 @@
#
# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
#
# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2, as published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#obj-y += cpu.o t11x.o
obj-y += cpu.o

8
arch/arm/cpu/arm720t/tegra124/Makefile
View file

@ -1,8 +0,0 @@
#
# (C) Copyright 2013-2014
# NVIDIA Corporation <www.nvidia.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += cpu.o

10
arch/arm/cpu/arm720t/tegra20/Makefile
View file

@ -1,10 +0,0 @@
#
# (C) Copyright 2010,2011 Nvidia Corporation.
#
# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += cpu.o

20
arch/arm/cpu/arm720t/tegra30/Makefile
View file

@ -1,20 +0,0 @@
#
# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
#
# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2, as published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
obj-y += cpu.o

3
arch/arm/cpu/arm920t/Makefile
View file

@ -10,9 +10,6 @@ extra-y = start.o
obj-y += cpu.o
obj-$(CONFIG_USE_IRQ) += interrupts.o
obj-$(if $(filter a320,$(SOC)),y) += a320/
obj-$(CONFIG_AT91FAMILY) += at91/
obj-$(CONFIG_EP93XX) += ep93xx/
obj-$(CONFIG_IMX) += imx/
obj-$(CONFIG_KS8695) += ks8695/
obj-$(CONFIG_S3C24X0) += s3c24x0/

9
arch/arm/cpu/arm920t/a320/Makefile
View file

@ -1,9 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += reset.o
obj-y += timer.o

10
arch/arm/cpu/arm920t/a320/reset.S
View file

@ -1,10 +0,0 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
.global reset_cpu
reset_cpu:
b reset_cpu

118
arch/arm/cpu/arm920t/a320/timer.c
View file

@ -1,118 +0,0 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <div64.h>
#include <asm/io.h>
#include <faraday/ftpmu010.h>
#include <faraday/fttmr010.h>
DECLARE_GLOBAL_DATA_PTR;
#define TIMER_CLOCK 32768
#define TIMER_LOAD_VAL 0xffffffff
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, gd->arch.timer_rate_hz);
return tick;
}
static inline unsigned long long usec_to_tick(unsigned long long usec)
{
usec *= gd->arch.timer_rate_hz;
do_div(usec, 1000000);
return usec;
}
int timer_init(void)
{
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
unsigned int cr;
debug("%s()\n", __func__);
/* disable timers */
writel(0, &tmr->cr);
/* use 32768Hz oscillator for RTC, WDT, TIMER */
ftpmu010_32768osc_enable();
/* setup timer */
writel(TIMER_LOAD_VAL, &tmr->timer3_load);
writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
writel(0, &tmr->timer3_match1);
writel(0, &tmr->timer3_match2);
/* we don't want timer to issue interrupts */
writel(FTTMR010_TM3_MATCH1 |
FTTMR010_TM3_MATCH2 |
FTTMR010_TM3_OVERFLOW,
&tmr->interrupt_mask);
cr = readl(&tmr->cr);
cr |= FTTMR010_TM3_CLOCK; /* use external clock */
cr |= FTTMR010_TM3_ENABLE;
writel(cr, &tmr->cr);
gd->arch.timer_rate_hz = TIMER_CLOCK;
gd->arch.tbu = gd->arch.tbl = 0;
return 0;
}
/*
* Get the current 64 bit timer tick count
*/
unsigned long long get_ticks(void)
{
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
/* increment tbu if tbl has rolled over */
if (now < gd->arch.tbl)
gd->arch.tbu++;
gd->arch.tbl = now;
return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
}
void __udelay(unsigned long usec)
{
unsigned long long start;
ulong tmo;
start = get_ticks(); /* get current timestamp */
tmo = usec_to_tick(usec); /* convert usecs to ticks */
while ((get_ticks() - start) < tmo)
; /* loop till time has passed */
}
/*
* get_timer(base) can be used to check for timeouts or
* to measure elasped time relative to an event:
*
* ulong start_time = get_timer(0) sets start_time to the current
* time value.
* get_timer(start_time) returns the time elapsed since then.
*
* The time is used in CONFIG_SYS_HZ units!
*/
ulong get_timer(ulong base)
{
return tick_to_time(get_ticks()) - base;
}
/*
* Return the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return gd->arch.timer_rate_hz;
}

9
arch/arm/cpu/arm920t/ks8695/Makefile
View file

@ -1,9 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = lowlevel_init.o
obj-y += timer.o

189
arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
View file

@ -1,189 +0,0 @@
/*
* lowlevel_init.S - basic hardware initialization for the KS8695 CPU
*
* Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <version.h>
#include <asm/arch/platform.h>
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*
*************************************************************************
*
* Handy dandy macros
*
*************************************************************************
*/
/* Delay a bit */
.macro DELAY_FOR cycles, reg0
ldr \reg0, =\cycles
subs \reg0, \reg0, #1
subne pc, pc, #0xc
.endm
/*
*************************************************************************
*
* Some local storage.
*
*************************************************************************
*/
/* Should we boot with an interactive console or not */
.globl serial_console
/*
*************************************************************************
*
* Raw hardware initialization code. The important thing is to get
* SDRAM setup and running. We do some other basic things here too,
* like getting the PLL set for high speed, and init the LEDs.
*
*************************************************************************
*/
.globl lowlevel_init
lowlevel_init:
#if DEBUG
/*
* enable UART for early debug trace
*/
ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
str r2, [r1]
ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
mov r2, #KS8695_UART_LINEC_WLEN8
str r2, [r1] /* 8 data bits, no parity, 1 stop */
ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
mov r2, #0x41
str r2, [r1] /* write 'A' */
#endif
#if DEBUG
ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
mov r2, #0x42
str r2, [r1]
#endif
/*
* remap the memory and flash regions. we want to end up with
* ram from address 0, and flash at 32MB.
*/
ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
ldr r2, =0xbfc00040
str r2, [r1] /* large flash map */
ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */
highflash:
ldr r2, =0x8fe00040
str r2, [r1] /* remap flash range */
/*
* remap the second select region to the 4MB immediately after
* the first region. This way if you have a larger flash (say 8Mb)
* then you can have it all mapped nicely. Has no effect if you
* only have a 4Mb or smaller flash.
*/
ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
ldr r2, =0x9fe40040
str r2, [r1] /* remap flash2 region, contiguous */
ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
ldr r2, =0x30000005
str r2, [r1] /* enable both flash selects */
#ifdef CONFIG_CM41xx
/*
* map the second flash chip, using the external IO lines.
*/
ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
ldr r2, =0xafe80b6d
str r2, [r1] /* remap io0 region, contiguous */
ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
ldr r2, =0xbfec0b6d
str r2, [r1] /* remap io1 region, contiguous */
ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
ldr r2, =0x30050005
str r2, [r1] /* enable second flash */
#endif
/*
* before relocating, we have to setup RAM timing
*/
ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
#if (PHYS_SDRAM_1_SIZE == 0x02000000)
ldr r2, =0x7fc0000e /* 32MB */
#else
ldr r2, =0x3fc0000e /* 16MB */
#endif
str r2, [r1] /* configure sdram bank0 setup */
ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
mov r2, #0
str r2, [r1] /* configure sdram bank1 setup */
ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
ldr r2, =0x0000000a
str r2, [r1] /* set RAS/CAS timing */
ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
ldr r2, =0x00030000
str r2, [r1] /* send NOP command */
DELAY_FOR 0x100, r0
ldr r2, =0x00010000
str r2, [r1] /* send PRECHARGE-ALL */
DELAY_FOR 0x100, r0
ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
ldr r2, =0x00000020
str r2, [r1] /* set for fast refresh */
DELAY_FOR 0x100, r0
ldr r2, =0x00000190
str r2, [r1] /* set normal refresh timing */
ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
ldr r2, =0x00020033
str r2, [r1] /* send mode command */
DELAY_FOR 0x100, r0
ldr r2, =0x01f00000
str r2, [r1] /* enable sdram fifos */
/*
* set pll to top speed
*/
ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
mov r2, #0
str r2, [r1] /* set pll clock to 166MHz */
ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
ldr r2, [r1] /* Get switch ctrl0 register */
and r2, r2, #0x0fc00000 /* Mask out LED control bits */
orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */
str r2, [r1]
#ifdef CONFIG_CM4008
ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
ldr r2, =0x0000fe30
str r2, [r1] /* enable LED's as outputs */
ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
ldr r2, =0x0000fe20
str r2, [r1] /* turn on power LED */
#endif
#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
ldr r2, [r1] /* get current GPIO input data */
tst r2, #0x8 /* check if "erase" depressed */
beq nobutton
mov r2, #0 /* be quiet on boot, no console */
ldr r1, =serial_console
str r2, [r1]
nobutton:
#endif
add lr, lr, #0x02000000 /* flash is now mapped high */
add ip, ip, #0x02000000 /* this is a hack */
mov pc, lr /* all done, return */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

77
arch/arm/cpu/arm920t/ks8695/timer.c
View file

@ -1,77 +0,0 @@
/*
* (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/platform.h>
/*
* Initial timer set constants. Nothing complicated, just set for a 1ms
* tick.
*/
#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1)
#define TIMER_COUNT (TIMER_INTERVAL / 2)
#define TIMER_PULSE TIMER_COUNT
/*
* Handy KS8695 register access functions.
*/
#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a)))
#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
ulong timer_ticks;
int timer_init (void)
{
/* Set the hadware timer for 1ms */
ks8695_write(KS8695_TIMER1, TIMER_COUNT);
ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
ks8695_write(KS8695_TIMER_CTRL, 0x2);
timer_ticks = 0;
return 0;
}
ulong get_timer_masked(void)
{
/* Check for timer wrap */
if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
/* Clear interrupt condition */
ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
timer_ticks++;
}
return timer_ticks;
}
ulong get_timer(ulong base)
{
return (get_timer_masked() - base);
}
void __udelay(ulong usec)
{
ulong start = get_timer_masked();
ulong end;
/* Only 1ms resolution :-( */
end = usec / 1000;
while (get_timer(start) < end)
;
}
void reset_cpu (ulong ignored)
{
ulong tc;
/* Set timer0 to watchdog, and let it timeout */
tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
ks8695_write(KS8695_TIMER_CTRL, tc);
ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
/* Should only wait here till watchdog resets */
for (;;)
;
}

8
arch/arm/cpu/arm926ejs/Makefile
View file

@ -15,16 +15,8 @@ endif
endif
obj-$(CONFIG_ARMADA100) += armada100/
obj-$(CONFIG_AT91FAMILY) += at91/
obj-$(CONFIG_ARCH_DAVINCI) += davinci/
obj-$(CONFIG_KIRKWOOD) += kirkwood/
obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
obj-$(CONFIG_MB86R0x) += mb86r0x/
obj-$(CONFIG_MX25) += mx25/
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
obj-$(CONFIG_ARCH_NOMADIK) += nomadik/
obj-$(CONFIG_ORION5X) += orion5x/
obj-$(CONFIG_PANTHEON) += pantheon/
obj-$(if $(filter spear,$(SOC)),y) += spear/
obj-$(CONFIG_ARCH_VERSATILE) += versatile/

2
arch/arm/cpu/arm926ejs/at91/config.mk
View file

@ -1,2 +0,0 @@
PF_CPPFLAGS_TUNE := $(call cc-option,-mtune=arm926ejs,)
PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_TUNE)

8
arch/arm/cpu/arm926ejs/mb86r0x/Makefile
View file

@ -1,8 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = clock.o reset.o timer.o

27
arch/arm/cpu/arm926ejs/mb86r0x/clock.c
View file

@ -1,27 +0,0 @@
/*
* (C) Copyright 2010
* Matthias Weisser <weisserm@arcor.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
/*
* Get the peripheral bus frequency depending on pll pin settings
*/
ulong get_bus_freq(ulong dummy)
{
struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
MB86R0x_CRG_BASE;
uint32_t pllmode;
pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE;
if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20)
return 40000000;
return 41164767;
}

24
arch/arm/cpu/arm926ejs/mb86r0x/reset.c
View file

@ -1,24 +0,0 @@
/*
* (C) Copyright 2010
* Matthias Weisser <weisserm@arcor.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
/*
* Reset the cpu by setting software reset request bit
*/
void reset_cpu(ulong ignored)
{
struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
MB86R0x_CRG_BASE;
writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr);
while (1)
/* NOP */;
/* Never reached */
}

115
arch/arm/cpu/arm926ejs/mb86r0x/timer.c
View file

@ -1,115 +0,0 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2010
* Matthias Weisser, Graf-Syteco <weisserm@arcor.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <div64.h>
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#define TIMER_LOAD_VAL 0xffffffff
#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256)
DECLARE_GLOBAL_DATA_PTR;
#define timestamp gd->arch.tbl
#define lastdec gd->arch.lastinc
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, TIMER_FREQ);
return tick;
}
static inline unsigned long long usec_to_tick(unsigned long long usec)
{
usec *= TIMER_FREQ;
do_div(usec, 1000000);
return usec;
}
/* nothing really to do with interrupts, just starts up a counter. */
int timer_init(void)
{
struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
MB86R0x_TIMER_BASE;
ulong ctrl = readl(&timer->control);
writel(TIMER_LOAD_VAL, &timer->load);
ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S |
MB86R0x_TIMER_SIZE_32;
writel(ctrl, &timer->control);
/* capture current value time */
lastdec = readl(&timer->value);
timestamp = 0; /* start "advancing" time stamp from 0 */
return 0;
}
/*
* timer without interrupts
*/
unsigned long long get_ticks(void)
{
struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
MB86R0x_TIMER_BASE;
ulong now = readl(&timer->value);
if (now <= lastdec) {
/* normal mode (non roll) */
/* move stamp forward with absolut diff ticks */
timestamp += lastdec - now;
} else {
/* we have rollover of incrementer */
timestamp += lastdec + TIMER_LOAD_VAL - now;
}
lastdec = now;
return timestamp;
}
ulong get_timer_masked(void)
{
return tick_to_time(get_ticks());
}
void __udelay(unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
tmo = usec_to_tick(usec);
tmp = get_ticks(); /* get current timestamp */
while ((get_ticks() - tmp) < tmo) /* loop till event */
/*NOP*/;
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
ulong tbclk;
tbclk = TIMER_FREQ;
return tbclk;
}

9
arch/arm/cpu/arm926ejs/pantheon/Makefile
View file

@ -1,9 +0,0 @@
#
# (C) Copyright 2011
# Marvell Semiconductor <www.marvell.com>
# Written-by: Lei Wen <leiwen@marvell.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = cpu.o timer.o dram.o

85
arch/arm/cpu/arm926ejs/pantheon/cpu.c
View file

@ -1,85 +0,0 @@
/*
* (C) Copyright 2011
* Marvell Semiconductor <www.marvell.com>
* Written-by: Lei Wen <leiwen@marvell.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/pantheon.h>
#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
#define SET_MRVL_ID (1<<8)
#define L2C_RAM_SEL (1<<4)
int arch_cpu_init(void)
{
u32 val;
struct panthcpu_registers *cpuregs =
(struct panthcpu_registers*) PANTHEON_CPU_BASE;
struct panthapb_registers *apbclkres =
(struct panthapb_registers*) PANTHEON_APBC_BASE;
struct panthmpmu_registers *mpmu =
(struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
struct panthapmu_registers *apmu =
(struct panthapmu_registers *) PANTHEON_APMU_BASE;
/* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
val = readl(&cpuregs->cpu_conf);
val = val | SET_MRVL_ID;
writel(val, &cpuregs->cpu_conf);
/* Turn on clock gating (PMUM_CCGR) */
writel(0xFFFFFFFF, &mpmu->ccgr);
/* Turn on clock gating (PMUM_ACGR) */
writel(0xFFFFFFFF, &mpmu->acgr);
/* Turn on uart2 clock */
writel(UARTCLK14745KHZ, &apbclkres->uart0);
/* Enable GPIO clock */
writel(APBC_APBCLK, &apbclkres->gpio);
#ifdef CONFIG_I2C_MV
/* Enable I2C clock */
writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
#endif
#ifdef CONFIG_MV_SDHCI
/* Enable mmc clock */
writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
&apmu->sd1);
writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
&apmu->sd3);
#endif
icache_enable();
return 0;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
u32 id;
struct panthcpu_registers *cpuregs =
(struct panthcpu_registers*) PANTHEON_CPU_BASE;
id = readl(&cpuregs->chip_id);
printf("SoC: PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
return 0;
}
#endif
#ifdef CONFIG_I2C_MV
void i2c_clk_enable(void)
{
}
#endif

117
arch/arm/cpu/arm926ejs/pantheon/dram.c
View file

@ -1,117 +0,0 @@
/*
* (C) Copyright 2011
* Marvell Semiconductor <www.marvell.com>
* Written-by: Lei Wen <leiwen@marvell.com>,
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/pantheon.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Pantheon DRAM controller supports upto 8 banks
* for chip select 0 and 1
*/
/*
* DDR Memory Control Registers
* Refer Datasheet 4.4
*/
struct panthddr_map_registers {
u32 cs; /* Memory Address Map Register -CS */
u32 pad[3];
};
struct panthddr_registers {
u8 pad[0x100 - 0x000];
struct panthddr_map_registers mmap[2];
};
/*
* panth_sdram_base - reads SDRAM Base Address Register
*/
u32 panth_sdram_base(int chip_sel)
{
struct panthddr_registers *ddr_regs =
(struct panthddr_registers *)PANTHEON_DRAM_BASE;
u32 result = 0;
u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
if (!CS_valid)
return 0;
result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
return result;
}
/*
* panth_sdram_size - reads SDRAM size
*/
u32 panth_sdram_size(int chip_sel)
{
struct panthddr_registers *ddr_regs =
(struct panthddr_registers *)PANTHEON_DRAM_BASE;
u32 result = 0;
u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
if (!CS_valid)
return 0;
result = readl(&ddr_regs->mmap[chip_sel].cs);
result = (result >> 16) & 0xF;
if (result < 0x7) {
printf("Unknown DRAM Size\n");
return -1;
} else {
return ((0x8 << (result - 0x7)) * 1024 * 1024);
}
}
#ifndef CONFIG_SYS_BOARD_DRAM_INIT
int dram_init(void)
{
int i;
gd->ram_size = 0;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = panth_sdram_base(i);
gd->bd->bi_dram[i].size = panth_sdram_size(i);
/*
* It is assumed that all memory banks are consecutive
* and without gaps.
* If the gap is found, ram_size will be reported for
* consecutive memory only
*/
if (gd->bd->bi_dram[i].start != gd->ram_size)
break;
gd->ram_size += gd->bd->bi_dram[i].size;
}
for (; i < CONFIG_NR_DRAM_BANKS; i++) {
/*
* If above loop terminated prematurely, we need to set
* remaining banks' start address & size as 0. Otherwise other
* u-boot functions and Linux kernel gets wrong values which
* could result in crash
*/
gd->bd->bi_dram[i].start = 0;
gd->bd->bi_dram[i].size = 0;
}
return 0;
}
/*
* If this function is not defined here,
* board.c alters dram bank zero configuration defined above.
*/
void dram_init_banksize(void)
{
dram_init();
}
#endif /* CONFIG_SYS_BOARD_DRAM_INIT */

201
arch/arm/cpu/arm926ejs/pantheon/timer.c
View file

@ -1,201 +0,0 @@
/*
* (C) Copyright 2011
* Marvell Semiconductor <www.marvell.com>
* Written-by: Lei Wen <leiwen@marvell.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/pantheon.h>
/*
* Timer registers
* Refer 6.2.9 in Datasheet
*/
struct panthtmr_registers {
u32 clk_ctrl; /* Timer clk control reg */
u32 match[9]; /* Timer match registers */
u32 count[3]; /* Timer count registers */
u32 status[3];
u32 ie[3];
u32 preload[3]; /* Timer preload value */
u32 preload_ctrl[3];
u32 wdt_match_en;
u32 wdt_match_r;
u32 wdt_val;
u32 wdt_sts;
u32 icr[3];
u32 wdt_icr;
u32 cer; /* Timer count enable reg */
u32 cmr;
u32 ilr[3];
u32 wcr;
u32 wfar;
u32 wsar;
u32 cvwr[3];
};
#define TIMER 0 /* Use TIMER 0 */
/* Each timer has 3 match registers */
#define MATCH_CMP(x) ((3 * TIMER) + x)
#define TIMER_LOAD_VAL 0xffffffff
#define COUNT_RD_REQ 0x1
DECLARE_GLOBAL_DATA_PTR;
/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
/*
* For preventing risk of instability in reading counter value,
* first set read request to register cvwr and then read same
* register after it captures counter value.
*/
ulong read_timer(void)
{
struct panthtmr_registers *panthtimers =
(struct panthtmr_registers *) PANTHEON_TIMER_BASE;
volatile int loop=100;
ulong val;
writel(COUNT_RD_REQ, &panthtimers->cvwr);
while (loop--)
val = readl(&panthtimers->cvwr);
/*
* This stop gcc complain and prevent loop mistake init to 0
*/
val = readl(&panthtimers->cvwr);
return val;
}
ulong get_timer_masked(void)
{
ulong now = read_timer();
if (now >= gd->arch.tbl) {
/* normal mode */
gd->arch.tbu += now - gd->arch.tbl;
} else {
/* we have an overflow ... */
gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
}
gd->arch.tbl = now;
return gd->arch.tbu;
}
ulong get_timer(ulong base)
{
return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
base);
}
void __udelay(unsigned long usec)
{
ulong delayticks;
ulong endtime;
delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
endtime = get_timer_masked() + delayticks;
while (get_timer_masked() < endtime)
;
}
/*
* init the Timer
*/
int timer_init(void)
{
struct panthapb_registers *apb1clkres =
(struct panthapb_registers *) PANTHEON_APBC_BASE;
struct panthtmr_registers *panthtimers =
(struct panthtmr_registers *) PANTHEON_TIMER_BASE;
/* Enable Timer clock at 3.25 MHZ */
writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
/* load value into timer */
writel(0x0, &panthtimers->clk_ctrl);
/* Use Timer 0 Match Resiger 0 */
writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
/* Preload value is 0 */
writel(0x0, &panthtimers->preload[TIMER]);
/* Enable match comparator 0 for Timer 0 */
writel(0x1, &panthtimers->preload_ctrl[TIMER]);
/* Enable timer 0 */
writel(0x1, &panthtimers->cer);
/* init the gd->arch.tbu and gd->arch.tbl value */
gd->arch.tbl = read_timer();
gd->arch.tbu = 0;
return 0;
}
#define MPMU_APRR_WDTR (1<<4)
#define TMR_WFAR 0xbaba /* WDT Register First key */
#define TMP_WSAR 0xeb10 /* WDT Register Second key */
/*
* This function uses internal Watchdog Timer
* based reset mechanism.
* Steps to write watchdog registers (protected access)
* 1. Write key value to TMR_WFAR reg.
* 2. Write key value to TMP_WSAR reg.
* 3. Perform write operation.
*/
void reset_cpu (unsigned long ignored)
{
struct panthmpmu_registers *mpmu =
(struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
struct panthtmr_registers *panthtimers =
(struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
u32 val;
/* negate hardware reset to the WDT after system reset */
val = readl(&mpmu->aprr);
val = val | MPMU_APRR_WDTR;
writel(val, &mpmu->aprr);
/* reset/enable WDT clock */
writel(APBC_APBCLK, &mpmu->wdtpcr);
/* clear previous WDT status */
writel(TMR_WFAR, &panthtimers->wfar);
writel(TMP_WSAR, &panthtimers->wsar);
writel(0, &panthtimers->wdt_sts);
/* set match counter */
writel(TMR_WFAR, &panthtimers->wfar);
writel(TMP_WSAR, &panthtimers->wsar);
writel(0xf, &panthtimers->wdt_match_r);
/* enable WDT reset */
writel(TMR_WFAR, &panthtimers->wfar);
writel(TMP_WSAR, &panthtimers->wsar);
writel(0x3, &panthtimers->wdt_match_en);
/*enable functional WDT clock */
writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk (void)
{
return (ulong)CONFIG_SYS_HZ;
}

6
arch/arm/cpu/armv7/Makefile
View file

@ -32,7 +32,6 @@ obj-$(CONFIG_IPROC) += iproc-common/
obj-$(CONFIG_KONA) += kona-common/
obj-$(CONFIG_OMAP_COMMON) += omap-common/
obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
obj-$(CONFIG_TEGRA) += tegra-common/
ifneq (,$(filter s5pc1xx exynos,$(SOC)))
obj-y += s5p-common/
@ -40,13 +39,11 @@ endif
obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
obj-$(CONFIG_AT91FAMILY) += at91/
obj-$(CONFIG_BCM2835) += bcm2835/
obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
obj-$(CONFIG_ARCH_EXYNOS) += exynos/
obj-$(CONFIG_ARCH_HIGHBANK) += highbank/
obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
obj-$(if $(filter mx5,$(SOC)),y) += mx5/
obj-$(CONFIG_MX6) += mx6/
@ -58,7 +55,6 @@ obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
obj-$(CONFIG_SOCFPGA) += socfpga/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_TEGRA20) += tegra20/
obj-$(CONFIG_U8500) += u8500/
obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
obj-$(CONFIG_VF610) += vf610/

3
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
View file

@ -118,4 +118,7 @@ void enable_basic_clocks(void)
/* Select the Master osc clk as Timer2 clock source */
writel(0x1, &cmdpll->clktimer2clk);
/* For OPP100 the mac clock should be /5. */
writel(0x4, &cmdpll->clkselmacclk);
}

8
arch/arm/cpu/armv7/at91/config.mk
View file

@ -1,8 +0,0 @@
#
# Copyright (C) 2014, Andreas Bießmann <andreas.devel@googlemail.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
ifndef CONFIG_SPL_BUILD
ALL-y += u-boot.img
endif

13
arch/arm/cpu/armv7/bcm2835/Makefile Normal file
View file

@ -0,0 +1,13 @@
#
# (C) Copyright 2012 Stephen Warren
#
# SPDX-License-Identifier: GPL-2.0+
#
src_dir := ../../arm1176/bcm2835/
obj-y :=
obj-y += $(src_dir)/init.o
obj-y += $(src_dir)/reset.o
obj-y += $(src_dir)/timer.o
obj-y += $(src_dir)/mbox.o

35
arch/arm/cpu/armv7/exynos/Kconfig
View file

@ -6,7 +6,7 @@ choice
config TARGET_SMDKV310
select SUPPORT_SPL
bool "Exynos4210 SMDKV310 board"
select OF_CONTROL if !SPL_BUILD
select OF_CONTROL
config TARGET_TRATS
bool "Exynos4210 Trats board"
@ -33,38 +33,59 @@ config TARGET_ARNDALE
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
select OF_CONTROL
config TARGET_SMDK5250
bool "SMDK5250 board"
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
select OF_CONTROL
config TARGET_SNOW
bool "Snow board"
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
select OF_CONTROL
config TARGET_SMDK5420
bool "SMDK5420 board"
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
select OF_CONTROL
config TARGET_PEACH_PI
bool "Peach Pi board"
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
select OF_CONTROL
config TARGET_PEACH_PIT
bool "Peach Pit board"
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
select OF_CONTROL
endchoice
config SYS_SOC
default "exynos"
config DM
default y
config DM_SERIAL
default y
config DM_SPI
default y
config DM_SPI_FLASH
default y
config DM_GPIO
default y
config SYS_MALLOC_F
default y
config SYS_MALLOC_F_LEN
default 0x400
source "board/samsung/smdkv310/Kconfig"
source "board/samsung/trats/Kconfig"
source "board/samsung/universal_c210/Kconfig"

721
arch/arm/cpu/armv7/exynos/clock.c
View file

@ -20,42 +20,84 @@
* positions of the peripheral clocks of the src and div registers
*/
struct clk_bit_info {
enum periph_id id;
int32_t src_mask;
int32_t div_mask;
int32_t prediv_mask;
int8_t src_bit;
int8_t div_bit;
int8_t prediv_bit;
};
/* src_bit div_bit prediv_bit */
static struct clk_bit_info clk_bit_info[] = {
{0, 0, -1},
{4, 4, -1},
{8, 8, -1},
{12, 12, -1},
{0, 0, 8},
{4, 16, 24},
{8, 0, 8},
{12, 16, 24},
{-1, -1, -1},
{16, 0, 8},
{20, 16, 24},
{24, 0, 8},
{0, 0, 4},
{4, 12, 16},
{-1, -1, -1},
{-1, -1, -1},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{24, 0, -1},
{24, 0, -1},
{24, 0, -1},
{24, 0, -1},
{24, 0, -1},
static struct clk_bit_info exynos5_bit_info[] = {
/* periph id s_mask d_mask p_mask s_bit d_bit p_bit */
{PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1},
{PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1},
{PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1},
{PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1},
{PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0},
{PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0},
{PERIPH_ID_I2C2, -1, 0x7, 0x7, -1, 24, 0},
{PERIPH_ID_I2C3, -1, 0x7, 0x7, -1, 24, 0},
{PERIPH_ID_I2C4, -1, 0x7, 0x7, -1, 24, 0},
{PERIPH_ID_I2C5, -1, 0x7, 0x7, -1, 24, 0},
{PERIPH_ID_I2C6, -1, 0x7, 0x7, -1, 24, 0},
{PERIPH_ID_I2C7, -1, 0x7, 0x7, -1, 24, 0},
{PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 16, 0, 8},
{PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 20, 16, 24},
{PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 24, 0, 8},
{PERIPH_ID_SDMMC0, 0xf, 0xf, 0xff, 0, 0, 8},
{PERIPH_ID_SDMMC1, 0xf, 0xf, 0xff, 4, 16, 24},
{PERIPH_ID_SDMMC2, 0xf, 0xf, 0xff, 8, 0, 8},
{PERIPH_ID_SDMMC3, 0xf, 0xf, 0xff, 12, 16, 24},
{PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4},
{PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16},
{PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 0, 0, 4},
{PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 4, 12, 16},
{PERIPH_ID_SDMMC4, 0xf, 0xf, 0xff, 16, 0, 8},
{PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 0, -1},
{PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 0, -1},
{PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 0, -1},
{PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 0, -1},
{PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 0, -1},
{PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1},
};
static struct clk_bit_info exynos542x_bit_info[] = {
/* periph id s_mask d_mask p_mask s_bit d_bit p_bit */
{PERIPH_ID_UART0, 0xf, 0xf, -1, 4, 8, -1},
{PERIPH_ID_UART1, 0xf, 0xf, -1, 8, 12, -1},
{PERIPH_ID_UART2, 0xf, 0xf, -1, 12, 16, -1},
{PERIPH_ID_UART3, 0xf, 0xf, -1, 16, 20, -1},
{PERIPH_ID_I2C0, -1, 0x3f, -1, -1, 8, -1},
{PERIPH_ID_I2C1, -1, 0x3f, -1, -1, 8, -1},
{PERIPH_ID_I2C2, -1, 0x3f, -1, -1, 8, -1},
{PERIPH_ID_I2C3, -1, 0x3f, -1, -1, 8, -1},
{PERIPH_ID_I2C4, -1, 0x3f, -1, -1, 8, -1},
{PERIPH_ID_I2C5, -1, 0x3f, -1, -1, 8, -1},
{PERIPH_ID_I2C6, -1, 0x3f, -1, -1, 8, -1},
{PERIPH_ID_I2C7, -1, 0x3f, -1, -1, 8, -1},
{PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 20, 20, 8},
{PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 24, 24, 16},
{PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 28, 28, 24},
{PERIPH_ID_SDMMC0, 0x7, 0x3ff, -1, 8, 0, -1},
{PERIPH_ID_SDMMC1, 0x7, 0x3ff, -1, 12, 10, -1},
{PERIPH_ID_SDMMC2, 0x7, 0x3ff, -1, 16, 20, -1},
{PERIPH_ID_I2C8, -1, 0x3f, -1, -1, 8, -1},
{PERIPH_ID_I2C9, -1, 0x3f, -1, -1, 8, -1},
{PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4},
{PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16},
{PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 12, 16, 0},
{PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 16, 20, 8},
{PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 28, -1},
{PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 28, -1},
{PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 28, -1},
{PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 28, -1},
{PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 28, -1},
{PERIPH_ID_I2C10, -1, 0x3f, -1, -1, 8, -1},
{PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1},
};
/* Epll Clock division values to achive different frequency output */
@ -260,112 +302,8 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
return fout;
}
static unsigned long exynos5_get_periph_rate(int peripheral)
{
struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
unsigned long sclk, sub_clk;
unsigned int src, div, sub_div;
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
switch (peripheral) {
case PERIPH_ID_UART0:
case PERIPH_ID_UART1:
case PERIPH_ID_UART2:
case PERIPH_ID_UART3:
src = readl(&clk->src_peric0);
div = readl(&clk->div_peric0);
break;
case PERIPH_ID_PWM0:
case PERIPH_ID_PWM1:
case PERIPH_ID_PWM2:
case PERIPH_ID_PWM3:
case PERIPH_ID_PWM4:
src = readl(&clk->src_peric0);
div = readl(&clk->div_peric3);
break;
case PERIPH_ID_I2S0:
src = readl(&clk->src_mau);
div = readl(&clk->div_mau);
case PERIPH_ID_SPI0:
case PERIPH_ID_SPI1:
src = readl(&clk->src_peric1);
div = readl(&clk->div_peric1);
break;
case PERIPH_ID_SPI2:
src = readl(&clk->src_peric1);
div = readl(&clk->div_peric2);
break;
case PERIPH_ID_SPI3:
case PERIPH_ID_SPI4:
src = readl(&clk->sclk_src_isp);
div = readl(&clk->sclk_div_isp);
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC2:
case PERIPH_ID_SDMMC3:
src = readl(&clk->src_fsys);
div = readl(&clk->div_fsys1);
break;
case PERIPH_ID_I2C0:
case PERIPH_ID_I2C1:
case PERIPH_ID_I2C2:
case PERIPH_ID_I2C3:
case PERIPH_ID_I2C4:
case PERIPH_ID_I2C5:
case PERIPH_ID_I2C6:
case PERIPH_ID_I2C7:
sclk = exynos5_get_pll_clk(MPLL);
sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
& 0x7) + 1;
div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
& 0x7) + 1;
return (sclk / sub_div) / div;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
};
src = (src >> bit_info->src_bit) & 0xf;
switch (src) {
case EXYNOS_SRC_MPLL:
sclk = exynos5_get_pll_clk(MPLL);
break;
case EXYNOS_SRC_EPLL:
sclk = exynos5_get_pll_clk(EPLL);
break;
case EXYNOS_SRC_VPLL:
sclk = exynos5_get_pll_clk(VPLL);
break;
default:
return 0;
}
/* Ratio clock division for this peripheral */
sub_div = (div >> bit_info->div_bit) & 0xf;
sub_clk = sclk / (sub_div + 1);
/* Pre-ratio clock division for SDMMC0 and 2 */
if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
div = (div >> bit_info->prediv_bit) & 0xff;
return sub_clk / (div + 1);
}
return sub_clk;
}
unsigned long clock_get_periph_rate(int peripheral)
{
if (cpu_is_exynos5())
return exynos5_get_periph_rate(peripheral);
else
return 0;
}
/* exynos5420: return pll clock frequency */
static unsigned long exynos5420_get_pll_clk(int pllreg)
/* exynos542x: return pll clock frequency */
static unsigned long exynos542x_get_pll_clk(int pllreg)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
@ -404,6 +342,231 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
return exynos_get_pll_clk(pllreg, r, k);
}
static struct clk_bit_info *get_clk_bit_info(int peripheral)
{
int i;
struct clk_bit_info *info;
if (proid_is_exynos5420() || proid_is_exynos5800())
info = exynos542x_bit_info;
else
info = exynos5_bit_info;
for (i = 0; info[i].id != PERIPH_ID_NONE; i++) {
if (info[i].id == peripheral)
break;
}
if (info[i].id == PERIPH_ID_NONE)
debug("ERROR: Peripheral ID %d not found\n", peripheral);
return &info[i];
}
static unsigned long exynos5_get_periph_rate(int peripheral)
{
struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
unsigned long sclk = 0;
unsigned int src = 0, div = 0, sub_div = 0;
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
switch (peripheral) {
case PERIPH_ID_UART0:
case PERIPH_ID_UART1:
case PERIPH_ID_UART2:
case PERIPH_ID_UART3:
src = readl(&clk->src_peric0);
div = readl(&clk->div_peric0);
break;
case PERIPH_ID_PWM0:
case PERIPH_ID_PWM1:
case PERIPH_ID_PWM2:
case PERIPH_ID_PWM3:
case PERIPH_ID_PWM4:
src = readl(&clk->src_peric0);
div = readl(&clk->div_peric3);
break;
case PERIPH_ID_I2S0:
src = readl(&clk->src_mau);
div = sub_div = readl(&clk->div_mau);
case PERIPH_ID_SPI0:
case PERIPH_ID_SPI1:
src = readl(&clk->src_peric1);
div = sub_div = readl(&clk->div_peric1);
break;
case PERIPH_ID_SPI2:
src = readl(&clk->src_peric1);
div = sub_div = readl(&clk->div_peric2);
break;
case PERIPH_ID_SPI3:
case PERIPH_ID_SPI4:
src = readl(&clk->sclk_src_isp);
div = sub_div = readl(&clk->sclk_div_isp);
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC1:
src = readl(&clk->src_fsys);
div = sub_div = readl(&clk->div_fsys1);
break;
case PERIPH_ID_SDMMC2:
case PERIPH_ID_SDMMC3:
src = readl(&clk->src_fsys);
div = sub_div = readl(&clk->div_fsys2);
break;
case PERIPH_ID_I2C0:
case PERIPH_ID_I2C1:
case PERIPH_ID_I2C2:
case PERIPH_ID_I2C3:
case PERIPH_ID_I2C4:
case PERIPH_ID_I2C5:
case PERIPH_ID_I2C6:
case PERIPH_ID_I2C7:
src = EXYNOS_SRC_MPLL;
div = readl(&clk->div_top0);
sub_div = readl(&clk->div_top1);
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
};
if (bit_info->src_bit >= 0)
src = (src >> bit_info->src_bit) & bit_info->src_mask;
switch (src) {
case EXYNOS_SRC_MPLL:
sclk = exynos5_get_pll_clk(MPLL);
break;
case EXYNOS_SRC_EPLL:
sclk = exynos5_get_pll_clk(EPLL);
break;
case EXYNOS_SRC_VPLL:
sclk = exynos5_get_pll_clk(VPLL);
break;
default:
debug("%s: EXYNOS_SRC %d not supported\n", __func__, src);
return 0;
}
/* Clock divider ratio for this peripheral */
if (bit_info->div_bit >= 0)
div = (div >> bit_info->div_bit) & bit_info->div_mask;
/* Clock pre-divider ratio for this peripheral */
if (bit_info->prediv_bit >= 0)
sub_div = (sub_div >> bit_info->prediv_bit)
& bit_info->prediv_mask;
/* Calculate and return required clock rate */
return (sclk / (div + 1)) / (sub_div + 1);
}
static unsigned long exynos542x_get_periph_rate(int peripheral)
{
struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
unsigned long sclk = 0;
unsigned int src = 0, div = 0, sub_div = 0;
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
switch (peripheral) {
case PERIPH_ID_UART0:
case PERIPH_ID_UART1:
case PERIPH_ID_UART2:
case PERIPH_ID_UART3:
case PERIPH_ID_PWM0:
case PERIPH_ID_PWM1:
case PERIPH_ID_PWM2:
case PERIPH_ID_PWM3:
case PERIPH_ID_PWM4:
src = readl(&clk->src_peric0);
div = readl(&clk->div_peric0);
break;
case PERIPH_ID_SPI0:
case PERIPH_ID_SPI1:
case PERIPH_ID_SPI2:
src = readl(&clk->src_peric1);
div = readl(&clk->div_peric1);
sub_div = readl(&clk->div_peric4);
break;
case PERIPH_ID_SPI3:
case PERIPH_ID_SPI4:
src = readl(&clk->src_isp);
div = readl(&clk->div_isp1);
sub_div = readl(&clk->div_isp1);
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC2:
case PERIPH_ID_SDMMC3:
src = readl(&clk->src_fsys);
div = readl(&clk->div_fsys1);
break;
case PERIPH_ID_I2C0:
case PERIPH_ID_I2C1:
case PERIPH_ID_I2C2:
case PERIPH_ID_I2C3:
case PERIPH_ID_I2C4:
case PERIPH_ID_I2C5:
case PERIPH_ID_I2C6:
case PERIPH_ID_I2C7:
case PERIPH_ID_I2C8:
case PERIPH_ID_I2C9:
case PERIPH_ID_I2C10:
src = EXYNOS542X_SRC_MPLL;
div = readl(&clk->div_top1);
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
};
if (bit_info->src_bit >= 0)
src = (src >> bit_info->src_bit) & bit_info->src_mask;
switch (src) {
case EXYNOS542X_SRC_MPLL:
sclk = exynos542x_get_pll_clk(MPLL);
break;
case EXYNOS542X_SRC_SPLL:
sclk = exynos542x_get_pll_clk(SPLL);
break;
case EXYNOS542X_SRC_EPLL:
sclk = exynos542x_get_pll_clk(EPLL);
break;
case EXYNOS542X_SRC_RPLL:
sclk = exynos542x_get_pll_clk(RPLL);
break;
default:
debug("%s: EXYNOS542X_SRC %d not supported", __func__, src);
return 0;
}
/* Clock divider ratio for this peripheral */
if (bit_info->div_bit >= 0)
div = (div >> bit_info->div_bit) & bit_info->div_mask;
/* Clock pre-divider ratio for this peripheral */
if (bit_info->prediv_bit >= 0)
sub_div = (sub_div >> bit_info->prediv_bit)
& bit_info->prediv_mask;
/* Calculate and return required clock rate */
return (sclk / (div + 1)) / (sub_div + 1);
}
unsigned long clock_get_periph_rate(int peripheral)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos542x_get_periph_rate(peripheral);
return exynos5_get_periph_rate(peripheral);
} else {
return 0;
}
}
/* exynos4: return ARM clock frequency */
static unsigned long exynos4_get_arm_clk(void)
{
@ -527,27 +690,6 @@ static unsigned long exynos4x12_get_pwm_clk(void)
return pclk;
}
/* exynos5420: return pwm clock frequency */
static unsigned long exynos5420_get_pwm_clk(void)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned long pclk, sclk;
unsigned int ratio;
/*
* CLK_DIV_PERIC0
* PWM_RATIO [31:28]
*/
ratio = readl(&clk->div_peric0);
ratio = (ratio >> 28) & 0xf;
sclk = get_pll_clk(MPLL);
pclk = sclk / (ratio + 1);
return pclk;
}
/* exynos4: return uart clock frequency */
static unsigned long exynos4_get_uart_clk(int dev_index)
{
@ -640,100 +782,6 @@ static unsigned long exynos4x12_get_uart_clk(int dev_index)
return uclk;
}
/* exynos5: return uart clock frequency */
static unsigned long exynos5_get_uart_clk(int dev_index)
{
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long uclk, sclk;
unsigned int sel;
unsigned int ratio;
/*
* CLK_SRC_PERIC0
* UART0_SEL [3:0]
* UART1_SEL [7:4]
* UART2_SEL [8:11]
* UART3_SEL [12:15]
* UART4_SEL [16:19]
* UART5_SEL [23:20]
*/
sel = readl(&clk->src_peric0);
sel = (sel >> (dev_index << 2)) & 0xf;
if (sel == 0x6)
sclk = get_pll_clk(MPLL);
else if (sel == 0x7)
sclk = get_pll_clk(EPLL);
else if (sel == 0x8)
sclk = get_pll_clk(VPLL);
else
return 0;
/*
* CLK_DIV_PERIC0
* UART0_RATIO [3:0]
* UART1_RATIO [7:4]
* UART2_RATIO [8:11]
* UART3_RATIO [12:15]
* UART4_RATIO [16:19]
* UART5_RATIO [23:20]
*/
ratio = readl(&clk->div_peric0);
ratio = (ratio >> (dev_index << 2)) & 0xf;
uclk = sclk / (ratio + 1);
return uclk;
}
/* exynos5420: return uart clock frequency */
static unsigned long exynos5420_get_uart_clk(int dev_index)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned long uclk, sclk;
unsigned int sel;
unsigned int ratio;
/*
* CLK_SRC_PERIC0
* UART0_SEL [6:4]
* UART1_SEL [10:8]
* UART2_SEL [14:12]
* UART3_SEL [18:16]
* generalised calculation as follows
* sel = (sel >> ((dev_index * 4) + 4)) & mask;
*/
sel = readl(&clk->src_peric0);
sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
if (sel == 0x3)
sclk = get_pll_clk(MPLL);
else if (sel == 0x6)
sclk = get_pll_clk(EPLL);
else if (sel == 0x7)
sclk = get_pll_clk(RPLL);
else
return 0;
/*
* CLK_DIV_PERIC0
* UART0_RATIO [11:8]
* UART1_RATIO [15:12]
* UART2_RATIO [19:16]
* UART3_RATIO [23:20]
* generalised calculation as follows
* ratio = (ratio >> ((dev_index * 4) + 8)) & mask;
*/
ratio = readl(&clk->div_peric0);
ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
uclk = sclk / (ratio + 1);
return uclk;
}
static unsigned long exynos4_get_mmc_clk(int dev_index)
{
struct exynos4_clock *clk =
@ -783,94 +831,6 @@ static unsigned long exynos4_get_mmc_clk(int dev_index)
return uclk;
}
static unsigned long exynos5_get_mmc_clk(int dev_index)
{
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long uclk, sclk;
unsigned int sel, ratio, pre_ratio;
int shift = 0;
sel = readl(&clk->src_fsys);
sel = (sel >> (dev_index << 2)) & 0xf;
if (sel == 0x6)
sclk = get_pll_clk(MPLL);
else if (sel == 0x7)
sclk = get_pll_clk(EPLL);
else if (sel == 0x8)
sclk = get_pll_clk(VPLL);
else
return 0;
switch (dev_index) {
case 0:
case 1:
ratio = readl(&clk->div_fsys1);
pre_ratio = readl(&clk->div_fsys1);
break;
case 2:
case 3:
ratio = readl(&clk->div_fsys2);
pre_ratio = readl(&clk->div_fsys2);
break;
default:
return 0;
}
if (dev_index == 1 || dev_index == 3)
shift = 16;
ratio = (ratio >> shift) & 0xf;
pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
return uclk;
}
static unsigned long exynos5420_get_mmc_clk(int dev_index)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned long uclk, sclk;
unsigned int sel, ratio;
/*
* CLK_SRC_FSYS
* MMC0_SEL [10:8]
* MMC1_SEL [14:12]
* MMC2_SEL [18:16]
* generalised calculation as follows
* sel = (sel >> ((dev_index * 4) + 8)) & mask
*/
sel = readl(&clk->src_fsys);
sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
if (sel == 0x3)
sclk = get_pll_clk(MPLL);
else if (sel == 0x4)
sclk = get_pll_clk(SPLL);
else if (sel == 0x6)
sclk = get_pll_clk(EPLL);
else
return 0;
/*
* CLK_DIV_FSYS1
* MMC0_RATIO [9:0]
* MMC1_RATIO [19:10]
* MMC2_RATIO [29:20]
* generalised calculation as follows
* ratio = (ratio >> (dev_index * 10)) & mask
*/
ratio = readl(&clk->div_fsys1);
ratio = (ratio >> (dev_index * 10)) & 0x3ff;
uclk = (sclk / (ratio + 1));
return uclk;
}
/* exynos4: set the mmc clock */
static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
{
@ -1249,29 +1209,6 @@ void exynos4_set_mipi_clk(void)
clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
}
/*
* I2C
*
* exynos5: obtaining the I2C clock
*/
static unsigned long exynos5_get_i2c_clk(void)
{
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long aclk_66, aclk_66_pre, sclk;
unsigned int ratio;
sclk = get_pll_clk(MPLL);
ratio = (readl(&clk->div_top1)) >> 24;
ratio &= 0x7;
aclk_66_pre = sclk / (ratio + 1);
ratio = readl(&clk->div_top0);
ratio &= 0x7;
aclk_66 = aclk_66_pre / (ratio + 1);
return aclk_66;
}
int exynos5_set_epll_clk(unsigned long rate)
{
unsigned int epll_con, epll_con_k;
@ -1585,7 +1522,7 @@ unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_pll_clk(pllreg);
return exynos542x_get_pll_clk(pllreg);
return exynos5_get_pll_clk(pllreg);
} else {
if (proid_is_exynos4412())
@ -1608,7 +1545,7 @@ unsigned long get_arm_clk(void)
unsigned long get_i2c_clk(void)
{
if (cpu_is_exynos5()) {
return exynos5_get_i2c_clk();
return clock_get_periph_rate(PERIPH_ID_I2C0);
} else if (cpu_is_exynos4()) {
return exynos4_get_i2c_clk();
} else {
@ -1620,8 +1557,6 @@ unsigned long get_i2c_clk(void)
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_pwm_clk();
return clock_get_periph_rate(PERIPH_ID_PWM0);
} else {
if (proid_is_exynos4412())
@ -1632,10 +1567,28 @@ unsigned long get_pwm_clk(void)
unsigned long get_uart_clk(int dev_index)
{
enum periph_id id;
switch (dev_index) {
case 0:
id = PERIPH_ID_UART0;
break;
case 1:
id = PERIPH_ID_UART1;
break;
case 2:
id = PERIPH_ID_UART2;
break;
case 3:
id = PERIPH_ID_UART3;
break;
default:
debug("%s: invalid UART index %d", __func__, dev_index);
return -1;
}
if (cpu_is_exynos5()) {
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_uart_clk(dev_index);
return exynos5_get_uart_clk(dev_index);
return clock_get_periph_rate(id);
} else {
if (proid_is_exynos4412())
return exynos4x12_get_uart_clk(dev_index);
@ -1645,10 +1598,28 @@ unsigned long get_uart_clk(int dev_index)
unsigned long get_mmc_clk(int dev_index)
{
enum periph_id id;
switch (dev_index) {
case 0:
id = PERIPH_ID_SDMMC0;
break;
case 1:
id = PERIPH_ID_SDMMC1;
break;
case 2:
id = PERIPH_ID_SDMMC2;
break;
case 3:
id = PERIPH_ID_SDMMC3;
break;
default:
debug("%s: invalid MMC index %d", __func__, dev_index);
return -1;
}
if (cpu_is_exynos5()) {
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_mmc_clk(dev_index);
return exynos5_get_mmc_clk(dev_index);
return clock_get_periph_rate(id);
} else {
return exynos4_get_mmc_clk(dev_index);
}
@ -1656,6 +1627,10 @@ unsigned long get_mmc_clk(int dev_index)
void set_mmc_clk(int dev_index, unsigned int div)
{
/* If want to set correct value, it needs to substract one from div.*/
if (div > 0)
div -= 1;
if (cpu_is_exynos5()) {
if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_set_mmc_clk(dev_index, div);

28
arch/arm/cpu/armv7/exynos/power.c
View file

@ -102,10 +102,34 @@ static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
}
}
static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable)
{
struct exynos5420_power *power =
(struct exynos5420_power *)samsung_get_base_power();
if (enable) {
/* Enabling USBDEV_PHY */
setbits_le32(&power->usbdev_phy_control,
POWER_USB_DRD_PHY_CTRL_EN);
setbits_le32(&power->usbdev1_phy_control,
POWER_USB_DRD_PHY_CTRL_EN);
} else {
/* Disabling USBDEV_PHY */
clrbits_le32(&power->usbdev_phy_control,
POWER_USB_DRD_PHY_CTRL_EN);
clrbits_le32(&power->usbdev1_phy_control,
POWER_USB_DRD_PHY_CTRL_EN);
}
}
void set_usbdrd_phy_ctrl(unsigned int enable)
{
if (cpu_is_exynos5())
exynos5_set_usbdrd_phy_ctrl(enable);
if (cpu_is_exynos5()) {
if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_set_usbdev_phy_ctrl(enable);
else
exynos5_set_usbdrd_phy_ctrl(enable);
}
}
static void exynos5_dp_phy_control(unsigned int enable)

1
arch/arm/cpu/armv7/exynos/spl_boot.c
View file

@ -309,4 +309,3 @@ void board_init_r(gd_t *id, ulong dest_addr)
while (1)
;
}
void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}

231
arch/arm/cpu/armv7/ls102xa/cpu.c
View file

@ -8,14 +8,214 @@
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
#include <asm/cache.h>
#include <asm/system.h>
#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
#include "fsl_epu.h"
#define DCSR_RCPM2_BLOCK_OFFSET 0x223000
#define DCSR_RCPM2_CPMFSMCR0 0x400
#define DCSR_RCPM2_CPMFSMSR0 0x404
#define DCSR_RCPM2_CPMFSMCR1 0x414
#define DCSR_RCPM2_CPMFSMSR1 0x418
#define CPMFSMSR_FSM_STATE_MASK 0x7f
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
/*
* Bit[1] of the descriptor indicates the descriptor type,
* and bit[0] indicates whether the descriptor is valid.
*/
#define PMD_TYPE_TABLE 0x3
#define PMD_TYPE_SECT 0x1
/* AttrIndx[2:0] */
#define PMD_ATTRINDX(t) ((t) << 2)
/* Section */
#define PMD_SECT_AF (1 << 10)
#define BLOCK_SIZE_L1 (1UL << 30)
#define BLOCK_SIZE_L2 (1UL << 21)
/* TTBCR flags */
#define TTBCR_EAE (1 << 31)
#define TTBCR_T0SZ(x) ((x) << 0)
#define TTBCR_T1SZ(x) ((x) << 16)
#define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
#define TTBCR_IRGN0_NC (0 << 8)
#define TTBCR_IRGN0_WBWA (1 << 8)
#define TTBCR_IRGN0_WT (2 << 8)
#define TTBCR_IRGN0_WBNWA (3 << 8)
#define TTBCR_IRGN0_MASK (3 << 8)
#define TTBCR_ORGN0_NC (0 << 10)
#define TTBCR_ORGN0_WBWA (1 << 10)
#define TTBCR_ORGN0_WT (2 << 10)
#define TTBCR_ORGN0_WBNWA (3 << 10)
#define TTBCR_ORGN0_MASK (3 << 10)
#define TTBCR_SHARED_NON (0 << 12)
#define TTBCR_SHARED_OUTER (2 << 12)
#define TTBCR_SHARED_INNER (3 << 12)
#define TTBCR_EPD0 (0 << 7)
#define TTBCR (TTBCR_SHARED_NON | \
TTBCR_ORGN0_NC | \
TTBCR_IRGN0_NC | \
TTBCR_USING_TTBR0 | \
TTBCR_EAE)
/*
* Memory region attributes for LPAE (defined in pgtable):
*
* n = AttrIndx[2:0]
*
* n MAIR
* UNCACHED 000 00000000
* BUFFERABLE 001 01000100
* DEV_WC 001 01000100
* WRITETHROUGH 010 10101010
* WRITEBACK 011 11101110
* DEV_CACHED 011 11101110
* DEV_SHARED 100 00000100
* DEV_NONSHARED 100 00000100
* unused 101
* unused 110
* WRITEALLOC 111 11111111
*/
#define MT_MAIR0 0xeeaa4400
#define MT_MAIR1 0xff000004
#define MT_STRONLY_ORDER 0
#define MT_NORMAL_NC 1
#define MT_DEVICE_MEM 4
#define MT_NORMAL 7
/* The phy_addr must be aligned to 4KB */
static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr)
{
u32 value = phy_addr | PMD_TYPE_TABLE;
page_table[2 * index] = value;
page_table[2 * index + 1] = 0;
}
/* The phy_addr must be aligned to 4KB */
static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr,
u32 memory_type)
{
u64 value;
value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF;
value |= PMD_ATTRINDX(memory_type);
page_table[2 * index] = value & 0xFFFFFFFF;
page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF;
}
/*
* Start MMU after DDR is available, we create MMU table in DRAM.
* The base address of TTLB is gd->arch.tlb_addr. We use two
* levels of translation tables here to cover 40-bit address space.
*
* The TTLBs are located at PHY 2G~4G.
*
* VA mapping:
*
* ------- <---- 0GB
* | |
* | |
* |-------| <---- 0x24000000
* |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
* |-------| <---- 0x300000000
* | |
* |-------| <---- 0x34000000
* |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
* |-------| <---- 0x40000000
* | |
* |-------| <---- 0x80000000 DDR0 space start
* |\\\\\\\|
*.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space
* |\\\\\\\|
* ------- <---- 4GB DDR0 space end
*/
static void mmu_setup(void)
{
u32 *level0_table = (u32 *)gd->arch.tlb_addr;
u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000);
u64 va_start = 0;
u32 reg;
int i;
/* Level 0 Table 2-3 are used to map DDR */
set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL);
set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL);
/* Level 0 Table 1 is used to map device */
set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM);
/* Level 0 Table 0 is used to map device including PCIe MEM */
set_pgtable(level0_table, 0, (u32)level1_table);
/* Level 1 has 512 entries */
for (i = 0; i < 512; i++) {
/* Mapping for PCIe 1 */
if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
CONFIG_SYS_PCIE_MMAP_SIZE))
set_pgsection(level1_table, i,
CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
MT_DEVICE_MEM);
/* Mapping for PCIe 2 */
else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
CONFIG_SYS_PCIE_MMAP_SIZE))
set_pgsection(level1_table, i,
CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
MT_DEVICE_MEM);
else
set_pgsection(level1_table, i,
va_start,
MT_DEVICE_MEM);
va_start += BLOCK_SIZE_L2;
}
asm volatile("dsb sy;isb");
asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */
: : "r" (TTBCR) : "memory");
asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */
: : "r" ((u32)level0_table), "r" (0) : "memory");
asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */
: : "r" (MT_MAIR0) : "memory");
asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */
: : "r" (MT_MAIR1) : "memory");
/* Set the access control to all-supervisor */
asm volatile("mcr p15, 0, %0, c3, c0, 0"
: : "r" (~0));
/* Enable the mmu */
reg = get_cr();
set_cr(reg | CR_M);
}
/*
* This function is called from lib/board.c. It recreates MMU
* table in main memory. MMU and i/d-cache are enabled here.
*/
void enable_caches(void)
{
/* Invalidate all TLB */
mmu_page_table_flush(gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
/* Set up and enable mmu */
mmu_setup();
/* Invalidate & Enable d-cache */
invalidate_dcache_all();
set_cr(get_cr() | CR_C);
}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
@ -78,16 +278,6 @@ int print_cpuinfo(void)
}
#endif
void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
icache_enable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_enable();
#endif
}
#ifdef CONFIG_FSL_ESDHC
int cpu_mmc_init(bd_t *bis)
{
@ -107,6 +297,27 @@ int cpu_eth_init(bd_t *bis)
int arch_cpu_init(void)
{
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *rcpm2_base =
(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
u32 state;
/*
* The RCPM FSM state may not be reset after power-on.
* So, reset them.
*/
state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
CPMFSMSR_FSM_STATE_MASK;
if (state != 0) {
out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
}
state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
CPMFSMSR_FSM_STATE_MASK;
if (state != 0) {
out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
}
/*
* After wakeup from deep sleep, Clear EPU registers

4
arch/arm/cpu/armv7/omap-common/emif-common.c
View file

@ -252,6 +252,8 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
/*
* Set SDRAM_CONFIG and PHY control registers to locked frequency
* and RL =7. As the default values of the Mode Registers are not
@ -265,7 +267,6 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
/*
@ -274,6 +275,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
*/
if (is_dra7xx()) {
do_ext_phy_settings(base, regs);
writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
} else {

2
arch/arm/cpu/armv7/omap-common/lowlevel_init.S
View file

@ -19,7 +19,7 @@
ENTRY(save_boot_params)
ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
str r0, [r1]
bx lr
b save_boot_params_ret
ENDPROC(save_boot_params)
ENTRY(set_pl310_ctrl_reg)

15
arch/arm/cpu/armv7/omap3/Kconfig
View file

@ -93,6 +93,21 @@ config TARGET_TWISTER
endchoice
config DM
default y
config DM_GPIO
default y if DM
config DM_SERIAL
default y if DM
config SYS_MALLOC_F
default y if DM
config SYS_MALLOC_F_LEN
default 0x400 if DM
config SYS_SOC
default "omap3"

2
arch/arm/cpu/armv7/omap3/lowlevel_init.S
View file

@ -23,7 +23,7 @@ ENTRY(save_boot_params)
ldr r5, [r0, #0x4]
and r5, r5, #0xff
str r5, [r4]
bx lr
b save_boot_params_ret
ENDPROC(save_boot_params)
#endif

83
arch/arm/cpu/armv7/omap5/sdram.c
View file

@ -141,7 +141,8 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61851ab2,
.sdram_config = 0x61851ab2,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x00001035,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
@ -151,10 +152,10 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
@ -165,7 +166,8 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x00001035,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
@ -175,10 +177,10 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
@ -186,18 +188,19 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
};
const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61851AB2,
.sdram_config = 0x61851AB2,
.sdram_config_init = 0x61862B32,
.sdram_config = 0x61862B32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
.ref_ctrl = 0x0000493E,
.ref_ctrl_final = 0x0000144A,
.sdram_tim1 = 0xD113781C,
.sdram_tim2 = 0x308F7FE3,
.sdram_tim3 = 0x009F86A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400A,
.emif_ddr_phy_ctlr_1 = 0x0024400A,
.emif_ddr_phy_ctlr_1_init = 0x0E24400D,
.emif_ddr_phy_ctlr_1 = 0x0E24400D,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
.emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
@ -420,22 +423,22 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
0x00BB00BB,
0x00440044,
0x00440044,
0x00440044,
0x00440044,
0x00440044,
0x00980098,
0x00340034,
0x00350035,
0x00340034,
0x00310031,
0x00340034,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x00480048,
0x004A004A,
0x00520052,
0x00550055,
0x00500050,
0x00000000,
0x00600020,
0x40010080,
@ -449,22 +452,22 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
0x00BB00BB,
0x00440044,
0x00440044,
0x00440044,
0x00440044,
0x00440044,
0x00980098,
0x00330033,
0x00330033,
0x002F002F,
0x00320032,
0x00310031,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x00520052,
0x00520052,
0x00470047,
0x00490049,
0x00500050,
0x00000000,
0x00600020,
0x40010080,

6
arch/arm/cpu/armv7/rmobile/Kconfig
View file

@ -21,6 +21,9 @@ config TARGET_KZM9G
config TARGET_ALT
bool "Alt board"
config TARGET_SILK
bool "Silk board"
endchoice
config SYS_SOC
@ -28,7 +31,7 @@ config SYS_SOC
config RMOBILE_EXTRAM_BOOT
bool "Enable boot from RAM"
depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER
depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_SILK
default n
source "board/atmark-techno/armadillo-800eva/Kconfig"
@ -37,5 +40,6 @@ source "board/renesas/koelsch/Kconfig"
source "board/renesas/lager/Kconfig"
source "board/kmc/kzm9g/Kconfig"
source "board/renesas/alt/Kconfig"
source "board/renesas/silk/Kconfig"
endif

12
arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
View file

@ -40,7 +40,7 @@ do_lowlevel_init:
and r1, r1, #0x7F00
lsrs r1, r1, #8
cmp r1, #0x4C /* 0x4C is ID of r8a7794 */
beq _exit_init_l2_a15
beq _enable_actlr_smp
/* surpress wfe if ca15 */
tst r4, #4
@ -64,6 +64,16 @@ do_lowlevel_init:
orrne r0, r0, #0x20 /* L2CTLR[5] */
#endif
mcrne p15, 1, r0, c9, c0, 2
b _exit_init_l2_a15
_enable_actlr_smp: /* R8A7794 only (CA7) */
#ifndef CONFIG_DCACHE_OFF
mrc p15, 0, r0, c1, c0, 1
orr r0, r0, #0x40
mcr p15, 0, r0, c1, c0, 1
#endif
_exit_init_l2_a15:
ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
sub sp, r3, #4

4
arch/arm/cpu/armv7/s5pc1xx/Kconfig
View file

@ -5,11 +5,11 @@ choice
config TARGET_S5P_GONI
bool "S5P Goni board"
select OF_CONTROL if !SPL_BUILD
select OF_CONTROL
config TARGET_SMDKC100
bool "Support smdkc100 board"
select OF_CONTROL if !SPL_BUILD
select OF_CONTROL
endchoice

7
arch/arm/cpu/armv7/start.S
View file

@ -31,9 +31,12 @@
*************************************************************************/
.globl reset
.globl save_boot_params_ret
reset:
bl save_boot_params
/* Allow the board to save important registers */
b save_boot_params
save_boot_params_ret:
/*
* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
* except if in HYP mode already
@ -96,7 +99,7 @@ ENDPROC(c_runtime_cpu_setup)
*
*************************************************************************/
ENTRY(save_boot_params)
bx lr @ back to my caller
b save_boot_params_ret @ back to my caller
ENDPROC(save_boot_params)
.weak save_boot_params

5
arch/arm/cpu/armv7/sunxi/Makefile
View file

@ -11,6 +11,7 @@ obj-y += timer.o
obj-y += board.o
obj-y += clock.o
obj-y += cpu_info.o
obj-y += dram_helpers.o
obj-y += pinmux.o
obj-y += usbc.o
obj-$(CONFIG_MACH_SUN6I) += prcm.o
@ -38,7 +39,5 @@ obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o
ifdef CONFIG_SPL_FEL
obj-y += start.o
endif
obj-y += fel_utils.o
endif

46
arch/arm/cpu/armv7/sunxi/board.c
View file

@ -27,6 +27,17 @@
#include <linux/compiler.h>
struct fel_stash {
uint32_t sp;
uint32_t lr;
uint32_t cpsr;
uint32_t sctlr;
uint32_t vbar;
uint32_t cr;
};
struct fel_stash fel_stash __attribute__((section(".data")));
static int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
@ -65,6 +76,12 @@ static int gpio_init(void)
return 0;
}
void spl_board_load_image(void)
{
debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
return_to_fel(fel_stash.sp, fel_stash.lr);
}
void s_init(void)
{
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
@ -95,7 +112,34 @@ void s_init(void)
*/
u32 spl_boot_device(void)
{
return BOOT_DEVICE_MMC1;
#ifdef CONFIG_SPL_FEL
/*
* This is the legacy compile time configuration for a special FEL
* enabled build. It has many restrictions and can only boot over USB.
*/
return BOOT_DEVICE_BOARD;
#else
/*
* When booting from the SD card, the "eGON.BT0" signature is expected
* to be found in memory at the address 0x0004 (see the "mksunxiboot"
* tool, which generates this header).
*
* When booting in the FEL mode over USB, this signature is patched in
* memory and replaced with something else by the 'fel' tool. This other
* signature is selected in such a way, that it can't be present in a
* valid bootable SD card image (because the BROM would refuse to
* execute the SPL in this case).
*
* This branch is just making a decision at runtime whether to load
* the main u-boot binary from the SD card (if the "eGON.BT0" signature
* is found) or return to the FEL code in the BROM to wait and receive
* the main u-boot binary over USB.
*/
if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */
return BOOT_DEVICE_MMC1;
else
return BOOT_DEVICE_BOARD;
#endif
}
/* No confirmation data available in SPL yet. Hardcode bootmode */

2
arch/arm/cpu/armv7/sunxi/config.mk
View file

@ -1,8 +1,6 @@
# Build a combined spl + u-boot image
ifdef CONFIG_SPL
ifndef CONFIG_SPL_BUILD
ifndef CONFIG_SPL_FEL
ALL-y += u-boot-sunxi-with-spl.bin
endif
endif
endif

37
arch/arm/cpu/armv7/sunxi/dram_helpers.c Normal file
View file

@ -0,0 +1,37 @@
/*
* DRAM init helper functions
*
* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/dram.h>
/*
* Wait up to 1s for value to be set in given part of reg.
*/
void mctl_await_completion(u32 *reg, u32 mask, u32 val)
{
unsigned long tmo = timer_get_us() + 1000000;
while ((readl(reg) & mask) != val) {
if (timer_get_us() > tmo)
panic("Timeout initialising DRAM\n");
}
}
/*
* Test if memory at offset offset matches memory at begin of DRAM
*/
bool mctl_mem_matches(u32 offset)
{
/* Try to write different values to RAM at two addresses */
writel(0, CONFIG_SYS_SDRAM_BASE);
writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset);
/* Check if the same value is actually observed when reading back */
return readl(CONFIG_SYS_SDRAM_BASE) ==
readl(CONFIG_SYS_SDRAM_BASE + offset);
}

42
arch/arm/cpu/armv7/sunxi/fel_utils.S Normal file
View file

@ -0,0 +1,42 @@
/*
* Utility functions for FEL mode.
*
* Copyright (c) 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/system.h>
#include <linux/linkage.h>
ENTRY(save_boot_params)
ldr r0, =fel_stash
str sp, [r0, #0]
str lr, [r0, #4]
mrs lr, cpsr @ Read CPSR
str lr, [r0, #8]
mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
str lr, [r0, #12]
mrc p15, 0, lr, c12, c0, 0 @ Read VBAR
str lr, [r0, #16]
mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
str lr, [r0, #20]
b save_boot_params_ret
ENDPROC(save_boot_params)
ENTRY(return_to_fel)
mov sp, r0
mov lr, r1
ldr r0, =fel_stash
ldr r1, [r0, #20]
mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
ldr r1, [r0, #16]
mcr p15, 0, r1, c12, c0, 0 @ Write VBAR
ldr r1, [r0, #12]
mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
ldr r1, [r0, #8]
msr cpsr, r1 @ Write CPSR
bx lr
ENDPROC(return_to_fel)

82
arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
View file

@ -1,82 +0,0 @@
/*
* (C) Copyright 2013
* Henrik Nordstrom <henrik@henriknordstrom.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(s_init)
SECTIONS
{
. = 0x00002000;
. = ALIGN(4);
.text :
{
*(.text.s_init)
*(.text*)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : {
*(.data*)
}
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
. = .;
. = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
__rel_dyn_end = .;
}
.dynsym : {
__dynsym_start = .;
*(.dynsym)
}
. = ALIGN(4);
.note.gnu.build-id :
{
*(.note.gnu.build-id)
}
_end = .;
. = ALIGN(4096);
.mmutable : {
*(.mmutable)
}
.bss_start __rel_dyn_start (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
.bss __bss_base (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
__bss_limit = .;
}
.bss_end __bss_limit (OVERLAY) : {
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
/DISCARD/ : { *(.note*) }
}

28
arch/arm/cpu/armv7/tegra-common/Kconfig
View file

@ -1,28 +0,0 @@
if TEGRA
choice
prompt "Tegra SoC select"
config TEGRA20
bool "Tegra20 family"
config TEGRA30
bool "Tegra30 family"
config TEGRA114
bool "Tegra114 family"
config TEGRA124
bool "Tegra124 family"
endchoice
config USE_PRIVATE_LIBGCC
default y if SPL_BUILD
source "arch/arm/cpu/armv7/tegra20/Kconfig"
source "arch/arm/cpu/armv7/tegra30/Kconfig"
source "arch/arm/cpu/armv7/tegra114/Kconfig"
source "arch/arm/cpu/armv7/tegra124/Kconfig"
endif

10
arch/arm/cpu/armv7/tegra-common/Makefile
View file

@ -1,10 +0,0 @@
#
# (C) Copyright 2010,2011 Nvidia Corporation.
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o

11
arch/arm/cpu/armv7/tegra20/Makefile
View file

@ -1,11 +0,0 @@
#
# (C) Copyright 2010,2011 Nvidia Corporation.
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_PWM_TEGRA) += pwm.o
obj-$(CONFIG_VIDEO_TEGRA) += display.o

8
arch/arm/cpu/armv7/uniphier/Kconfig
View file

@ -48,6 +48,12 @@ config DCC_MICRO_SUPPORT_CARD
endchoice
config SYS_MALLOC_F
default y
config SYS_MALLOC_F_LEN
default 0x400
config CMD_PINMON
bool "Enable boot mode pins monitor command"
default y
@ -58,14 +64,12 @@ config CMD_PINMON
config CMD_DDRPHY_DUMP
bool "Enable dump command of DDR PHY parameters"
depends on !SPL_BUILD
help
The command "ddrphy" shows the resulting parameters of DDR PHY
training; it is useful for the evaluation of DDR PHY training.
choice
prompt "DDR3 Frequency select"
depends on SPL_BUILD
config DDR_FREQ_1600
bool "DDR3 1600"

6
arch/arm/cpu/armv8/cache.S
View file

@ -155,3 +155,9 @@ ENTRY(__asm_invalidate_icache_all)
isb sy
ret
ENDPROC(__asm_invalidate_icache_all)
ENTRY(__asm_flush_l3_cache)
mov x0, #0 /* return status as success */
ret
ENDPROC(__asm_flush_l3_cache)
.weak __asm_flush_l3_cache

18
arch/arm/cpu/armv8/cache_v8.c
View file

@ -73,17 +73,21 @@ void invalidate_dcache_all(void)
__asm_invalidate_dcache_all();
}
void __weak flush_l3_cache(void)
{
}
/*
* Performs a clean & invalidation of the entire data cache at all levels
* Performs a clean & invalidation of the entire data cache at all levels.
* This function needs to be inline to avoid using stack.
* __asm_flush_l3_cache return status of timeout
*/
void flush_dcache_all(void)
inline void flush_dcache_all(void)
{
int ret;
__asm_flush_dcache_all();
flush_l3_cache();
ret = __asm_flush_l3_cache();
if (ret)
debug("flushing dcache returns 0x%x\n", ret);
else
debug("flushing dcache successfully.\n");
}
/*

62
arch/arm/cpu/armv8/fsl-lsch3/cpu.c
View file

@ -10,10 +10,10 @@
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
#include <fsl-mc/fsl_mc.h>
#include "cpu.h"
#include "mp.h"
#include "speed.h"
#include <fsl_mc.h>
DECLARE_GLOBAL_DATA_PTR;
@ -150,7 +150,7 @@ static inline void final_mmu_setup(void)
* set level 2 table 0 to cache-inhibit, covering 0 to 1GB
*/
section_l1t0 = 0;
section_l1t1 = BLOCK_SIZE_L0;
section_l1t1 = BLOCK_SIZE_L0 | PMD_SECT_OUTER_SHARE;
section_l2 = 0;
for (i = 0; i < 512; i++) {
set_pgtable_section(level1_table_0, i, section_l1t0,
@ -168,10 +168,10 @@ static inline void final_mmu_setup(void)
(u64)level2_table_0 | PMD_TYPE_TABLE;
level1_table_0[2] =
0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
PMD_ATTRINDX(MT_NORMAL);
PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL);
level1_table_0[3] =
0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
PMD_ATTRINDX(MT_NORMAL);
PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL);
/* Rewrite table to enable cache */
set_pgtable_section(level2_table_0,
@ -242,59 +242,6 @@ int arch_cpu_init(void)
return 0;
}
/*
* flush_l3_cache
* Dickens L3 cache can be flushed by transitioning from FAM to SFONLY power
* state, by writing to HP-F P-state request register.
* Fixme: This function should moved to a common file if other SoCs also use
* the same Dickens.
*/
#define HNF0_PSTATE_REQ 0x04200010
#define HNF1_PSTATE_REQ 0x04210010
#define HNF2_PSTATE_REQ 0x04220010
#define HNF3_PSTATE_REQ 0x04230010
#define HNF4_PSTATE_REQ 0x04240010
#define HNF5_PSTATE_REQ 0x04250010
#define HNF6_PSTATE_REQ 0x04260010
#define HNF7_PSTATE_REQ 0x04270010
#define HNFPSTAT_MASK (0xFFFFFFFFFFFFFFFC)
#define HNFPSTAT_FAM 0x3
#define HNFPSTAT_SFONLY 0x01
static void hnf_pstate_req(u64 *ptr, u64 state)
{
int timeout = 1000;
out_le64(ptr, (in_le64(ptr) & HNFPSTAT_MASK) | (state & 0x3));
ptr++;
/* checking if the transition is completed */
while (timeout > 0) {
if (((in_le64(ptr) & 0x0c) >> 2) == (state & 0x3))
break;
udelay(100);
timeout--;
}
}
void flush_l3_cache(void)
{
hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_SFONLY);
hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_SFONLY);
hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_SFONLY);
hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_SFONLY);
hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_SFONLY);
hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_SFONLY);
hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_SFONLY);
hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_SFONLY);
hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_FAM);
hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_FAM);
hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_FAM);
hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_FAM);
hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_FAM);
hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_FAM);
hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_FAM);
hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_FAM);
}
/*
* This function is called from lib/board.c.
* It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
@ -420,6 +367,7 @@ int print_cpuinfo(void)
printf("\n Bus: %-4s MHz ",
strmhz(buf, sysinfo.freq_systembus));
printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus));
printf(" DP-DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2));
puts("\n");
return 0;

28
arch/arm/cpu/armv8/fsl-lsch3/fdt.c
View file

@ -16,7 +16,7 @@ void ft_fixup_cpu(void *blob)
__maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
fdt32_t *reg;
int addr_cells;
u64 val;
u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
off = fdt_path_offset(blob, "/cpus");
@ -29,15 +29,20 @@ void ft_fixup_cpu(void *blob)
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
core_id = of_read_number(reg, addr_cells);
if (reg) {
val = spin_tbl_addr;
val += id_to_core(of_read_number(reg, addr_cells))
* SPIN_TABLE_ELEM_SIZE;
val = cpu_to_fdt64(val);
fdt_setprop_string(blob, off, "enable-method",
"spin-table");
fdt_setprop(blob, off, "cpu-release-addr",
&val, sizeof(val));
if (core_id == 0 || (is_core_online(core_id))) {
val = spin_tbl_addr;
val += id_to_core(core_id) *
SPIN_TABLE_ELEM_SIZE;
val = cpu_to_fdt64(val);
fdt_setprop_string(blob, off, "enable-method",
"spin-table");
fdt_setprop(blob, off, "cpu-release-addr",
&val, sizeof(val));
} else {
debug("skipping offline core\n");
}
} else {
puts("Warning: found cpu node without reg property\n");
}
@ -55,4 +60,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_MP
ft_fixup_cpu(blob);
#endif
#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "ns16550",
"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
#endif
}

132
arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
View file

@ -42,10 +42,142 @@ ENTRY(lowlevel_init)
ldr x0, =secondary_boot_func
blr x0
2:
#ifdef CONFIG_FSL_TZPC_BP147
/* Set Non Secure access for all devices protected via TZPC */
ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
str w0, [x1]
isb
dsb sy
#endif
#ifdef CONFIG_FSL_TZASC_400
/* Set TZASC so that:
* a. We use only Region0 whose global secure write/read is EN
* b. We use only Region0 whose NSAID write/read is EN
*
* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
* placeholders.
*/
ldr x1, =TZASC_GATE_KEEPER(0)
ldr x0, [x1] /* Filter 0 Gate Keeper Register */
orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */
str x0, [x1]
ldr x1, =TZASC_GATE_KEEPER(1)
ldr x0, [x1] /* Filter 0 Gate Keeper Register */
orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */
str x0, [x1]
ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
ldr x0, [x1] /* Region-0 Attributes Register */
orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */
orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */
str x0, [x1]
ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
ldr x0, [x1] /* Region-1 Attributes Register */
orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */
orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */
str x0, [x1]
ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
ldr w0, [x1] /* Region-0 Access Register */
mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
str w0, [x1]
ldr x1, =TZASC_REGION_ID_ACCESS_0(1)
ldr w0, [x1] /* Region-1 Attributes Register */
mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
str w0, [x1]
isb
dsb sy
#endif
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)
hnf_pstate_poll:
/* x0 has the desired status, return 0 for success, 1 for timeout
* clobber x1, x2, x3, x4, x6, x7
*/
mov x1, x0
mov x7, #0 /* flag for timeout */
mrs x3, cntpct_el0 /* read timer */
add x3, x3, #1200 /* timeout after 100 microseconds */
mov x0, #0x18
movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
mov w6, #8 /* HN-F node count */
1:
ldr x2, [x0]
cmp x2, x1 /* check status */
b.eq 2f
mrs x4, cntpct_el0
cmp x4, x3
b.ls 1b
mov x7, #1 /* timeout */
b 3f
2:
add x0, x0, #0x10000 /* move to next node */
subs w6, w6, #1
cbnz w6, 1b
3:
mov x0, x7
ret
hnf_set_pstate:
/* x0 has the desired state, clobber x1, x2, x6 */
mov x1, x0
/* power state to SFONLY */
mov w6, #8 /* HN-F node count */
mov x0, #0x10
movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
1: /* set pstate to sfonly */
ldr x2, [x0]
and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
orr x2, x2, x1
str x2, [x0]
add x0, x0, #0x10000 /* move to next node */
subs w6, w6, #1
cbnz w6, 1b
ret
ENTRY(__asm_flush_l3_cache)
/*
* Return status in x0
* success 0
* tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
*/
mov x29, lr
mov x8, #0
dsb sy
mov x0, #0x1 /* HNFPSTAT_SFONLY */
bl hnf_set_pstate
mov x0, #0x4 /* SFONLY status */
bl hnf_pstate_poll
cbz x0, 1f
mov x8, #1 /* timeout */
1:
dsb sy
mov x0, #0x3 /* HNFPSTAT_FAM */
bl hnf_set_pstate
mov x0, #0xc /* FAM status */
bl hnf_pstate_poll
cbz x0, 1f
add x8, x8, #0x2
1:
mov x0, x8
mov lr, x29
ret
ENDPROC(__asm_flush_l3_cache)
/* Keep literals not used by the secondary boot code outside it */
.ltorg

8
arch/arm/cpu/armv8/fsl-lsch3/mp.c
View file

@ -83,6 +83,14 @@ int is_core_valid(unsigned int core)
return !!((1 << core) & cpu_mask());
}
int is_core_online(u64 cpu_id)
{
u64 *table;
int pos = id_to_core(cpu_id);
table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY;
return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
}
int cpu_reset(int nr)
{
puts("Feature is not implemented.\n");

1
arch/arm/cpu/armv8/fsl-lsch3/mp.h
View file

@ -32,5 +32,6 @@ int fsl_lsch3_wake_seconday_cores(void);
void *get_spin_tbl_addr(void);
phys_addr_t determine_mp_bootpg(void);
void secondary_boot_func(void);
int is_core_online(u64 cpu_id);
#endif
#endif /* _FSL_CH3_MP_H */

16
arch/arm/cpu/armv8/fsl-lsch3/speed.c
View file

@ -77,8 +77,10 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_systembus = sysclk;
#ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
#else
sys_info->freq_ddrbus = sysclk;
sys_info->freq_ddrbus2 = sysclk;
#endif
sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
@ -87,6 +89,9 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
/*
@ -129,7 +134,7 @@ int get_clocks(void)
gd->cpu_clk = sys_info.freq_processor[0];
gd->bus_clk = sys_info.freq_systembus;
gd->mem_clk = sys_info.freq_ddrbus;
gd->arch.mem2_clk = sys_info.freq_ddrbus2;
#if defined(CONFIG_FSL_ESDHC)
gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif /* defined(CONFIG_FSL_ESDHC) */
@ -156,11 +161,18 @@ ulong get_bus_freq(ulong dummy)
* get_ddr_freq
* return ddr bus freq in Hz
*********************************************/
ulong get_ddr_freq(ulong dummy)
ulong get_ddr_freq(ulong ctrl_num)
{
if (!gd->mem_clk)
get_clocks();
/*
* DDR controller 0 & 1 are on memory complex 0
* DDR controler 2 is on memory complext 1
*/
if (ctrl_num >= 2)
return gd->arch.mem2_clk;
return gd->mem_clk;
}

5
arch/arm/dts/exynos4412-odroid.dts
View file

@ -85,4 +85,9 @@
reg = <0x125B0000 0x100>;
};
};
emmc-reset {
compatible = "samsung,emmc-reset";
reset-gpio = <&gpk1 2 0>;
};
};

5
arch/arm/dts/exynos5422-odroidxu3.dts
View file

@ -46,4 +46,9 @@
mmc@12220000 {
fifoth_val = <0x201f0020>;
};
emmc-reset {
compatible = "samsung,emmc-reset";
reset-gpio = <&gpd1 0 0>;
};
};

22
arch/arm/include/asm/arch-a320/a320.h
View file

@ -1,22 +0,0 @@
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __A320_H
#define __A320_H
/*
* Hardware register bases
*/
#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */
#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */
#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */
#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */
#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */
#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */
#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/
#endif /* __A320_H */

2
arch/arm/include/asm/arch-am33xx/cpu.h
View file

@ -400,6 +400,8 @@ struct prm_device_inst {
struct cm_dpll {
unsigned int resv1;
unsigned int clktimer2clk; /* offset 0x04 */
unsigned int resv2[11];
unsigned int clkselmacclk; /* offset 0x34 */
};
#endif /* CONFIG_AM43XX */

5
arch/arm/include/asm/arch-bcm2835/gpio.h
View file

@ -1,6 +1,7 @@
/*
* Copyright (C) 2012 Vikram Narayananan
* <vikram186@gmail.com>
* (C) Copyright 2012,2015 Stephen Warren
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -8,7 +9,11 @@
#ifndef _BCM2835_GPIO_H_
#define _BCM2835_GPIO_H_
#ifdef CONFIG_BCM2836
#define BCM2835_GPIO_BASE 0x3f200000
#else
#define BCM2835_GPIO_BASE 0x20200000
#endif
#define BCM2835_GPIO_COUNT 54
#define BCM2835_GPIO_FSEL_MASK 0x7

10
arch/arm/include/asm/arch-bcm2835/mbox.h
View file

@ -1,5 +1,5 @@
/*
* (C) Copyright 2012 Stephen Warren
* (C) Copyright 2012,2015 Stephen Warren
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -38,7 +38,11 @@
/* Raw mailbox HW */
#ifdef CONFIG_BCM2836
#define BCM2835_MBOX_PHYSADDR 0x3f00b880
#else
#define BCM2835_MBOX_PHYSADDR 0x2000b880
#endif
struct bcm2835_mbox_regs {
u32 read;
@ -121,6 +125,9 @@ struct bcm2835_mbox_tag_hdr {
#define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002
#ifdef CONFIG_BCM2836
#define BCM2836_BOARD_REV_2_B 0x4
#else
/*
* 0x2..0xf from:
* http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/
@ -141,6 +148,7 @@ struct bcm2835_mbox_tag_hdr {
#define BCM2835_BOARD_REV_B_PLUS 0x10
#define BCM2835_BOARD_REV_CM 0x11
#define BCM2835_BOARD_REV_A_PLUS 0x12
#endif
struct bcm2835_mbox_tag_get_board_rev {
struct bcm2835_mbox_tag_hdr tag_hdr;

18
arch/arm/include/asm/arch-bcm2835/sdhci.h
View file

@ -1,23 +1,17 @@
/*
* (C) Copyright 2012 Stephen Warren
* (C) Copyright 2012,2015 Stephen Warren
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _BCM2835_SDHCI_H_
#define _BCM2835_SDHCI_H_
#ifdef CONFIG_BCM2836
#define BCM2835_SDHCI_BASE 0x3f300000
#else
#define BCM2835_SDHCI_BASE 0x20300000
#endif
int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq);

18
arch/arm/include/asm/arch-bcm2835/timer.h
View file

@ -1,23 +1,17 @@
/*
* (C) Copyright 2012 Stephen Warren
* (C) Copyright 2012,2015 Stephen Warren
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _BCM2835_TIMER_H
#define _BCM2835_TIMER_H
#ifdef CONFIG_BCM2836
#define BCM2835_TIMER_PHYSADDR 0x3f003000
#else
#define BCM2835_TIMER_PHYSADDR 0x20003000
#endif
struct bcm2835_timer_regs {
u32 cs;

18
arch/arm/include/asm/arch-bcm2835/wdog.h
View file

@ -1,23 +1,17 @@
/*
* (C) Copyright 2012 Stephen Warren
* (C) Copyright 2012,2015 Stephen Warren
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _BCM2835_TIMER_H
#define _BCM2835_TIMER_H
#ifdef CONFIG_BCM2836
#define BCM2835_WDOG_PHYSADDR 0x3f100000
#else
#define BCM2835_WDOG_PHYSADDR 0x20100000
#endif
struct bcm2835_wdog_regs {
u32 unknown0[7];

4
arch/arm/include/asm/arch-exynos/clk.h
View file

@ -26,6 +26,10 @@ enum pll_src_bit {
EXYNOS_SRC_MPLL = 6,
EXYNOS_SRC_EPLL,
EXYNOS_SRC_VPLL,
EXYNOS542X_SRC_MPLL = 3,
EXYNOS542X_SRC_SPLL,
EXYNOS542X_SRC_EPLL = 6,
EXYNOS542X_SRC_RPLL,
};
unsigned long get_pll_clk(int pllreg);

38
arch/arm/include/asm/arch-fsl-lsch3/config.h
View file

@ -30,11 +30,44 @@
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
0x18A0)
#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
/* TZ Protection Controller Definitions */
#define TZPC_BASE 0x02200000
#define TZPCR0SIZE_BASE (TZPC_BASE)
#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
/* TZ Address Space Controller Definitions */
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
#define GICR_BASE 0x06100000
@ -68,4 +101,9 @@
#error SoC not defined
#endif
#ifdef CONFIG_LS2085A
#define CONFIG_SYS_FSL_ERRATUM_A008336
#define CONFIG_SYS_FSL_ERRATUM_A008514
#endif
#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */

3
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
View file

@ -15,6 +15,7 @@ struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
unsigned long freq_systembus;
unsigned long freq_ddrbus;
unsigned long freq_ddrbus2;
unsigned long freq_localbus;
unsigned long freq_qe;
#ifdef CONFIG_SYS_DPAA_FMAN
@ -60,6 +61,8 @@ struct ccsr_gur {
#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
u8 res_180[0x200-0x180];
u32 scratchrw[32]; /* Scratch Read/Write */
u8 res_280[0x300-0x280];

294
arch/arm/include/asm/arch-ks8695/platform.h
View file

@ -1,294 +0,0 @@
/*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __address_h
#define __address_h 1
#define KS8695_SDRAM_START 0x00000000
#define KS8695_SDRAM_SIZE 0x01000000
#define KS8695_MEM_SIZE KS8695_SDRAM_SIZE
#define KS8695_MEM_START KS8695_SDRAM_START
#define KS8695_PCMCIA_IO_BASE 0x03800000
#define KS8695_PCMCIA_IO_SIZE 0x00040000
#define KS8695_IO_BASE 0x03FF0000
#define KS8695_IO_SIZE 0x00010000
#define KS8695_SYSTEN_CONFIG 0x00
#define KS8695_SYSTEN_BUS_CLOCK 0x04
#define KS8695_FLASH_START 0x02800000
#define KS8695_FLASH_SIZE 0x00400000
/*i/o control registers offset difinitions*/
#define KS8695_IO_CTRL0 0x4000
#define KS8695_IO_CTRL1 0x4004
#define KS8695_IO_CTRL2 0x4008
#define KS8695_IO_CTRL3 0x400C
/*memory control registers offset difinitions*/
#define KS8695_MEM_CTRL0 0x4010
#define KS8695_MEM_CTRL1 0x4014
#define KS8695_MEM_CTRL2 0x4018
#define KS8695_MEM_CTRL3 0x401C
#define KS8695_MEM_GENERAL 0x4020
#define KS8695_SDRAM_CTRL0 0x4030
#define KS8695_SDRAM_CTRL1 0x4034
#define KS8695_SDRAM_GENERAL 0x4038
#define KS8695_SDRAM_BUFFER 0x403C
#define KS8695_SDRAM_REFRESH 0x4040
/*WAN control registers offset difinitions*/
#define KS8695_WAN_DMA_TX 0x6000
#define KS8695_WAN_DMA_RX 0x6004
#define KS8695_WAN_DMA_TX_START 0x6008
#define KS8695_WAN_DMA_RX_START 0x600C
#define KS8695_WAN_TX_LIST 0x6010
#define KS8695_WAN_RX_LIST 0x6014
#define KS8695_WAN_MAC_LOW 0x6018
#define KS8695_WAN_MAC_HIGH 0x601C
#define KS8695_WAN_MAC_ELOW 0x6080
#define KS8695_WAN_MAC_EHIGH 0x6084
/*LAN control registers offset difinitions*/
#define KS8695_LAN_DMA_TX 0x8000
#define KS8695_LAN_DMA_RX 0x8004
#define KS8695_LAN_DMA_TX_START 0x8008
#define KS8695_LAN_DMA_RX_START 0x800C
#define KS8695_LAN_TX_LIST 0x8010
#define KS8695_LAN_RX_LIST 0x8014
#define KS8695_LAN_MAC_LOW 0x8018
#define KS8695_LAN_MAC_HIGH 0x801C
#define KS8695_LAN_MAC_ELOW 0X8080
#define KS8695_LAN_MAC_EHIGH 0X8084
/*HPNA control registers offset difinitions*/
#define KS8695_HPNA_DMA_TX 0xA000
#define KS8695_HPNA_DMA_RX 0xA004
#define KS8695_HPNA_DMA_TX_START 0xA008
#define KS8695_HPNA_DMA_RX_START 0xA00C
#define KS8695_HPNA_TX_LIST 0xA010
#define KS8695_HPNA_RX_LIST 0xA014
#define KS8695_HPNA_MAC_LOW 0xA018
#define KS8695_HPNA_MAC_HIGH 0xA01C
#define KS8695_HPNA_MAC_ELOW 0xA080
#define KS8695_HPNA_MAC_EHIGH 0xA084
/*UART control registers offset difinitions*/
#define KS8695_UART_RX_BUFFER 0xE000
#define KS8695_UART_TX_HOLDING 0xE004
#define KS8695_UART_FIFO_CTRL 0xE008
#define KS8695_UART_FIFO_TRIG01 0x00
#define KS8695_UART_FIFO_TRIG04 0x80
#define KS8695_UART_FIFO_TXRST 0x03
#define KS8695_UART_FIFO_RXRST 0x02
#define KS8695_UART_FIFO_FEN 0x01
#define KS8695_UART_LINE_CTRL 0xE00C
#define KS8695_UART_LINEC_BRK 0x40
#define KS8695_UART_LINEC_EPS 0x10
#define KS8695_UART_LINEC_PEN 0x08
#define KS8695_UART_LINEC_STP2 0x04
#define KS8695_UART_LINEC_WLEN8 0x03
#define KS8695_UART_LINEC_WLEN7 0x02
#define KS8695_UART_LINEC_WLEN6 0x01
#define KS8695_UART_LINEC_WLEN5 0x00
#define KS8695_UART_MODEM_CTRL 0xE010
#define KS8695_UART_MODEMC_RTS 0x02
#define KS8695_UART_MODEMC_DTR 0x01
#define KS8695_UART_LINE_STATUS 0xE014
#define KS8695_UART_LINES_TXFE 0x20
#define KS8695_UART_LINES_BE 0x10
#define KS8695_UART_LINES_FE 0x08
#define KS8695_UART_LINES_PE 0x04
#define KS8695_UART_LINES_OE 0x02
#define KS8695_UART_LINES_RXFE 0x01
#define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE)
#define KS8695_UART_MODEM_STATUS 0xE018
#define KS8695_UART_MODEM_DCD 0x80
#define KS8695_UART_MODEM_DSR 0x20
#define KS8695_UART_MODEM_CTS 0x10
#define KS8695_UART_MODEM_DDCD 0x08
#define KS8695_UART_MODEM_DDSR 0x02
#define KS8695_UART_MODEM_DCTS 0x01
#define UART8695_MODEM_ANY 0xFF
#define KS8695_UART_DIVISOR 0xE01C
#define KS8695_UART_STATUS 0xE020
/*Interrupt controlller registers offset difinitions*/
#define KS8695_INT_CONTL 0xE200
#define KS8695_INT_ENABLE 0xE204
#define KS8695_INT_ENABLE_MODEM 0x0800
#define KS8695_INT_ENABLE_ERR 0x0400
#define KS8695_INT_ENABLE_RX 0x0200
#define KS8695_INT_ENABLE_TX 0x0100
#define KS8695_INT_STATUS 0xE208
#define KS8695_INT_WAN_PRIORITY 0xE20C
#define KS8695_INT_HPNA_PRIORITY 0xE210
#define KS8695_INT_LAN_PRIORITY 0xE214
#define KS8695_INT_TIMER_PRIORITY 0xE218
#define KS8695_INT_UART_PRIORITY 0xE21C
#define KS8695_INT_EXT_PRIORITY 0xE220
#define KS8695_INT_CHAN_PRIORITY 0xE224
#define KS8695_INT_BUSERROR_PRO 0xE228
#define KS8695_INT_MASK_STATUS 0xE22C
#define KS8695_FIQ_PEND_PRIORITY 0xE230
#define KS8695_IRQ_PEND_PRIORITY 0xE234
/*timer registers offset difinitions*/
#define KS8695_TIMER_CTRL 0xE400
#define KS8695_TIMER1 0xE404
#define KS8695_TIMER0 0xE408
#define KS8695_TIMER1_PCOUNT 0xE40C
#define KS8695_TIMER0_PCOUNT 0xE410
/*GPIO registers offset difinitions*/
#define KS8695_GPIO_MODE 0xE600
#define KS8695_GPIO_CTRL 0xE604
#define KS8695_GPIO_DATA 0xE608
/*SWITCH registers offset difinitions*/
#define KS8695_SWITCH_CTRL0 0xE800
#define KS8695_SWITCH_CTRL1 0xE804
#define KS8695_SWITCH_PORT1 0xE808
#define KS8695_SWITCH_PORT2 0xE80C
#define KS8695_SWITCH_PORT3 0xE810
#define KS8695_SWITCH_PORT4 0xE814
#define KS8695_SWITCH_PORT5 0xE818
#define KS8695_SWITCH_AUTO0 0xE81C
#define KS8695_SWITCH_AUTO1 0xE820
#define KS8695_SWITCH_LUE_CTRL 0xE824
#define KS8695_SWITCH_LUE_HIGH 0xE828
#define KS8695_SWITCH_LUE_LOW 0xE82C
#define KS8695_SWITCH_ADVANCED 0xE830
#define KS8695_SWITCH_LPPM12 0xE874
#define KS8695_SWITCH_LPPM34 0xE878
/*host communication registers difinitions*/
#define KS8695_DSCP_HIGH 0xE834
#define KS8695_DSCP_LOW 0xE838
#define KS8695_SWITCH_MAC_HIGH 0xE83C
#define KS8695_SWITCH_MAC_LOW 0xE840
/*miscellaneours registers difinitions*/
#define KS8695_MANAGE_COUNTER 0xE844
#define KS8695_MANAGE_DATA 0xE848
#define KS8695_LAN12_POWERMAGR 0xE84C
#define KS8695_LAN34_POWERMAGR 0xE850
#define KS8695_DEVICE_ID 0xEA00
#define KS8695_REVISION_ID 0xEA04
#define KS8695_MISC_CONTROL 0xEA08
#define KS8695_WAN_CONTROL 0xEA0C
#define KS8695_WAN_POWERMAGR 0xEA10
#define KS8695_WAN_PHY_CONTROL 0xEA14
#define KS8695_WAN_PHY_STATUS 0xEA18
/* bus clock definitions*/
#define KS8695_BUS_CLOCK_125MHZ 0x0
#define KS8695_BUS_CLOCK_100MHZ 0x1
#define KS8695_BUS_CLOCK_62MHZ 0x2
#define KS8695_BUS_CLOCK_50MHZ 0x3
#define KS8695_BUS_CLOCK_41MHZ 0x4
#define KS8695_BUS_CLOCK_33MHZ 0x5
#define KS8695_BUS_CLOCK_31MHZ 0x6
#define KS8695_BUS_CLOCK_25MHZ 0x7
/* -------------------------------------------------------------------------------
* definations for IRQ
* -------------------------------------------------------------------------------*/
#define KS8695_INT_EXT_INT0 2
#define KS8695_INT_EXT_INT1 3
#define KS8695_INT_EXT_INT2 4
#define KS8695_INT_EXT_INT3 5
#define KS8695_INT_TIMERINT0 6
#define KS8695_INT_TIMERINT1 7
#define KS8695_INT_UART_TX 8
#define KS8695_INT_UART_RX 9
#define KS8695_INT_UART_LINE_ERR 10
#define KS8695_INT_UART_MODEMS 11
#define KS8695_INT_LAN_STOP_RX 12
#define KS8695_INT_LAN_STOP_TX 13
#define KS8695_INT_LAN_BUF_RX_STATUS 14
#define KS8695_INT_LAN_BUF_TX_STATUS 15
#define KS8695_INT_LAN_RX_STATUS 16
#define KS8695_INT_LAN_TX_STATUS 17
#define KS8695_INT_HPAN_STOP_RX 18
#define KS8695_INT_HPNA_STOP_TX 19
#define KS8695_INT_HPNA_BUF_RX_STATUS 20
#define KS8695_INT_HPNA_BUF_TX_STATUS 21
#define KS8695_INT_HPNA_RX_STATUS 22
#define KS8695_INT_HPNA_TX_STATUS 23
#define KS8695_INT_BUS_ERROR 24
#define KS8695_INT_WAN_STOP_RX 25
#define KS8695_INT_WAN_STOP_TX 26
#define KS8695_INT_WAN_BUF_RX_STATUS 27
#define KS8695_INT_WAN_BUF_TX_STATUS 28
#define KS8695_INT_WAN_RX_STATUS 29
#define KS8695_INT_WAN_TX_STATUS 30
#define KS8695_INT_UART KS8695_INT_UART_TX
/* -------------------------------------------------------------------------------
* Interrupt bit positions
*
* -------------------------------------------------------------------------------
*/
#define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 )
#define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 )
#define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 )
#define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 )
#define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 )
#define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 )
#define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX )
#define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX )
#define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR )
#define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS )
#define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX )
#define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX )
#define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS )
#define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS )
#define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
#define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
#define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX )
#define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX )
#define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS )
#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS
#define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS )
#define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS )
#define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR )
#define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX )
#define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX )
#define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS )
#define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS )
#define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS )
#define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS )
#define KS8695_SC_VALID_INT 0xFFFFFFFF
#define MAXIRQNUM 31
/*
* Timer definitions
*
* Use timer 1 & 2
* (both run at 25MHz).
*
*/
#define TICKS_PER_uSEC 25
#define mSEC_1 1000
#define mSEC_10 (mSEC_1 * 10)
#endif
/* END */

4
arch/arm/include/asm/arch-lpc32xx/config.h
View file

@ -1,7 +1,7 @@
/*
* Common definitions for LPC32XX board configurations
*
* Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
* Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -9,6 +9,8 @@
#ifndef _LPC32XX_CONFIG_H
#define _LPC32XX_CONFIG_H
#define CONFIG_SYS_GENERIC_BOARD
/* Basic CPU architecture */
#define CONFIG_ARCH_CPU_INIT

15
arch/arm/include/asm/arch-ls102xa/config.h
View file

@ -36,6 +36,7 @@
#define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
@ -61,6 +62,20 @@
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL
#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL
#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL
#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */
/*
* TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
* So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
*/
#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \
CONFIG_SYS_PCIE1_VIRT_ADDR)
#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \
CONFIG_SYS_PCIE2_VIRT_ADDR)
#ifdef CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_VERY_BIG_RAM

40
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
View file

@ -37,6 +37,43 @@
#define DCFG_DCSR_PORCR1 0
/*
* Define default values for some CCSR macros to make header files cleaner
*
* To completely disable CCSR relocation in a board header file, define
* CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
* to a value that is the same as CONFIG_SYS_CCSRBAR.
*/
#ifdef CONFIG_SYS_CCSRBAR_PHYS
#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
#endif
#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
#ifndef CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
#else
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR
#endif
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
CONFIG_SYS_CCSRBAR_PHYS_LOW)
struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
unsigned long freq_systembus;
@ -133,8 +170,7 @@ struct ccsr_scfg {
u32 pex1rdmmsgrqsr;
u32 pex2rdmmsgrqsr;
u32 spimsiclrcr;
u32 pex1mscportsr;
u32 pex2mscportsr;
u32 pexmscportsr[2];
u32 pex2pmwrcr;
u32 resv5[24];
u32 mac1_streamid;

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