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https://github.com/AsahiLinux/u-boot
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ppc4xx: Update esd's common LCD code for 405 boards
- Coding style cleanup (long lines) - Add s1d13505 support - Make some functions return a result code instead of void Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This commit is contained in:
Matthias Fuchs
Stefan Roese
parent
dea6818942
commit
b9233fe5d5
2 changed files with 151 additions and 38 deletions
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@ -44,37 +44,57 @@ void lcd_setup(int lcd, int config)
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/*
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* Set endianess and reset lcd controller 0 (small)
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*/
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */
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/* set reset to low */
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out_be32((void*)GPIO0_OR,
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in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST);
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udelay(10); /* wait 10us */
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if (config == 1)
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
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else
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
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if (config == 1) {
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/* big-endian */
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out_be32((void*)GPIO0_OR,
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in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN);
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} else {
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/* little-endian */
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out_be32((void*)GPIO0_OR,
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in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN);
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}
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udelay(10); /* wait 10us */
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */
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/* set reset to high */
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out_be32((void*)GPIO0_OR,
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in_be32((void*)GPIO0_OR) | CFG_LCD0_RST);
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} else {
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/*
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* Set endianess and reset lcd controller 1 (big)
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*/
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */
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/* set reset to low */
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out_be32((void*)GPIO0_OR,
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in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST);
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udelay(10); /* wait 10us */
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if (config == 1)
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
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else
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
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if (config == 1) {
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/* big-endian */
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out_be32((void*)GPIO0_OR,
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in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN);
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} else {
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/* little-endian */
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out_be32((void*)GPIO0_OR,
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in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN);
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}
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udelay(10); /* wait 10us */
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */
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/* set reset to high */
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out_be32((void*)GPIO0_OR,
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in_be32((void*)GPIO0_OR) | CFG_LCD1_RST);
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}
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/*
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* CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive
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*/
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN);
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}
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#endif /* CFG_LCD_ENDIAN */
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void lcd_bmp(uchar *logo_bmp)
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int lcd_bmp(uchar *logo_bmp)
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{
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int i;
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uchar *ptr;
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@ -99,13 +119,18 @@ void lcd_bmp(uchar *logo_bmp)
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len = CFG_VIDEO_LOGO_MAX_SIZE;
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dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE);
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if (dst == NULL) {
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printf("Error: malloc in gunzip failed!\n");
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return;
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printf("Error: malloc for gunzip failed!\n");
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return 1;
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}
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if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE,
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(uchar *)logo_bmp, &len) != 0) {
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free(dst);
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return 1;
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}
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if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
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printf("Image could be truncated"
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" (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
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}
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if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0)
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return;
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if (len == CFG_VIDEO_LOGO_MAX_SIZE)
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printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
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/*
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* Check for bmp mark 'BM'
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@ -113,7 +138,7 @@ void lcd_bmp(uchar *logo_bmp)
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if (*(ushort *)dst != 0x424d) {
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printf("LCD: Unknown image format!\n");
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free(dst);
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return;
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return 1;
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}
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} else {
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/*
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@ -150,7 +175,7 @@ void lcd_bmp(uchar *logo_bmp)
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printf("LCD: Unknown bpp (%d) im image!\n", bpp);
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if ((dst != NULL) && (dst != (uchar *)logo_bmp))
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free(dst);
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return;
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return 1;
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}
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printf(" (%d*%d, %dbpp)\n", width, height, bpp);
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@ -180,23 +205,28 @@ void lcd_bmp(uchar *logo_bmp)
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if (bpp == 24) {
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for (x = 0; x < width; x++) {
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/*
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* Generate epson 16bpp fb-format from 24bpp image
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* Generate epson 16bpp fb-format
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* from 24bpp image
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*/
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b = *bmp++ >> 3;
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g = *bmp++ >> 2;
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r = *bmp++ >> 3;
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val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f);
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val = ((r & 0x1f) << 11) |
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((g & 0x3f) << 5) |
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(b & 0x1f);
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*ptr2++ = val;
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}
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} else if (bpp == 8) {
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for (x = 0; x < line_size; x++) {
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/* query rgb value from palette */
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ptr = (unsigned char *)(dst + 14 + 40) ;
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ptr = (unsigned char *)(dst + 14 + 40);
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ptr += (*bmp++) << 2;
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b = *ptr++ >> 3;
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g = *ptr++ >> 2;
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r = *ptr++ >> 3;
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val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f);
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val = ((r & 0x1f) << 11) |
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((g & 0x3f) << 5) |
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(b & 0x1f);
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*ptr2++ = val;
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}
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}
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@ -208,11 +238,12 @@ void lcd_bmp(uchar *logo_bmp)
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if ((dst != NULL) && (dst != (uchar *)logo_bmp))
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free(dst);
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return 0;
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}
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void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
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uchar *logo_bmp, ulong len)
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int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
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uchar *logo_bmp, ulong len)
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{
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int i;
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ushort s1dReg;
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@ -263,8 +294,22 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
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lcd_reg += 0x10000; /* add offset for 705 regs */
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puts("LCD: S1D13705");
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} else {
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puts("LCD: No controller detected!\n");
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return;
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out_8(&lcd_reg[0x1a], 0x00);
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udelay(1000);
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if (in_8(&lcd_reg[1]) == 0x0c) {
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/*
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* S1D13505 detected
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*/
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reg_byte_swap = TRUE;
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palette_index = 0x25;
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palette_value = 0x27;
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lcd_depth = 16;
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puts("LCD: S1D13505");
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} else {
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puts("LCD: No controller detected!\n");
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return 1;
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}
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}
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/*
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@ -279,7 +324,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
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s1dReg &= ~0x0001;
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}
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s1dValue = regs[i].Value;
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lcd_reg[s1dReg] = s1dValue;
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out_8(&lcd_reg[s1dReg], s1dValue);
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}
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/*
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@ -291,15 +336,15 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
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/*
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* Display bmp image
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*/
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lcd_bmp(logo_bmp);
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return lcd_bmp(logo_bmp);
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}
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#if defined(CONFIG_VIDEO_SM501)
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int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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ulong addr;
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#ifdef CONFIG_VIDEO_SM501
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char *str;
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#endif
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if (argc != 2) {
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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@ -307,19 +352,22 @@ int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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addr = simple_strtoul(argv[1], NULL, 16);
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#ifdef CONFIG_VIDEO_SM501
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str = getenv("bd_type");
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if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) {
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/*
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* SM501 available, use standard bmp command
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*/
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return (video_display_bitmap(addr, 0, 0));
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return video_display_bitmap(addr, 0, 0);
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} else {
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/*
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* No SM501 available, use esd epson bmp command
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*/
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lcd_bmp((uchar *)addr);
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return 0;
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return lcd_bmp((uchar *)addr);
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}
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#else
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return lcd_bmp((uchar *)addr);
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#endif
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}
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U_BOOT_CMD(
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@ -327,4 +375,3 @@ U_BOOT_CMD(
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"esdbmp - display BMP image\n",
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"<imageAddr> - display image\n"
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);
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#endif
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66
board/esd/common/s1d13505_640_480_16bpp.h
Normal file
66
board/esd/common/s1d13505_640_480_16bpp.h
Normal file
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@ -0,0 +1,66 @@
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/*
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* (C) Copyright 2008
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Panel: 640x480 50Hz TFT Single 18-bit (PCLK=20.000 MHz)
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* Memory: DRAM (MCLK=40.000 MHz)
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*/
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static S1D_REGS regs_13505_640_480_16bpp[] =
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{
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{0x1B,0x00}, /* Miscellaneous Register */
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{0x23,0x20}, /* Performance Enhancement Register 1 */
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{0x01,0x30}, /* Memory Configuration Register */
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{0x22,0x24}, /* Performance Enhancement Register 0 */
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{0x02,0x25}, /* Panel Type Register */
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{0x03,0x00}, /* MOD Rate Register */
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{0x04,0x4F}, /* Horizontal Display Width Register */
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{0x05,0x0c}, /* Horizontal Non-Display Period Register */
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{0x06,0x00}, /* HRTC/FPLINE Start Position Register */
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{0x07,0x01}, /* HRTC/FPLINE Pulse Width Register */
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{0x08,0xDF}, /* Vertical Display Height Register 0 */
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{0x09,0x01}, /* Vertical Display Height Register 1 */
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{0x0A,0x3E}, /* Vertical Non-Display Period Register */
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{0x0B,0x00}, /* VRTC/FPFRAME Start Position Register */
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{0x0C,0x01}, /* VRTC/FPFRAME Pulse Width Register */
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{0x0E,0xFF}, /* Screen 1 Line Compare Register 0 */
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{0x0F,0x03}, /* Screen 1 Line Compare Register 1 */
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{0x10,0x00}, /* Screen 1 Display Start Address Register 0 */
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{0x11,0x00}, /* Screen 1 Display Start Address Register 1 */
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{0x12,0x00}, /* Screen 1 Display Start Address Register 2 */
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{0x13,0x00}, /* Screen 2 Display Start Address Register 0 */
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{0x14,0x00}, /* Screen 2 Display Start Address Register 1 */
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{0x15,0x00}, /* Screen 2 Display Start Address Register 2 */
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{0x16,0x80}, /* Memory Address Offset Register 0 */
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{0x17,0x02}, /* Memory Address Offset Register 1 */
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{0x18,0x00}, /* Pixel Panning Register */
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{0x19,0x01}, /* Clock Configuration Register */
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{0x1A,0x00}, /* Power Save Configuration Register */
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{0x1C,0x00}, /* MD Configuration Readback Register 0 */
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{0x1E,0x06}, /* General IO Pins Configuration Register 0 */
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{0x1F,0x00}, /* General IO Pins Configuration Register 1 */
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{0x20,0x00}, /* General IO Pins Control Register 0 */
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{0x21,0x00}, /* General IO Pins Control Register 1 */
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{0x23,0x20}, /* Performance Enhancement Register 1 */
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{0x0D,0x15}, /* Display Mode Register */
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};
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