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CLK: HSDK: Check for PLL bypass firstly

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Pll bypass has priority over enable/disable.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
Eugeniy Paltsev 2020-01-29 14:08:29 +03:00 committed by Alexey Brodkin
parent 95f7103f94
commit b8f3ce0137
1 changed files with 4 additions and 4 deletions
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8
drivers/clk/clk-hsdk-cgu.c
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@ -377,14 +377,14 @@ static ulong pll_get(struct clk *sclk)
pr_debug("current configurarion: %#x\n", val);
/* Check if PLL is disabled */
if (val & CGU_PLL_CTRL_PD)
return 0;
/* Check if PLL is bypassed */
if (val & CGU_PLL_CTRL_BYPASS)
return PARENT_RATE;
/* Check if PLL is disabled */
if (val & CGU_PLL_CTRL_PD)
return 0;
/* input divider = reg.idiv + 1 */
idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
/* fb divider = 2*(reg.fbdiv + 1) */