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https://github.com/AsahiLinux/u-boot
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dm: pci: add Freescale PowerPC PCIe driver
Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Hou Zhiqiang
Prabhakar Kushwaha
parent
13c5e5bd6a
commit
b89e3d9250
5 changed files with 725 additions and 0 deletions
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@ -60,6 +60,14 @@ config PCIE_DW_MVEBU
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Armada-8K SoCs. The PCIe controller on Armada-8K is based on
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DesignWare hardware.
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config PCIE_FSL
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bool "FSL PowerPC PCIe support"
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depends on DM_PCI
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help
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Say Y here if you want to enable PCIe controller support on FSL
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PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.
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This driver does not support SRIO_PCIE_BOOT feature.
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config PCI_RCAR_GEN2
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bool "Renesas RCar Gen2 PCIe driver"
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depends on DM_PCI
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@ -31,6 +31,7 @@ obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
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obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
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obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
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obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
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obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o
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obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
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obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
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obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
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610
drivers/pci/pcie_fsl.c
Normal file
610
drivers/pci/pcie_fsl.c
Normal file
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@ -0,0 +1,610 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Copyright 2019 NXP
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*
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* PCIe DM U-Boot driver for Freescale PowerPC SoCs
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* Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <mapmem.h>
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#include <pci.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_serdes.h>
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#include <asm/io.h>
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#include "pcie_fsl.h"
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LIST_HEAD(fsl_pcie_list);
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static int fsl_pcie_link_up(struct fsl_pcie *pcie);
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static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
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{
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struct udevice *bus = pcie->bus;
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if (!pcie->enabled)
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return -ENXIO;
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if (PCI_BUS(bdf) < bus->seq)
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return -EINVAL;
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if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode))
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return -EINVAL;
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if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))
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return -EINVAL;
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if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))
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return -EINVAL;
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return 0;
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}
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static int fsl_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct fsl_pcie *pcie = dev_get_priv(bus);
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ccsr_fsl_pci_t *regs = pcie->regs;
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u32 val;
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if (fsl_pcie_addr_valid(pcie, bdf)) {
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*valuep = pci_get_ff(size);
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return 0;
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}
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bdf = bdf - PCI_BDF(bus->seq, 0, 0);
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val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
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out_be32(®s->cfg_addr, val);
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sync();
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switch (size) {
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case PCI_SIZE_8:
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*valuep = in_8((u8 *)®s->cfg_data + (offset & 3));
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break;
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case PCI_SIZE_16:
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*valuep = in_le16((u16 *)((u8 *)®s->cfg_data +
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(offset & 2)));
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break;
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case PCI_SIZE_32:
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*valuep = in_le32(®s->cfg_data);
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break;
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}
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return 0;
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}
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static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct fsl_pcie *pcie = dev_get_priv(bus);
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ccsr_fsl_pci_t *regs = pcie->regs;
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u32 val;
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u8 val_8;
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u16 val_16;
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u32 val_32;
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if (fsl_pcie_addr_valid(pcie, bdf))
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return 0;
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bdf = bdf - PCI_BDF(bus->seq, 0, 0);
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val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
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out_be32(®s->cfg_addr, val);
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sync();
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switch (size) {
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case PCI_SIZE_8:
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val_8 = value;
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out_8((u8 *)®s->cfg_data + (offset & 3), val_8);
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break;
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case PCI_SIZE_16:
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val_16 = value;
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out_le16((u16 *)((u8 *)®s->cfg_data + (offset & 2)), val_16);
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break;
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case PCI_SIZE_32:
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val_32 = value;
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out_le32(®s->cfg_data, val_32);
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break;
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}
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return 0;
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}
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static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
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ulong *valuep, enum pci_size_t size)
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{
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int ret;
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struct udevice *bus = pcie->bus;
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ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),
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offset, valuep, size);
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return ret;
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}
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static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
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ulong value, enum pci_size_t size)
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{
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struct udevice *bus = pcie->bus;
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return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),
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offset, value, size);
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}
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static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
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u8 *valuep)
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{
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ulong val;
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int ret;
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ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
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*valuep = val;
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return ret;
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}
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static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
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u16 *valuep)
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{
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ulong val;
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int ret;
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ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
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*valuep = val;
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return ret;
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}
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static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
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u32 *valuep)
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{
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ulong val;
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int ret;
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ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
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*valuep = val;
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return ret;
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}
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static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
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u8 value)
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{
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return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
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}
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static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
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u16 value)
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{
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return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
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}
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static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
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u32 value)
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{
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return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
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}
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static int fsl_pcie_link_up(struct fsl_pcie *pcie)
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{
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ccsr_fsl_pci_t *regs = pcie->regs;
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u16 ltssm;
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if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
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ltssm = (in_be32(®s->pex_csr0)
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& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
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return ltssm == LTSSM_L0_REV3;
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}
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fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm);
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return ltssm == LTSSM_L0;
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}
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static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
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{
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u8 header_type;
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fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);
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return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
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}
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static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
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{
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struct pci_region *io, *mem, *pref;
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pci_get_regions(pcie->bus, &io, &mem, &pref);
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if (mem)
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set_next_law(mem->phys_start,
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law_size_bits(mem->size),
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pcie->law_trgt_if);
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if (io)
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set_next_law(io->phys_start,
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law_size_bits(io->size),
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pcie->law_trgt_if);
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return 0;
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}
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static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
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{
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ccsr_fsl_pci_t *regs = pcie->regs;
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if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
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setbits_be32(®s->config, FSL_PCIE_V3_CFG_RDY);
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return;
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}
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fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
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}
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static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
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int type, u64 phys, u64 bus_addr,
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pci_size_t size)
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{
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ccsr_fsl_pci_t *regs = pcie->regs;
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pot_t *po = ®s->pot[idx];
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u32 war, sz;
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if (idx < 0)
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return -EINVAL;
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out_be32(&po->powbar, phys >> 12);
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out_be32(&po->potar, bus_addr >> 12);
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#ifdef CONFIG_SYS_PCI_64BIT
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out_be32(&po->potear, bus_addr >> 44);
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#else
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out_be32(&po->potear, 0);
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#endif
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sz = (__ilog2_u64((u64)size) - 1);
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war = POWAR_EN | sz;
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if (type == PCI_REGION_IO)
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war |= POWAR_IO_READ | POWAR_IO_WRITE;
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else
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war |= POWAR_MEM_READ | POWAR_MEM_WRITE;
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out_be32(&po->powar, war);
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return 0;
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}
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static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
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bool pf, u64 phys, u64 bus_addr,
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pci_size_t size)
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{
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ccsr_fsl_pci_t *regs = pcie->regs;
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pit_t *pi = ®s->pit[idx];
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u32 sz = (__ilog2_u64(size) - 1);
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u32 flag = PIWAR_LOCAL;
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if (idx < 0)
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return -EINVAL;
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out_be32(&pi->pitar, phys >> 12);
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out_be32(&pi->piwbar, bus_addr >> 12);
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#ifdef CONFIG_SYS_PCI_64BIT
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out_be32(&pi->piwbear, bus_addr >> 44);
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#else
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out_be32(&pi->piwbear, 0);
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#endif
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if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A005434))
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flag = 0;
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flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
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if (pf)
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flag |= PIWAR_PF;
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out_be32(&pi->piwar, flag | sz);
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return 0;
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}
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static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
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{
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struct pci_region *io, *mem, *pref;
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int idx = 1; /* skip 0 */
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pci_get_regions(pcie->bus, &io, &mem, &pref);
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if (io)
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/* ATU : OUTBOUND : IO */
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fsl_pcie_setup_outbound_win(pcie, idx++,
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PCI_REGION_IO,
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io->phys_start,
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io->bus_start,
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io->size);
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if (mem)
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/* ATU : OUTBOUND : MEM */
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fsl_pcie_setup_outbound_win(pcie, idx++,
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PCI_REGION_MEM,
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mem->phys_start,
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mem->bus_start,
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mem->size);
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return 0;
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}
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static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
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{
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phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
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pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
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u64 sz = min((u64)gd->ram_size, (1ull << 32));
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pci_size_t pci_sz;
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int idx;
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if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
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idx = 2;
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else
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idx = 3;
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pci_sz = 1ull << __ilog2_u64(sz);
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dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
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(u64)bus_start, (u64)phys_start, (u64)sz);
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/* if we aren't an exact power of two match, pci_sz is smaller
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* round it up to the next power of two. We report the actual
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* size to pci region tracking.
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*/
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if (pci_sz != sz)
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sz = 2ull << __ilog2_u64(sz);
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fsl_pcie_setup_inbound_win(pcie, idx--, true,
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CONFIG_SYS_PCI_MEMORY_PHYS,
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CONFIG_SYS_PCI_MEMORY_BUS, sz);
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#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
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/*
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* On 64-bit capable systems, set up a mapping for all of DRAM
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* in high pci address space.
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*/
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pci_sz = 1ull << __ilog2_u64(gd->ram_size);
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/* round up to the next largest power of two */
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if (gd->ram_size > pci_sz)
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pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
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dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
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(u64)CONFIG_SYS_PCI64_MEMORY_BUS,
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(u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
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fsl_pcie_setup_inbound_win(pcie, idx--, true,
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CONFIG_SYS_PCI_MEMORY_PHYS,
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CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
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#endif
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return 0;
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}
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static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
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{
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fsl_pcie_setup_outbound_wins(pcie);
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fsl_pcie_setup_inbound_wins(pcie);
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return 0;
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}
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static int fsl_pcie_init_port(struct fsl_pcie *pcie)
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{
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ccsr_fsl_pci_t *regs = pcie->regs;
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u32 val_32;
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u16 val_16;
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fsl_pcie_init_atmu(pcie);
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if (IS_ENABLED(CONFIG_FSL_PCIE_DISABLE_ASPM)) {
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val_32 = 0;
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fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
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val_32 &= ~0x03;
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fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
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udelay(1);
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}
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if (IS_ENABLED(CONFIG_FSL_PCIE_RESET)) {
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u16 ltssm;
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int i;
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if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
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/* assert PCIe reset */
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setbits_be32(®s->pdb_stat, 0x08000000);
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(void)in_be32(®s->pdb_stat);
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udelay(1000);
|
||||
/* clear PCIe reset */
|
||||
clrbits_be32(®s->pdb_stat, 0x08000000);
|
||||
asm("sync;isync");
|
||||
for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
|
||||
udelay(1000);
|
||||
} else {
|
||||
fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm);
|
||||
if (ltssm == 1) {
|
||||
/* assert PCIe reset */
|
||||
setbits_be32(®s->pdb_stat, 0x08000000);
|
||||
(void)in_be32(®s->pdb_stat);
|
||||
udelay(100);
|
||||
/* clear PCIe reset */
|
||||
clrbits_be32(®s->pdb_stat, 0x08000000);
|
||||
asm("sync;isync");
|
||||
for (i = 0; i < 100 &&
|
||||
!fsl_pcie_link_up(pcie); i++)
|
||||
udelay(1000);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_SYS_P4080_ERRATUM_PCIE_A003) &&
|
||||
!fsl_pcie_link_up(pcie)) {
|
||||
serdes_corenet_t *srds_regs;
|
||||
|
||||
srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
|
||||
val_32 = in_be32(&srds_regs->srdspccr0);
|
||||
|
||||
if ((val_32 >> 28) == 3) {
|
||||
int i;
|
||||
|
||||
out_be32(&srds_regs->srdspccr0, 2 << 28);
|
||||
setbits_be32(®s->pdb_stat, 0x08000000);
|
||||
in_be32(®s->pdb_stat);
|
||||
udelay(100);
|
||||
clrbits_be32(®s->pdb_stat, 0x08000000);
|
||||
asm("sync;isync");
|
||||
for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
|
||||
udelay(1000);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* The Read-Only Write Enable bit defaults to 1 instead of 0.
|
||||
* Set to 0 to protect the read-only registers.
|
||||
*/
|
||||
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A007815))
|
||||
clrbits_be32(®s->dbi_ro_wr_en, 0x01);
|
||||
|
||||
/*
|
||||
* Enable All Error Interrupts except
|
||||
* - Master abort (pci)
|
||||
* - Master PERR (pci)
|
||||
* - ICCA (PCIe)
|
||||
*/
|
||||
out_be32(®s->peer, ~0x20140);
|
||||
|
||||
/* set URR, FER, NFER (but not CER) */
|
||||
fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
|
||||
val_32 |= 0xf000e;
|
||||
fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);
|
||||
|
||||
/* Clear all error indications */
|
||||
out_be32(®s->pme_msg_det, 0xffffffff);
|
||||
out_be32(®s->pme_msg_int_en, 0xffffffff);
|
||||
out_be32(®s->pedr, 0xffffffff);
|
||||
|
||||
fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
|
||||
if (val_16)
|
||||
fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);
|
||||
|
||||
fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
|
||||
if (val_16)
|
||||
fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
|
||||
{
|
||||
ccsr_fsl_pci_t *regs = pcie->regs;
|
||||
u32 val;
|
||||
|
||||
setbits_be32(®s->dbi_ro_wr_en, 0x01);
|
||||
fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val);
|
||||
val &= 0xff;
|
||||
val |= PCI_CLASS_BRIDGE_PCI << 16;
|
||||
fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val);
|
||||
clrbits_be32(®s->dbi_ro_wr_en, 0x01);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
|
||||
{
|
||||
return fsl_pcie_fixup_classcode(pcie);
|
||||
}
|
||||
|
||||
static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
|
||||
{
|
||||
fsl_pcie_config_ready(pcie);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_pcie_probe(struct udevice *dev)
|
||||
{
|
||||
struct fsl_pcie *pcie = dev_get_priv(dev);
|
||||
ccsr_fsl_pci_t *regs = pcie->regs;
|
||||
u16 val_16;
|
||||
|
||||
pcie->bus = dev;
|
||||
pcie->block_rev = in_be32(®s->block_rev1);
|
||||
|
||||
list_add(&pcie->list, &fsl_pcie_list);
|
||||
pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
|
||||
if (!pcie->enabled) {
|
||||
printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
fsl_pcie_setup_law(pcie);
|
||||
|
||||
pcie->mode = fsl_pcie_is_agent(pcie);
|
||||
|
||||
fsl_pcie_init_port(pcie);
|
||||
|
||||
printf("PCIe%d: %s ", pcie->idx, dev->name);
|
||||
|
||||
if (pcie->mode) {
|
||||
printf("Endpoint");
|
||||
fsl_pcie_init_ep(pcie);
|
||||
} else {
|
||||
printf("Root Complex");
|
||||
fsl_pcie_init_rc(pcie);
|
||||
}
|
||||
|
||||
if (!fsl_pcie_link_up(pcie)) {
|
||||
printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
|
||||
return 0;
|
||||
}
|
||||
|
||||
fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
|
||||
printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
|
||||
{
|
||||
struct fsl_pcie *pcie = dev_get_priv(dev);
|
||||
int ret;
|
||||
|
||||
pcie->regs = dev_remap_addr(dev);
|
||||
if (!pcie->regs) {
|
||||
pr_err("\"reg\" resource not found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
|
||||
if (ret < 0) {
|
||||
pr_err("\"law_trgt_if\" not found\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pcie->idx = (dev_read_addr(dev) - 0xffe240000) / 0x10000;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_pci_ops fsl_pcie_ops = {
|
||||
.read_config = fsl_pcie_read_config,
|
||||
.write_config = fsl_pcie_write_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id fsl_pcie_ids[] = {
|
||||
{ .compatible = "fsl,pcie-t2080" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(fsl_pcie) = {
|
||||
.name = "fsl_pcie",
|
||||
.id = UCLASS_PCI,
|
||||
.of_match = fsl_pcie_ids,
|
||||
.ops = &fsl_pcie_ops,
|
||||
.ofdata_to_platdata = fsl_pcie_ofdata_to_platdata,
|
||||
.probe = fsl_pcie_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct fsl_pcie),
|
||||
};
|
||||
56
drivers/pci/pcie_fsl.h
Normal file
56
drivers/pci/pcie_fsl.h
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*
|
||||
* PCIe DM U-Boot driver for Freescale PowerPC SoCs
|
||||
* Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
||||
*/
|
||||
|
||||
#ifndef _PCIE_FSL_H_
|
||||
#define _PCIE_FSL_H_
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
|
||||
#define FSL_PCIE_CAP_ID 0x70
|
||||
#else
|
||||
#define FSL_PCIE_CAP_ID 0x4c
|
||||
#endif
|
||||
/* PCIe Device Control Register */
|
||||
#define PCI_DCR (FSL_PCIE_CAP_ID + 0x08)
|
||||
/* PCIe Device Status Register */
|
||||
#define PCI_DSR (FSL_PCIE_CAP_ID + 0x0a)
|
||||
/* PCIe Link Control Register */
|
||||
#define PCI_LCR (FSL_PCIE_CAP_ID + 0x10)
|
||||
/* PCIe Link Status Register */
|
||||
#define PCI_LSR (FSL_PCIE_CAP_ID + 0x12)
|
||||
|
||||
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
|
||||
#define CONFIG_SYS_PCI_MEMORY_BUS 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
|
||||
#define CONFIG_SYS_PCI_MEMORY_PHYS 0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
|
||||
#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024)
|
||||
#endif
|
||||
|
||||
#define PEX_CSR0_LTSSM_MASK 0xFC
|
||||
#define PEX_CSR0_LTSSM_SHIFT 2
|
||||
#define LTSSM_L0_REV3 0x11
|
||||
#define LTSSM_L0 0x16
|
||||
|
||||
struct fsl_pcie {
|
||||
int idx;
|
||||
struct udevice *bus;
|
||||
void __iomem *regs;
|
||||
u32 law_trgt_if; /* LAW target ID */
|
||||
u32 block_rev; /* IP block revision */
|
||||
bool mode; /* RC&EP mode flag */
|
||||
bool enabled; /* Enable status */
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
extern struct list_head fsl_pcie_list;
|
||||
|
||||
#endif /* _PCIE_FSL_H_ */
|
||||
50
drivers/pci/pcie_fsl_fixup.c
Normal file
50
drivers/pci/pcie_fsl_fixup.c
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*
|
||||
* PCIe Kernel DT fixup of DM U-Boot driver for Freescale PowerPC SoCs
|
||||
* Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
#include <dm.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/fsl_pci.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include "pcie_fsl.h"
|
||||
|
||||
static void ft_fsl_pcie_setup(void *blob, struct fsl_pcie *pcie)
|
||||
{
|
||||
struct pci_controller *hose = dev_get_uclass_priv(pcie->bus);
|
||||
fdt_addr_t regs_addr;
|
||||
int off;
|
||||
|
||||
regs_addr = dev_read_addr(pcie->bus);
|
||||
off = fdt_node_offset_by_compat_reg(blob, FSL_PCIE_COMPAT, regs_addr);
|
||||
if (off < 0) {
|
||||
printf("%s: Fail to find PCIe node@0x%pa\n",
|
||||
FSL_PCIE_COMPAT, ®s_addr);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!hose || !pcie->enabled)
|
||||
fdt_del_node(blob, off);
|
||||
else
|
||||
fdt_pci_dma_ranges(blob, off, hose);
|
||||
}
|
||||
|
||||
/* Fixup Kernel DT for PCIe */
|
||||
void pci_of_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
struct fsl_pcie *pcie;
|
||||
|
||||
list_for_each_entry(pcie, &fsl_pcie_list, list)
|
||||
ft_fsl_pcie_setup(blob, pcie);
|
||||
}
|
||||
|
||||
#else
|
||||
void pci_of_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in a new issue