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omap3: mem: Comment enable_gpmc_cs_config more

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Expand the "enable the config" comment to explain what the bit shifts
are and define out two of the magic numbers.

Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Tom Rini 2011-11-18 12:47:58 +00:00 • committed by Albert ARIBAUD
parent b609009801
commit b7eb9e7895
2 changed files with 13 additions and 3 deletions
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12
arch/arm/cpu/armv7/omap3/mem.c
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@ -105,9 +105,15 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
writel(gpmc_config[3], &cs->config4); writel(gpmc_config[3], &cs->config4);
writel(gpmc_config[4], &cs->config5); writel(gpmc_config[4], &cs->config5);
writel(gpmc_config[5], &cs->config6); writel(gpmc_config[5], &cs->config6);
/* Enable the config */
writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | /*
(1 << 6)), &cs->config7); * Enable the config. size is the CS size and goes in
* bits 11:8. We set bit 6 to enable this CS and the base
* address goes into bits 5:0.
*/
writel((size << 8) | (GPMC_CS_ENABLE << 6) |
((base >> 24) & GPMC_BASEADDR_MASK),
&cs->config7);
sdelay(2000); sdelay(2000);
} }

4
arch/arm/include/asm/arch-omap3/mem.h
View file

@ -259,6 +259,10 @@ enum {
#define GPMC_SIZE_32M 0xE #define GPMC_SIZE_32M 0xE
#define GPMC_SIZE_16M 0xF #define GPMC_SIZE_16M 0xF
#define GPMC_BASEADDR_MASK 0x3F
#define GPMC_CS_ENABLE 0x1
#define SMNAND_GPMC_CONFIG1 0x00000800 #define SMNAND_GPMC_CONFIG1 0x00000800
#define SMNAND_GPMC_CONFIG2 0x00141400 #define SMNAND_GPMC_CONFIG2 0x00141400
#define SMNAND_GPMC_CONFIG3 0x00141400 #define SMNAND_GPMC_CONFIG3 0x00141400