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Merge branch 'master' of git://git.denx.de/u-boot-tegra

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Conflicts:
	README

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2015-03-10 19:09:18 -04:00
commit b79dadf846
53 changed files with 1533 additions and 380 deletions
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119
README
View file

@ -690,6 +690,125 @@ The following options need to be configured:
exists, unlike the similar options in the Linux kernel. Do not
set these options unless they apply!
- Tegra SoC options:
CONFIG_TEGRA_SUPPORT_NON_SECURE
Support executing U-Boot in non-secure (NS) mode. Certain
impossible actions will be skipped if the CPU is in NS mode,
such as ARM architectural timer initialization.
- Driver Model
Driver model is a new framework for devices in U-Boot
introduced in early 2014. U-Boot is being progressively
moved over to this. It offers a consistent device structure,
supports grouping devices into classes and has built-in
handling of platform data and device tree.
To enable transition to driver model in a relatively
painful fashion, each subsystem can be independently
switched between the legacy/ad-hoc approach and the new
driver model using the options below. Also, many uclass
interfaces include compatibility features which may be
removed once the conversion of that subsystem is complete.
As a result, the API provided by the subsystem may in fact
not change with driver model.
See doc/driver-model/README.txt for more information.
CONFIG_DM
Enable driver model. This brings in the core support,
including scanning of platform data on start-up. If
CONFIG_OF_CONTROL is enabled, the device tree will be
scanned also when available.
CONFIG_CMD_DM
Enable driver model test commands. These allow you to print
out the driver model tree and the uclasses.
CONFIG_DM_DEMO
Enable some demo devices and the 'demo' command. These are
really only useful for playing around while trying to
understand driver model in sandbox.
CONFIG_SPL_DM
Enable driver model in SPL. You will need to provide a
suitable malloc() implementation. If you are not using the
full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
must provide CONFIG_SYS_MALLOC_F_LEN to set the size.
In most cases driver model will only allocate a few uclasses
and devices in SPL, so 1KB should be enable. See
CONFIG_SYS_MALLOC_F_LEN for more details on how to enable
it.
CONFIG_DM_SERIAL
Enable driver model for serial. This replaces
drivers/serial/serial.c with the serial uclass, which
implements serial_putc() etc. The uclass interface is
defined in include/serial.h.
CONFIG_DM_GPIO
Enable driver model for GPIO access. The standard GPIO
interface (gpio_get_value(), etc.) is then implemented by
the GPIO uclass. Drivers provide methods to query the
particular GPIOs that they provide. The uclass interface
is defined in include/asm-generic/gpio.h.
CONFIG_DM_SPI
Enable driver model for SPI. The SPI slave interface
(spi_setup_slave(), spi_xfer(), etc.) is then implemented by
the SPI uclass. Drivers provide methods to access the SPI
buses that they control. The uclass interface is defined in
include/spi.h. The existing spi_slave structure is attached
as 'parent data' to every slave on each bus. Slaves
typically use driver-private data instead of extending the
spi_slave structure.
CONFIG_DM_SPI_FLASH
Enable driver model for SPI flash. This SPI flash interface
(spi_flash_probe(), spi_flash_write(), etc.) is then
implemented by the SPI flash uclass. There is one standard
SPI flash driver which knows how to probe most chips
supported by U-Boot. The uclass interface is defined in
include/spi_flash.h, but is currently fully compatible
with the old interface to avoid confusion and duplication
during the transition parent. SPI and SPI flash must be
enabled together (it is not possible to use driver model
for one and not the other).
CONFIG_DM_CROS_EC
Enable driver model for the Chrome OS EC interface. This
allows the cros_ec SPI driver to operate with CONFIG_DM_SPI
but otherwise makes few changes. Since cros_ec also supports
I2C and LPC (which don't support driver model yet), a full
conversion is not yet possible.
** Code size options: The following options are enabled by
default except in SPL. Enable them explicitly to get these
features in SPL.
CONFIG_DM_WARN
Enable the dm_warn() function. This can use up quite a bit
of space for its strings.
CONFIG_DM_STDIO
Enable registering a serial device with the stdio library.
CONFIG_DM_DEVICE_REMOVE
Enable removing of devices.
- Linux Kernel Interface:
CONFIG_CLOCKS_IN_MHZ

61
arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds Normal file
View file

@ -0,0 +1,61 @@
/*
* (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* Based on:
*
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
* Tom Cubie <tangliang@allwinnertech.com>
*
* Based on omap-common/u-boot-spl.lds:
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
* Aneesh V <aneesh@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_SIZE }
MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
.text :
{
__start = .;
*(.vectors)
CPUDIR/start.o (.text)
*(.text*)
} > .nor
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.nor
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.nor
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
} > .nor
. = ALIGN(4);
__image_copy_end = .;
_end = .;
.bss :
{
. = ALIGN(4);
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_end = .;
} > .bss
}

9
arch/arm/cpu/armv7/virt-v7.c
View file

@ -112,13 +112,20 @@ int armv7_init_nonsec(void)
for (i = 1; i <= itlinesnr; i++)
writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
/*
* Relocate secure section before any cpu runs in secure ram.
* smp_kick_all_cpus may enable other cores and runs into secure
* ram, so need to relocate secure section before enabling other
* cores.
*/
relocate_secure_section();
#ifndef CONFIG_ARMV7_PSCI
smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
smp_kick_all_cpus();
#endif
/* call the non-sec switching code on this CPU also */
relocate_secure_section();
secure_ram_addr(_nonsec_init)();
return 0;
}

45
arch/arm/cpu/armv8/start.S
View file

@ -67,6 +67,9 @@ reset:
msr cpacr_el1, x0 /* Enable FP/SIMD */
0:
/* Apply ARM core specific erratas */
bl apply_core_errata
/*
* Cache/BPB/TLB Invalidate
* i-cache is invalidated before enabled in icache_enable()
@ -97,6 +100,48 @@ master_cpu:
/*-----------------------------------------------------------------------*/
WEAK(apply_core_errata)
mov x29, lr /* Save LR */
/* For now, we support Cortex-A57 specific errata only */
/* Check if we are running on a Cortex-A57 core */
branch_if_a57_core x0, apply_a57_core_errata
0:
mov lr, x29 /* Restore LR */
ret
apply_a57_core_errata:
#ifdef CONFIG_ARM_ERRATA_828024
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* Disable non-allocate hint of w-b-n-a memory type */
mov x0, #0x1 << 49
/* Disable write streaming no L1-allocate threshold */
mov x0, #0x3 << 25
/* Disable write streaming no-allocate threshold */
mov x0, #0x3 << 27
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
#ifdef CONFIG_ARM_ERRATA_826974
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* Disable speculative load execution ahead of a DMB */
mov x0, #0x1 << 59
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
#ifdef CONFIG_ARM_ERRATA_833069
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* Disable Enable Invalidates of BTB bit */
and x0, x0, #0xE
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
b 0b
ENDPROC(apply_core_errata)
/*-----------------------------------------------------------------------*/
WEAK(lowlevel_init)
mov x29, lr /* Save LR */

195
arch/arm/cpu/tegra210-common/pinmux.c Normal file
View file

@ -0,0 +1,195 @@
/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/pinmux.h>
#define PIN(pin, f0, f1, f2, f3) \
{ \
.funcs = { \
PMUX_FUNC_##f0, \
PMUX_FUNC_##f1, \
PMUX_FUNC_##f2, \
PMUX_FUNC_##f3, \
}, \
}
#define PIN_RESERVED {}
static const struct pmux_pingrp_desc tegra210_pingroups[] = {
/* pin, f0, f1, f2, f3 */
/* Offset 0x3000 */
PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3),
PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3),
PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3),
PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3),
PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3),
PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3),
PIN_RESERVED,
/* Offset 0x301c */
PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN_RESERVED,
/* Offset 0x3038 */
PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3),
PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3),
PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3),
PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3),
PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3),
PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3),
PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3),
PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3),
PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3),
PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3),
PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3),
PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3),
PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3),
PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3),
PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3),
PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3),
PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3),
PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3),
PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3),
PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3),
PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3),
PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3),
PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3),
PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3),
PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3),
PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3),
PIN_RESERVED,
/* Offset 0x30a4 */
PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3),
PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3),
PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3),
PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3),
PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3),
PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3),
PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3),
PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3),
PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3),
PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3),
PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3),
PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3),
PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3),
PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3),
PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3),
PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3),
PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3),
PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3),
PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3),
PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3),
PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART),
PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART),
PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART),
PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART),
PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3),
PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3),
PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3),
PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3),
PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3),
PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3),
PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3),
PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3),
PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3),
PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3),
PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3),
PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3),
PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3),
PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3),
PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3),
PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3),
PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3),
PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3),
PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3),
PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3),
PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3),
PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3),
PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3),
PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3),
PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3),
PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3),
PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3),
PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3),
PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3),
PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3),
PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3),
PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3),
PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3),
PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3),
PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3),
PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3),
PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3),
PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3),
PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3),
PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3),
PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3),
PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3),
PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3),
PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3),
PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3),
PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3),
PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3),
PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3),
PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3),
PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3),
PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3),
PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3),
PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1),
PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3),
PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(PA6, SATA, RSVD1, RSVD2, RSVD3),
PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3),
PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3),
PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3),
PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3),
PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3),
PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3),
PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3),
PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3),
PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3),
PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3),
PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(PL1, SOC, RSVD1, RSVD2, RSVD3),
PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3),
PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3),
PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3),
PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3),
PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3),
};
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups;

13
arch/arm/dts/tegra30-apalis.dts
View file

@ -18,6 +18,10 @@
sdhci0 = "/sdhci@78000600";
sdhci1 = "/sdhci@78000400";
sdhci2 = "/sdhci@78000000";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000dc00";
spi2 = "/spi@7000de00";
spi3 = "/spi@7000da00";
usb0 = "/usb@7d000000";
usb1 = "/usb@7d004000";
usb2 = "/usb@7d008000";
@ -243,13 +247,15 @@
sdhci@78000000 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
/* SD1_CD# */
cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>;
};
sdhci@78000400 {
status = "okay";
bus-width = <8>;
cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
/* MMC1_CD# */
cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
};
sdhci@78000600 {
@ -262,12 +268,14 @@
usb@7d000000 {
status = "okay";
dr_mode = "peripheral";
/* USBO1_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
};
/* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
usb@7d004000 {
status = "okay";
/* USBH_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
phy_type = "utmi";
};
@ -275,6 +283,7 @@
/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
usb@7d008000 {
status = "okay";
/* USBH_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
};

4
arch/arm/dts/tegra30-colibri.dts
View file

@ -64,7 +64,7 @@
sdhci@78000200 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
};
sdhci@78000600 {
@ -83,12 +83,14 @@
usb@7d004000 {
status = "okay";
phy_type = "utmi";
/* VBUS_LAN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
};
/* EHCI instance 2: USB3_DP/N -> USBH_P/N */
usb@7d008000 {
status = "okay";
/* USBH_PEN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
};
};

10
arch/arm/include/asm/arch-orion5x/spl.h Normal file
View file

@ -0,0 +1,10 @@
/*
* (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_ARCH_SPL_H_
#define BOOT_DEVICE_NOR 1

4
arch/arm/include/asm/arch-tegra/ap.h
View file

@ -74,3 +74,7 @@ static inline void config_vpr(void)
{
}
#endif
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
bool tegra_cpu_is_non_secure(void);
#endif

110
arch/arm/include/asm/arch-tegra/pinmux.h
View file

@ -23,39 +23,82 @@ enum pmux_tristate {
PMUX_TRI_TRISTATE = 1,
};
#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
enum pmux_pin_io {
PMUX_PIN_OUTPUT = 0,
PMUX_PIN_INPUT = 1,
PMUX_PIN_NONE,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_LOCK
enum pmux_pin_lock {
PMUX_PIN_LOCK_DEFAULT = 0,
PMUX_PIN_LOCK_DISABLE,
PMUX_PIN_LOCK_ENABLE,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_OD
enum pmux_pin_od {
PMUX_PIN_OD_DEFAULT = 0,
PMUX_PIN_OD_DISABLE,
PMUX_PIN_OD_ENABLE,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
enum pmux_pin_ioreset {
PMUX_PIN_IO_RESET_DEFAULT = 0,
PMUX_PIN_IO_RESET_DISABLE,
PMUX_PIN_IO_RESET_ENABLE,
};
#endif
#ifdef TEGRA_PMX_HAS_RCV_SEL
#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
enum pmux_pin_rcv_sel {
PMUX_PIN_RCV_SEL_DEFAULT = 0,
PMUX_PIN_RCV_SEL_NORMAL,
PMUX_PIN_RCV_SEL_HIGH,
};
#endif /* TEGRA_PMX_HAS_RCV_SEL */
#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
#endif
#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
enum pmux_pin_e_io_hv {
PMUX_PIN_E_IO_HV_DEFAULT = 0,
PMUX_PIN_E_IO_HV_NORMAL,
PMUX_PIN_E_IO_HV_HIGH,
};
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
/* Defines a pin group cfg's low-power mode select */
enum pmux_lpmd {
PMUX_LPMD_X8 = 0,
PMUX_LPMD_X4,
PMUX_LPMD_X2,
PMUX_LPMD_X,
PMUX_LPMD_NONE = -1,
};
#endif
#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
/* Defines whether a pin group cfg's schmidt is enabled or not */
enum pmux_schmt {
PMUX_SCHMT_DISABLE = 0,
PMUX_SCHMT_ENABLE = 1,
PMUX_SCHMT_NONE = -1,
};
#endif
#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
/* Defines whether a pin group cfg's high-speed mode is enabled or not */
enum pmux_hsm {
PMUX_HSM_DISABLE = 0,
PMUX_HSM_ENABLE = 1,
PMUX_HSM_NONE = -1,
};
#endif
/*
* This defines the configuration for a pin, including the function assigned,
@ -68,21 +111,37 @@ struct pmux_pingrp_config {
u32 func:8; /* function to assign PMUX_FUNC_... */
u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/
u32 tristate:2; /* tristate or normal PMUX_TRI_... */
#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
u32 io:2; /* input or output PMUX_PIN_... */
#endif
#ifdef TEGRA_PMX_PINS_HAVE_LOCK
u32 lock:2; /* lock enable/disable PMUX_PIN... */
#endif
#ifdef TEGRA_PMX_PINS_HAVE_OD
u32 od:2; /* open-drain or push-pull driver */
#endif
#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
u32 ioreset:2; /* input/output reset PMUX_PIN... */
#ifdef TEGRA_PMX_HAS_RCV_SEL
#endif
#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
u32 rcv_sel:2; /* select between High and Normal */
/* VIL/VIH receivers */
#endif
#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
u32 e_io_hv:2; /* select 3.3v tolerant receivers */
#endif
#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
u32 schmt:2; /* schmitt enable */
#endif
#ifdef TEGRA_PMX_PINS_HAVE_HSM
u32 hsm:2; /* high-speed mode enable */
#endif
};
#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
/* Set the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
/* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
void pinmux_set_tristate_input_clamping(void);
void pinmux_clear_tristate_input_clamping(void);
#endif
/* Set the mux function for a pin group */
@ -97,7 +156,7 @@ void pinmux_tristate_enable(enum pmux_pingrp pin);
/* Set a pin group to normal (non tristate) */
void pinmux_tristate_disable(enum pmux_pingrp pin);
#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
/* Set a pin group as input or output */
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
#endif
@ -111,7 +170,7 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
int len);
#ifdef TEGRA_PMX_HAS_DRVGRPS
#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
#define PMUX_SLWF_MIN 0
#define PMUX_SLWF_MAX 3
@ -129,29 +188,6 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
#define PMUX_DRVDN_MAX 127
#define PMUX_DRVDN_NONE -1
/* Defines a pin group cfg's low-power mode select */
enum pmux_lpmd {
PMUX_LPMD_X8 = 0,
PMUX_LPMD_X4,
PMUX_LPMD_X2,
PMUX_LPMD_X,
PMUX_LPMD_NONE = -1,
};
/* Defines whether a pin group cfg's schmidt is enabled or not */
enum pmux_schmt {
PMUX_SCHMT_DISABLE = 0,
PMUX_SCHMT_ENABLE = 1,
PMUX_SCHMT_NONE = -1,
};
/* Defines whether a pin group cfg's high-speed mode is enabled or not */
enum pmux_hsm {
PMUX_HSM_DISABLE = 0,
PMUX_HSM_ENABLE = 1,
PMUX_HSM_NONE = -1,
};
/*
* This defines the configuration for a pin group's pad control config
*/
@ -161,9 +197,15 @@ struct pmux_drvgrp_config {
u32 slwr:3; /* rising edge slew */
u32 drvup:8; /* pull-up drive strength */
u32 drvdn:8; /* pull-down drive strength */
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
u32 lpmd:3; /* low-power mode selection */
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
u32 schmt:2; /* schmidt enable */
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_HSM
u32 hsm:2; /* high-speed mode enable */
#endif
};
/**
@ -175,7 +217,7 @@ struct pmux_drvgrp_config {
void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
int len);
#endif /* TEGRA_PMX_HAS_DRVGRPS */
#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
struct pmux_pingrp_desc {
u8 funcs[4];

14
arch/arm/include/asm/arch-tegra114/pinmux.h
View file

@ -313,9 +313,17 @@ enum pmux_func {
PMUX_FUNC_COUNT,
};
#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#define TEGRA_PMX_HAS_RCV_SEL
#define TEGRA_PMX_HAS_DRVGRPS
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
#define TEGRA_PMX_SOC_HAS_DRVGRPS
#define TEGRA_PMX_GRPS_HAVE_LPMD
#define TEGRA_PMX_GRPS_HAVE_SCHMT
#define TEGRA_PMX_GRPS_HAVE_HSM
#define TEGRA_PMX_PINS_HAVE_E_INPUT
#define TEGRA_PMX_PINS_HAVE_LOCK
#define TEGRA_PMX_PINS_HAVE_OD
#define TEGRA_PMX_PINS_HAVE_IO_RESET
#define TEGRA_PMX_PINS_HAVE_RCV_SEL
#include <asm/arch-tegra/pinmux.h>
#endif /* _TEGRA114_PINMUX_H_ */

14
arch/arm/include/asm/arch-tegra124/pinmux.h
View file

@ -335,9 +335,17 @@ enum pmux_func {
PMUX_FUNC_COUNT,
};
#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#define TEGRA_PMX_HAS_RCV_SEL
#define TEGRA_PMX_HAS_DRVGRPS
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
#define TEGRA_PMX_SOC_HAS_DRVGRPS
#define TEGRA_PMX_GRPS_HAVE_LPMD
#define TEGRA_PMX_GRPS_HAVE_SCHMT
#define TEGRA_PMX_GRPS_HAVE_HSM
#define TEGRA_PMX_PINS_HAVE_E_INPUT
#define TEGRA_PMX_PINS_HAVE_LOCK
#define TEGRA_PMX_PINS_HAVE_OD
#define TEGRA_PMX_PINS_HAVE_IO_RESET
#define TEGRA_PMX_PINS_HAVE_RCV_SEL
#include <asm/arch-tegra/pinmux.h>
#endif /* _TEGRA124_PINMUX_H_ */

1
arch/arm/include/asm/arch-tegra20/pinmux.h
View file

@ -233,6 +233,7 @@ enum pmux_func {
PMUX_FUNC_COUNT,
};
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
#include <asm/arch-tegra/pinmux.h>
#endif /* _TEGRA20_PINMUX_H_ */

416
arch/arm/include/asm/arch-tegra210/pinmux.h Normal file
View file

@ -0,0 +1,416 @@
/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_PINMUX_H_
#define _TEGRA210_PINMUX_H_
enum pmux_pingrp {
PMUX_PINGRP_SDMMC1_CLK_PM0,
PMUX_PINGRP_SDMMC1_CMD_PM1,
PMUX_PINGRP_SDMMC1_DAT3_PM2,
PMUX_PINGRP_SDMMC1_DAT2_PM3,
PMUX_PINGRP_SDMMC1_DAT1_PM4,
PMUX_PINGRP_SDMMC1_DAT0_PM5,
PMUX_PINGRP_SDMMC3_CLK_PP0 = (0x1c / 4),
PMUX_PINGRP_SDMMC3_CMD_PP1,
PMUX_PINGRP_SDMMC3_DAT0_PP5,
PMUX_PINGRP_SDMMC3_DAT1_PP4,
PMUX_PINGRP_SDMMC3_DAT2_PP3,
PMUX_PINGRP_SDMMC3_DAT3_PP2,
PMUX_PINGRP_PEX_L0_RST_N_PA0 = (0x38 / 4),
PMUX_PINGRP_PEX_L0_CLKREQ_N_PA1,
PMUX_PINGRP_PEX_WAKE_N_PA2,
PMUX_PINGRP_PEX_L1_RST_N_PA3,
PMUX_PINGRP_PEX_L1_CLKREQ_N_PA4,
PMUX_PINGRP_SATA_LED_ACTIVE_PA5,
PMUX_PINGRP_SPI1_MOSI_PC0,
PMUX_PINGRP_SPI1_MISO_PC1,
PMUX_PINGRP_SPI1_SCK_PC2,
PMUX_PINGRP_SPI1_CS0_PC3,
PMUX_PINGRP_SPI1_CS1_PC4,
PMUX_PINGRP_SPI2_MOSI_PB4,
PMUX_PINGRP_SPI2_MISO_PB5,
PMUX_PINGRP_SPI2_SCK_PB6,
PMUX_PINGRP_SPI2_CS0_PB7,
PMUX_PINGRP_SPI2_CS1_PDD0,
PMUX_PINGRP_SPI4_MOSI_PC7,
PMUX_PINGRP_SPI4_MISO_PD0,
PMUX_PINGRP_SPI4_SCK_PC5,
PMUX_PINGRP_SPI4_CS0_PC6,
PMUX_PINGRP_QSPI_SCK_PEE0,
PMUX_PINGRP_QSPI_CS_N_PEE1,
PMUX_PINGRP_QSPI_IO0_PEE2,
PMUX_PINGRP_QSPI_IO1_PEE3,
PMUX_PINGRP_QSPI_IO2_PEE4,
PMUX_PINGRP_QSPI_IO3_PEE5,
PMUX_PINGRP_DMIC1_CLK_PE0 = (0xa4 / 4),
PMUX_PINGRP_DMIC1_DAT_PE1,
PMUX_PINGRP_DMIC2_CLK_PE2,
PMUX_PINGRP_DMIC2_DAT_PE3,
PMUX_PINGRP_DMIC3_CLK_PE4,
PMUX_PINGRP_DMIC3_DAT_PE5,
PMUX_PINGRP_GEN1_I2C_SCL_PJ1,
PMUX_PINGRP_GEN1_I2C_SDA_PJ0,
PMUX_PINGRP_GEN2_I2C_SCL_PJ2,
PMUX_PINGRP_GEN2_I2C_SDA_PJ3,
PMUX_PINGRP_GEN3_I2C_SCL_PF0,
PMUX_PINGRP_GEN3_I2C_SDA_PF1,
PMUX_PINGRP_CAM_I2C_SCL_PS2,
PMUX_PINGRP_CAM_I2C_SDA_PS3,
PMUX_PINGRP_PWR_I2C_SCL_PY3,
PMUX_PINGRP_PWR_I2C_SDA_PY4,
PMUX_PINGRP_UART1_TX_PU0,
PMUX_PINGRP_UART1_RX_PU1,
PMUX_PINGRP_UART1_RTS_PU2,
PMUX_PINGRP_UART1_CTS_PU3,
PMUX_PINGRP_UART2_TX_PG0,
PMUX_PINGRP_UART2_RX_PG1,
PMUX_PINGRP_UART2_RTS_PG2,
PMUX_PINGRP_UART2_CTS_PG3,
PMUX_PINGRP_UART3_TX_PD1,
PMUX_PINGRP_UART3_RX_PD2,
PMUX_PINGRP_UART3_RTS_PD3,
PMUX_PINGRP_UART3_CTS_PD4,
PMUX_PINGRP_UART4_TX_PI4,
PMUX_PINGRP_UART4_RX_PI5,
PMUX_PINGRP_UART4_RTS_PI6,
PMUX_PINGRP_UART4_CTS_PI7,
PMUX_PINGRP_DAP1_FS_PB0,
PMUX_PINGRP_DAP1_DIN_PB1,
PMUX_PINGRP_DAP1_DOUT_PB2,
PMUX_PINGRP_DAP1_SCLK_PB3,
PMUX_PINGRP_DAP2_FS_PAA0,
PMUX_PINGRP_DAP2_DIN_PAA2,
PMUX_PINGRP_DAP2_DOUT_PAA3,
PMUX_PINGRP_DAP2_SCLK_PAA1,
PMUX_PINGRP_DAP4_FS_PJ4,
PMUX_PINGRP_DAP4_DIN_PJ5,
PMUX_PINGRP_DAP4_DOUT_PJ6,
PMUX_PINGRP_DAP4_SCLK_PJ7,
PMUX_PINGRP_CAM1_MCLK_PS0,
PMUX_PINGRP_CAM2_MCLK_PS1,
PMUX_PINGRP_JTAG_RTCK,
PMUX_PINGRP_CLK_32K_IN,
PMUX_PINGRP_CLK_32K_OUT_PY5,
PMUX_PINGRP_BATT_BCL,
PMUX_PINGRP_CLK_REQ,
PMUX_PINGRP_CPU_PWR_REQ,
PMUX_PINGRP_PWR_INT_N,
PMUX_PINGRP_SHUTDOWN,
PMUX_PINGRP_CORE_PWR_REQ,
PMUX_PINGRP_AUD_MCLK_PBB0,
PMUX_PINGRP_DVFS_PWM_PBB1,
PMUX_PINGRP_DVFS_CLK_PBB2,
PMUX_PINGRP_GPIO_X1_AUD_PBB3,
PMUX_PINGRP_GPIO_X3_AUD_PBB4,
PMUX_PINGRP_PCC7,
PMUX_PINGRP_HDMI_CEC_PCC0,
PMUX_PINGRP_HDMI_INT_DP_HPD_PCC1,
PMUX_PINGRP_SPDIF_OUT_PCC2,
PMUX_PINGRP_SPDIF_IN_PCC3,
PMUX_PINGRP_USB_VBUS_EN0_PCC4,
PMUX_PINGRP_USB_VBUS_EN1_PCC5,
PMUX_PINGRP_DP_HPD0_PCC6,
PMUX_PINGRP_WIFI_EN_PH0,
PMUX_PINGRP_WIFI_RST_PH1,
PMUX_PINGRP_WIFI_WAKE_AP_PH2,
PMUX_PINGRP_AP_WAKE_BT_PH3,
PMUX_PINGRP_BT_RST_PH4,
PMUX_PINGRP_BT_WAKE_AP_PH5,
PMUX_PINGRP_AP_WAKE_NFC_PH7,
PMUX_PINGRP_NFC_EN_PI0,
PMUX_PINGRP_NFC_INT_PI1,
PMUX_PINGRP_GPS_EN_PI2,
PMUX_PINGRP_GPS_RST_PI3,
PMUX_PINGRP_CAM_RST_PS4,
PMUX_PINGRP_CAM_AF_EN_PS5,
PMUX_PINGRP_CAM_FLASH_EN_PS6,
PMUX_PINGRP_CAM1_PWDN_PS7,
PMUX_PINGRP_CAM2_PWDN_PT0,
PMUX_PINGRP_CAM1_STROBE_PT1,
PMUX_PINGRP_LCD_TE_PY2,
PMUX_PINGRP_LCD_BL_PWM_PV0,
PMUX_PINGRP_LCD_BL_EN_PV1,
PMUX_PINGRP_LCD_RST_PV2,
PMUX_PINGRP_LCD_GPIO1_PV3,
PMUX_PINGRP_LCD_GPIO2_PV4,
PMUX_PINGRP_AP_READY_PV5,
PMUX_PINGRP_TOUCH_RST_PV6,
PMUX_PINGRP_TOUCH_CLK_PV7,
PMUX_PINGRP_MODEM_WAKE_AP_PX0,
PMUX_PINGRP_TOUCH_INT_PX1,
PMUX_PINGRP_MOTION_INT_PX2,
PMUX_PINGRP_ALS_PROX_INT_PX3,
PMUX_PINGRP_TEMP_ALERT_PX4,
PMUX_PINGRP_BUTTON_POWER_ON_PX5,
PMUX_PINGRP_BUTTON_VOL_UP_PX6,
PMUX_PINGRP_BUTTON_VOL_DOWN_PX7,
PMUX_PINGRP_BUTTON_SLIDE_SW_PY0,
PMUX_PINGRP_BUTTON_HOME_PY1,
PMUX_PINGRP_PA6,
PMUX_PINGRP_PE6,
PMUX_PINGRP_PE7,
PMUX_PINGRP_PH6,
PMUX_PINGRP_PK0,
PMUX_PINGRP_PK1,
PMUX_PINGRP_PK2,
PMUX_PINGRP_PK3,
PMUX_PINGRP_PK4,
PMUX_PINGRP_PK5,
PMUX_PINGRP_PK6,
PMUX_PINGRP_PK7,
PMUX_PINGRP_PL0,
PMUX_PINGRP_PL1,
PMUX_PINGRP_PZ0,
PMUX_PINGRP_PZ1,
PMUX_PINGRP_PZ2,
PMUX_PINGRP_PZ3,
PMUX_PINGRP_PZ4,
PMUX_PINGRP_PZ5,
PMUX_PINGRP_COUNT,
};
enum pmux_drvgrp {
PMUX_DRVGRP_ALS_PROX_INT = (0x10 / 4),
PMUX_DRVGRP_AP_READY,
PMUX_DRVGRP_AP_WAKE_BT,
PMUX_DRVGRP_AP_WAKE_NFC,
PMUX_DRVGRP_AUD_MCLK,
PMUX_DRVGRP_BATT_BCL,
PMUX_DRVGRP_BT_RST,
PMUX_DRVGRP_BT_WAKE_AP,
PMUX_DRVGRP_BUTTON_HOME,
PMUX_DRVGRP_BUTTON_POWER_ON,
PMUX_DRVGRP_BUTTON_SLIDE_SW,
PMUX_DRVGRP_BUTTON_VOL_DOWN,
PMUX_DRVGRP_BUTTON_VOL_UP,
PMUX_DRVGRP_CAM1_MCLK,
PMUX_DRVGRP_CAM1_PWDN,
PMUX_DRVGRP_CAM1_STROBE,
PMUX_DRVGRP_CAM2_MCLK,
PMUX_DRVGRP_CAM2_PWDN,
PMUX_DRVGRP_CAM_AF_EN,
PMUX_DRVGRP_CAM_FLASH_EN,
PMUX_DRVGRP_CAM_I2C_SCL,
PMUX_DRVGRP_CAM_I2C_SDA,
PMUX_DRVGRP_CAM_RST,
PMUX_DRVGRP_CLK_32K_IN,
PMUX_DRVGRP_CLK_32K_OUT,
PMUX_DRVGRP_CLK_REQ,
PMUX_DRVGRP_CORE_PWR_REQ,
PMUX_DRVGRP_CPU_PWR_REQ,
PMUX_DRVGRP_DAP1_DIN,
PMUX_DRVGRP_DAP1_DOUT,
PMUX_DRVGRP_DAP1_FS,
PMUX_DRVGRP_DAP1_SCLK,
PMUX_DRVGRP_DAP2_DIN,
PMUX_DRVGRP_DAP2_DOUT,
PMUX_DRVGRP_DAP2_FS,
PMUX_DRVGRP_DAP2_SCLK,
PMUX_DRVGRP_DAP4_DIN,
PMUX_DRVGRP_DAP4_DOUT,
PMUX_DRVGRP_DAP4_FS,
PMUX_DRVGRP_DAP4_SCLK,
PMUX_DRVGRP_DMIC1_CLK,
PMUX_DRVGRP_DMIC1_DAT,
PMUX_DRVGRP_DMIC2_CLK,
PMUX_DRVGRP_DMIC2_DAT,
PMUX_DRVGRP_DMIC3_CLK,
PMUX_DRVGRP_DMIC3_DAT,
PMUX_DRVGRP_DP_HPD0,
PMUX_DRVGRP_DVFS_CLK,
PMUX_DRVGRP_DVFS_PWM,
PMUX_DRVGRP_GEN1_I2C_SCL,
PMUX_DRVGRP_GEN1_I2C_SDA,
PMUX_DRVGRP_GEN2_I2C_SCL,
PMUX_DRVGRP_GEN2_I2C_SDA,
PMUX_DRVGRP_GEN3_I2C_SCL,
PMUX_DRVGRP_GEN3_I2C_SDA,
PMUX_DRVGRP_PA6,
PMUX_DRVGRP_PCC7,
PMUX_DRVGRP_PE6,
PMUX_DRVGRP_PE7,
PMUX_DRVGRP_PH6,
PMUX_DRVGRP_PK0,
PMUX_DRVGRP_PK1,
PMUX_DRVGRP_PK2,
PMUX_DRVGRP_PK3,
PMUX_DRVGRP_PK4,
PMUX_DRVGRP_PK5,
PMUX_DRVGRP_PK6,
PMUX_DRVGRP_PK7,
PMUX_DRVGRP_PL0,
PMUX_DRVGRP_PL1,
PMUX_DRVGRP_PZ0,
PMUX_DRVGRP_PZ1,
PMUX_DRVGRP_PZ2,
PMUX_DRVGRP_PZ3,
PMUX_DRVGRP_PZ4,
PMUX_DRVGRP_PZ5,
PMUX_DRVGRP_GPIO_X1_AUD,
PMUX_DRVGRP_GPIO_X3_AUD,
PMUX_DRVGRP_GPS_EN,
PMUX_DRVGRP_GPS_RST,
PMUX_DRVGRP_HDMI_CEC,
PMUX_DRVGRP_HDMI_INT_DP_HPD,
PMUX_DRVGRP_JTAG_RTCK,
PMUX_DRVGRP_LCD_BL_EN,
PMUX_DRVGRP_LCD_BL_PWM,
PMUX_DRVGRP_LCD_GPIO1,
PMUX_DRVGRP_LCD_GPIO2,
PMUX_DRVGRP_LCD_RST,
PMUX_DRVGRP_LCD_TE,
PMUX_DRVGRP_MODEM_WAKE_AP,
PMUX_DRVGRP_MOTION_INT,
PMUX_DRVGRP_NFC_EN,
PMUX_DRVGRP_NFC_INT,
PMUX_DRVGRP_PEX_L0_CLKREQ_N,
PMUX_DRVGRP_PEX_L0_RST_N,
PMUX_DRVGRP_PEX_L1_CLKREQ_N,
PMUX_DRVGRP_PEX_L1_RST_N,
PMUX_DRVGRP_PEX_WAKE_N,
PMUX_DRVGRP_PWR_I2C_SCL,
PMUX_DRVGRP_PWR_I2C_SDA,
PMUX_DRVGRP_PWR_INT_N,
PMUX_DRVGRP_QSPI_SCK = (0x1bc / 4),
PMUX_DRVGRP_SATA_LED_ACTIVE,
PMUX_DRVGRP_SDMMC1,
PMUX_DRVGRP_SDMMC2,
PMUX_DRVGRP_SDMMC3 = (0x1dc / 4),
PMUX_DRVGRP_SDMMC4,
PMUX_DRVGRP_SHUTDOWN = (0x1f4 / 4),
PMUX_DRVGRP_SPDIF_IN,
PMUX_DRVGRP_SPDIF_OUT,
PMUX_DRVGRP_SPI1_CS0,
PMUX_DRVGRP_SPI1_CS1,
PMUX_DRVGRP_SPI1_MISO,
PMUX_DRVGRP_SPI1_MOSI,
PMUX_DRVGRP_SPI1_SCK,
PMUX_DRVGRP_SPI2_CS0,
PMUX_DRVGRP_SPI2_CS1,
PMUX_DRVGRP_SPI2_MISO,
PMUX_DRVGRP_SPI2_MOSI,
PMUX_DRVGRP_SPI2_SCK,
PMUX_DRVGRP_SPI4_CS0,
PMUX_DRVGRP_SPI4_MISO,
PMUX_DRVGRP_SPI4_MOSI,
PMUX_DRVGRP_SPI4_SCK,
PMUX_DRVGRP_TEMP_ALERT,
PMUX_DRVGRP_TOUCH_CLK,
PMUX_DRVGRP_TOUCH_INT,
PMUX_DRVGRP_TOUCH_RST,
PMUX_DRVGRP_UART1_CTS,
PMUX_DRVGRP_UART1_RTS,
PMUX_DRVGRP_UART1_RX,
PMUX_DRVGRP_UART1_TX,
PMUX_DRVGRP_UART2_CTS,
PMUX_DRVGRP_UART2_RTS,
PMUX_DRVGRP_UART2_RX,
PMUX_DRVGRP_UART2_TX,
PMUX_DRVGRP_UART3_CTS,
PMUX_DRVGRP_UART3_RTS,
PMUX_DRVGRP_UART3_RX,
PMUX_DRVGRP_UART3_TX,
PMUX_DRVGRP_UART4_CTS,
PMUX_DRVGRP_UART4_RTS,
PMUX_DRVGRP_UART4_RX,
PMUX_DRVGRP_UART4_TX,
PMUX_DRVGRP_USB_VBUS_EN0,
PMUX_DRVGRP_USB_VBUS_EN1,
PMUX_DRVGRP_WIFI_EN,
PMUX_DRVGRP_WIFI_RST,
PMUX_DRVGRP_WIFI_WAKE_AP,
PMUX_DRVGRP_COUNT,
};
enum pmux_func {
PMUX_FUNC_DEFAULT,
PMUX_FUNC_AUD,
PMUX_FUNC_BCL,
PMUX_FUNC_BLINK,
PMUX_FUNC_CCLA,
PMUX_FUNC_CEC,
PMUX_FUNC_CLDVFS,
PMUX_FUNC_CLK,
PMUX_FUNC_CORE,
PMUX_FUNC_CPU,
PMUX_FUNC_DISPLAYA,
PMUX_FUNC_DISPLAYB,
PMUX_FUNC_DMIC1,
PMUX_FUNC_DMIC2,
PMUX_FUNC_DMIC3,
PMUX_FUNC_DP,
PMUX_FUNC_DTV,
PMUX_FUNC_EXTPERIPH3,
PMUX_FUNC_I2C1,
PMUX_FUNC_I2C2,
PMUX_FUNC_I2C3,
PMUX_FUNC_I2CPMU,
PMUX_FUNC_I2CVI,
PMUX_FUNC_I2S1,
PMUX_FUNC_I2S2,
PMUX_FUNC_I2S3,
PMUX_FUNC_I2S4A,
PMUX_FUNC_I2S4B,
PMUX_FUNC_I2S5A,
PMUX_FUNC_I2S5B,
PMUX_FUNC_IQC0,
PMUX_FUNC_IQC1,
PMUX_FUNC_JTAG,
PMUX_FUNC_PE,
PMUX_FUNC_PE0,
PMUX_FUNC_PE1,
PMUX_FUNC_PMI,
PMUX_FUNC_PWM0,
PMUX_FUNC_PWM1,
PMUX_FUNC_PWM2,
PMUX_FUNC_PWM3,
PMUX_FUNC_QSPI,
PMUX_FUNC_SATA,
PMUX_FUNC_SDMMC1,
PMUX_FUNC_SDMMC3,
PMUX_FUNC_SHUTDOWN,
PMUX_FUNC_SOC,
PMUX_FUNC_SOR0,
PMUX_FUNC_SOR1,
PMUX_FUNC_SPDIF,
PMUX_FUNC_SPI1,
PMUX_FUNC_SPI2,
PMUX_FUNC_SPI3,
PMUX_FUNC_SPI4,
PMUX_FUNC_SYS,
PMUX_FUNC_TOUCH,
PMUX_FUNC_UART,
PMUX_FUNC_UARTA,
PMUX_FUNC_UARTB,
PMUX_FUNC_UARTC,
PMUX_FUNC_UARTD,
PMUX_FUNC_USB,
PMUX_FUNC_VGP1,
PMUX_FUNC_VGP2,
PMUX_FUNC_VGP3,
PMUX_FUNC_VGP4,
PMUX_FUNC_VGP5,
PMUX_FUNC_VGP6,
PMUX_FUNC_VIMCLK,
PMUX_FUNC_VIMCLK2,
PMUX_FUNC_RSVD0,
PMUX_FUNC_RSVD1,
PMUX_FUNC_RSVD2,
PMUX_FUNC_RSVD3,
PMUX_FUNC_COUNT,
};
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x8d4
#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
#define TEGRA_PMX_SOC_HAS_DRVGRPS
#define TEGRA_PMX_PINS_HAVE_E_INPUT
#define TEGRA_PMX_PINS_HAVE_LOCK
#define TEGRA_PMX_PINS_HAVE_OD
#define TEGRA_PMX_PINS_HAVE_E_IO_HV
#include <asm/arch-tegra/pinmux.h>
#endif /* _TEGRA210_PINMUX_H_ */

11
arch/arm/include/asm/arch-tegra30/pinmux.h
View file

@ -391,8 +391,15 @@ enum pmux_func {
PMUX_FUNC_COUNT,
};
#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#define TEGRA_PMX_HAS_DRVGRPS
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
#define TEGRA_PMX_SOC_HAS_DRVGRPS
#define TEGRA_PMX_GRPS_HAVE_LPMD
#define TEGRA_PMX_GRPS_HAVE_SCHMT
#define TEGRA_PMX_GRPS_HAVE_HSM
#define TEGRA_PMX_PINS_HAVE_E_INPUT
#define TEGRA_PMX_PINS_HAVE_LOCK
#define TEGRA_PMX_PINS_HAVE_OD
#define TEGRA_PMX_PINS_HAVE_IO_RESET
#include <asm/arch-tegra/pinmux.h>
#endif /* _TEGRA30_PINMUX_H_ */

22
arch/arm/include/asm/macro.h
View file

@ -73,6 +73,28 @@ lr .req x30
b.eq \el1_label
.endm
/*
* Branch if current processor is a Cortex-A57 core.
*/
.macro branch_if_a57_core, xreg, a57_label
mrs \xreg, midr_el1
lsr \xreg, \xreg, #4
and \xreg, \xreg, #0x00000FFF
cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */
b.eq \a57_label
.endm
/*
* Branch if current processor is a Cortex-A53 core.
*/
.macro branch_if_a53_core, xreg, a53_label
mrs \xreg, midr_el1
lsr \xreg, \xreg, #4
and \xreg, \xreg, #0x00000FFF
cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */
b.eq \a53_label
.endm
/*
* Branch if current processor is a slave,
* choose processor with all zero affinity value as the master.

13
arch/arm/lib/interrupts.c
View file

@ -137,10 +137,15 @@ void show_regs (struct pt_regs *regs)
flags = condition_codes (regs);
printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
"sp : %08lx ip : %08lx fp : %08lx\n",
instruction_pointer (regs),
regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
printf("pc : [<%08lx>] lr : [<%08lx>]\n",
instruction_pointer(regs), regs->ARM_lr);
if (gd->flags & GD_FLG_RELOC) {
printf("reloc pc : [<%08lx>] lr : [<%08lx>]\n",
instruction_pointer(regs) - gd->reloc_off,
regs->ARM_lr - gd->reloc_off);
}
printf("sp : %08lx ip : %08lx fp : %08lx\n",
regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",

1
arch/arm/mach-orion5x/Kconfig
View file

@ -5,6 +5,7 @@ choice
config TARGET_EDMINIV2
bool "LaCie Ethernet Disk mini V2"
select SUPPORT_SPL
endchoice

2
arch/arm/mach-orion5x/cpu.c
View file

@ -234,7 +234,9 @@ int arch_cpu_init(void)
/* Enable and invalidate L2 cache in write through mode */
invalidate_l2_cache();
#ifdef CONFIG_SPL_BUILD
orion5x_config_adr_windows();
#endif
return 0;
}

2
arch/arm/mach-orion5x/include/mach/cpu.h
View file

@ -86,7 +86,7 @@ enum orion5x_cpu_attrib {
#endif
#if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO)
#define ORION5X_ADR_PCIE_IO_REMAP_LO 0x90000000
#define ORION5X_ADR_PCIE_IO_REMAP_LO 0xf0000000
#endif
#if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI)

14
arch/arm/mach-orion5x/lowlevel_init.S
View file

@ -62,14 +62,16 @@
/*
* Low-level init happens right after start.S has switched to SVC32,
* flushed and disabled caches and disabled MMU. We're still running
* from the boot chip select, so the first thing we should do is set
* up RAM for us to relocate into.
* from the boot chip select, so the first thing SPL should do is to
* set up the RAM to copy U-Boot into.
*/
.globl lowlevel_init
lowlevel_init:
#ifdef CONFIG_SPL_BUILD
/* Use 'r4 as the base for internal register accesses */
ldr r4, =ORION5X_REGS_PHY_BASE
@ -273,5 +275,13 @@ lowlevel_init:
orr r2, r2, r6
str r2, [r3, #0x484]
/* enable for 2 GB DDR; detection should find out real amount */
sub r6, r6, r6
str r6, [r3, #0x500]
ldr r6, =0x7fff0001
str r6, [r3, #0x504]
#endif /* CONFIG_SPL_BUILD */
/* Return to U-boot via saved link register */
mov pc, lr

56
arch/arm/mach-tegra/board.c
View file

@ -11,6 +11,7 @@
#include <asm/arch/funcmux.h>
#include <asm/arch/mc.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/sys_proto.h>
@ -28,27 +29,66 @@ enum {
UART_COUNT = 5,
};
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
#if !defined(CONFIG_TEGRA124)
#error tegra_cpu_is_non_secure has only been validated on Tegra124
#endif
bool tegra_cpu_is_non_secure(void)
{
/*
* This register reads 0xffffffff in non-secure mode. This register
* only implements bits 31:20, so the lower bits will always read 0 in
* secure mode. Thus, the lower bits are an indicator for secure vs.
* non-secure mode.
*/
struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
return (mc_s_cfg0 & 1) == 1;
}
#endif
/* Read the RAM size directly from the memory controller */
unsigned int query_sdram_size(void)
{
struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
u32 size_mb;
u32 emem_cfg, size_bytes;
size_mb = readl(&mc->mc_emem_cfg);
emem_cfg = readl(&mc->mc_emem_cfg);
#if defined(CONFIG_TEGRA20)
debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", size_mb);
size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024);
debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
#else
debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb);
size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024 * 1024);
debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
/*
* If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
* and will wrap. Clip the reported size to the maximum that a 32-bit
* variable can represent (rounded to a page).
*/
if (emem_cfg >= 4096) {
size_bytes = U32_MAX & ~(0x1000 - 1);
} else {
/* RAM size EMC is programmed to. */
size_bytes = emem_cfg * 1024 * 1024;
/*
* If all RAM fits within 32-bits, it can be accessed without
* LPAE, so go test the RAM size. Otherwise, we can't access
* all the RAM, and get_ram_size() would get confused, so
* avoid using it. There's no reason we should need this
* validation step anyway.
*/
if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
size_bytes);
}
#endif
#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
/* External memory limited to 2047 MB due to IROM/HI-VEC */
if (size_mb == SZ_2G) size_mb -= SZ_1M;
if (size_bytes == SZ_2G)
size_bytes -= SZ_1M;
#endif
return size_mb;
return size_bytes;
}
int dram_init(void)

6
arch/arm/mach-tegra/clock.c
View file

@ -20,6 +20,7 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/timer.h>
#include <div64.h>
@ -573,7 +574,10 @@ void clock_init(void)
debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
/* Do any special system timer/TSC setup */
arch_timer_init();
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
if (!tegra_cpu_is_non_secure())
#endif
arch_timer_init();
}
static void set_avp_clock_source(u32 src)

223
arch/arm/mach-tegra/pinmux-common.c
View file

@ -24,31 +24,59 @@
#define pmux_pin_tristate_isvalid(tristate) \
(((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
/* return 1 if a pin_io_is in range */
#define pmux_pin_io_isvalid(io) \
(((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
#endif
#ifdef TEGRA_PMX_PINS_HAVE_LOCK
/* return 1 if a pin_lock is in range */
#define pmux_pin_lock_isvalid(lock) \
(((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
#endif
#ifdef TEGRA_PMX_PINS_HAVE_OD
/* return 1 if a pin_od is in range */
#define pmux_pin_od_isvalid(od) \
(((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
#endif
#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
/* return 1 if a pin_ioreset_is in range */
#define pmux_pin_ioreset_isvalid(ioreset) \
(((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
#endif
#ifdef TEGRA_PMX_HAS_RCV_SEL
#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
/* return 1 if a pin_rcv_sel_is in range */
#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
(((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
#endif /* TEGRA_PMX_HAS_RCV_SEL */
#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
#endif
#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
/* return 1 if a pin_e_io_hv is in range */
#define pmux_pin_e_io_hv_isvalid(e_io_hv) \
(((e_io_hv) >= PMUX_PIN_E_IO_HV_NORMAL) && \
((e_io_hv) <= PMUX_PIN_E_IO_HV_HIGH))
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
#define pmux_lpmd_isvalid(lpm) \
(((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
#endif
#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
#define pmux_schmt_isvalid(schmt) \
(((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
#endif
#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
#define pmux_hsm_isvalid(hsm) \
(((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
#endif
#define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset))
@ -78,15 +106,34 @@
#endif /* CONFIG_TEGRA20 */
#define DRV_REG(group) _R(0x868 + ((group) * 4))
#define DRV_REG(group) _R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4))
/*
* We could force arch-tegraNN/pinmux.h to define all of these. However,
* that's a lot of defines, and for now it's manageable to just put a
* special case here. It's possible this decision will change with future
* SoCs.
*/
#ifdef CONFIG_TEGRA210
#define IO_SHIFT 6
#define LOCK_SHIFT 7
#ifdef TEGRA_PMX_PINS_HAVE_HSM
#define HSM_SHIFT 9
#endif
#define E_IO_HV_SHIFT 10
#define OD_SHIFT 11
#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
#define SCHMT_SHIFT 12
#endif
#else
#define IO_SHIFT 5
#define OD_SHIFT 6
#define LOCK_SHIFT 7
#define IO_RESET_SHIFT 8
#define RCV_SEL_SHIFT 9
#endif
#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
/* This register/field only exists on Tegra114 and later */
#define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
#define CLAMP_INPUTS_WHEN_TRISTATED 1
@ -94,11 +141,15 @@
void pinmux_set_tristate_input_clamping(void)
{
u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
u32 val;
val = readl(reg);
val |= CLAMP_INPUTS_WHEN_TRISTATED;
writel(val, reg);
setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
}
void pinmux_clear_tristate_input_clamping(void)
{
u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
}
#endif
@ -176,7 +227,7 @@ void pinmux_tristate_disable(enum pmux_pingrp pin)
pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
}
#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
{
u32 *reg = REG(pin);
@ -196,7 +247,9 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
val &= ~(1 << IO_SHIFT);
writel(val, reg);
}
#endif
#ifdef TEGRA_PMX_PINS_HAVE_LOCK
static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
{
u32 *reg = REG(pin);
@ -221,7 +274,9 @@ static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
return;
}
#endif
#ifdef TEGRA_PMX_PINS_HAVE_OD
static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
{
u32 *reg = REG(pin);
@ -243,7 +298,9 @@ static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
return;
}
#endif
#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
static void pinmux_set_ioreset(enum pmux_pingrp pin,
enum pmux_pin_ioreset ioreset)
{
@ -266,8 +323,9 @@ static void pinmux_set_ioreset(enum pmux_pingrp pin,
return;
}
#endif
#ifdef TEGRA_PMX_HAS_RCV_SEL
#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
enum pmux_pin_rcv_sel rcv_sel)
{
@ -290,8 +348,82 @@ static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
return;
}
#endif /* TEGRA_PMX_HAS_RCV_SEL */
#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
#endif
#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
static void pinmux_set_e_io_hv(enum pmux_pingrp pin,
enum pmux_pin_e_io_hv e_io_hv)
{
u32 *reg = REG(pin);
u32 val;
if (e_io_hv == PMUX_PIN_E_IO_HV_DEFAULT)
return;
/* Error check on pin and e_io_hv */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_e_io_hv_isvalid(e_io_hv));
val = readl(reg);
if (e_io_hv == PMUX_PIN_E_IO_HV_HIGH)
val |= (1 << E_IO_HV_SHIFT);
else
val &= ~(1 << E_IO_HV_SHIFT);
writel(val, reg);
return;
}
#endif
#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
static void pinmux_set_schmt(enum pmux_pingrp pin, enum pmux_schmt schmt)
{
u32 *reg = REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
if (schmt == PMUX_SCHMT_NONE)
return;
/* Error check pad */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_schmt_isvalid(schmt));
val = readl(reg);
if (schmt == PMUX_SCHMT_ENABLE)
val |= (1 << SCHMT_SHIFT);
else
val &= ~(1 << SCHMT_SHIFT);
writel(val, reg);
return;
}
#endif
#ifdef TEGRA_PMX_PINS_HAVE_HSM
static void pinmux_set_hsm(enum pmux_pingrp pin, enum pmux_hsm hsm)
{
u32 *reg = REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
if (hsm == PMUX_HSM_NONE)
return;
/* Error check pad */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_hsm_isvalid(hsm));
val = readl(reg);
if (hsm == PMUX_HSM_ENABLE)
val |= (1 << HSM_SHIFT);
else
val &= ~(1 << HSM_SHIFT);
writel(val, reg);
return;
}
#endif
static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
{
@ -300,14 +432,29 @@ static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
pinmux_set_func(pin, config->func);
pinmux_set_pullupdown(pin, config->pull);
pinmux_set_tristate(pin, config->tristate);
#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
pinmux_set_io(pin, config->io);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_LOCK
pinmux_set_lock(pin, config->lock);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_OD
pinmux_set_od(pin, config->od);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
pinmux_set_ioreset(pin, config->ioreset);
#ifdef TEGRA_PMX_HAS_RCV_SEL
#endif
#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
pinmux_set_rcv_sel(pin, config->rcv_sel);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
pinmux_set_e_io_hv(pin, config->e_io_hv);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
pinmux_set_schmt(pin, config->schmt);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_HSM
pinmux_set_hsm(pin, config->hsm);
#endif
}
@ -320,7 +467,7 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
pinmux_config_pingrp(&config[i]);
}
#ifdef TEGRA_PMX_HAS_DRVGRPS
#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
#define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
@ -330,19 +477,31 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
#define pmux_drv_isvalid(drv) \
(((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
#define pmux_lpmd_isvalid(lpm) \
(((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
#define pmux_schmt_isvalid(schmt) \
(((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
#define pmux_hsm_isvalid(hsm) \
(((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
#ifdef TEGRA_PMX_GRPS_HAVE_HSM
#define HSM_SHIFT 2
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
#define SCHMT_SHIFT 3
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
#define LPMD_SHIFT 4
#define LPMD_MASK (3 << LPMD_SHIFT)
#endif
/*
* Note that the following DRV* and SLW* defines are accurate for many drive
* groups on many SoCs. We really need a per-group data structure to solve
* this, since the fields are in different positions/sizes in different
* registers (for different groups).
*
* On Tegra30/114/124, the DRV*_SHIFT values vary.
* On Tegra30, the SLW*_SHIFT values vary.
* On Tegra30/114/124/210, the DRV*_MASK values vary, although the values
* below are wide enough to cover the widest fields, and hopefully don't
* interfere with any other fields.
* On Tegra30, the SLW*_MASK values vary, but we can't use a value that's
* wide enough to cover all cases, since that would cause the field to
* overlap with other fields in the narrower cases.
*/
#define DRVDN_SHIFT 12
#define DRVDN_MASK (0x7F << DRVDN_SHIFT)
#define DRVUP_SHIFT 20
@ -436,6 +595,7 @@ static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
return;
}
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
{
u32 *reg = DRV_REG(grp);
@ -456,7 +616,9 @@ static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
return;
}
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
{
u32 *reg = DRV_REG(grp);
@ -479,7 +641,9 @@ static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
return;
}
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_HSM
static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
{
u32 *reg = DRV_REG(grp);
@ -502,6 +666,7 @@ static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
return;
}
#endif
static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
{
@ -511,9 +676,15 @@ static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
pinmux_set_drvdn_slwr(grp, config->slwr);
pinmux_set_drvup(grp, config->drvup);
pinmux_set_drvdn(grp, config->drvdn);
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
pinmux_set_lpmd(grp, config->lpmd);
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
pinmux_set_schmt(grp, config->schmt);
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_HSM
pinmux_set_hsm(grp, config->hsm);
#endif
}
void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,

12
board/LaCie/edminiv2/config.mk
View file

@ -1,12 +0,0 @@
#
# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
#
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
# TEXT_BASE must equal the intended FLASH location of u-boot.
CONFIG_SYS_TEXT_BASE = 0xfff90000

70
board/LaCie/edminiv2/edminiv2.c
View file

@ -12,59 +12,11 @@
#include <miiphy.h>
#include <asm/arch/orion5x.h>
#include "../common/common.h"
#include <spl.h>
#include <ns16550.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH
* which CFI does not properly detect, hence the LEGACY config.
*/
#if defined(CONFIG_FLASH_CFI_LEGACY)
#include <flash.h>
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
{
int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;
int sect;
if (base != CONFIG_SYS_FLASH_BASE)
return 0;
info->size = 0;
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
/* set each sector's start address and size based */
for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) {
info->start[sect] = base+info->size;
info->size += sectsz[sect];
}
/* This flash must be accessed in 8-bits mode, no buffer. */
info->flash_id = 0x01000000;
info->portwidth = FLASH_CFI_8BIT;
info->chipwidth = FLASH_CFI_BY8;
info->buffer_size = 0;
/* timings are derived from the Macronix datasheet. */
info->erase_blk_tout = 1000;
info->write_tout = 10;
info->buffer_write_tout = 300;
/* Commands and addresses are for AMD mode 8-bit access. */
info->vendor = CFI_CMDSET_AMD_LEGACY;
info->cmd_reset = 0xF0;
info->interface = FLASH_CFI_X8;
info->legacy_unlock = 0;
info->ext_addr = 0;
info->addr_unlock1 = 0x00000aaa;
info->addr_unlock2 = 0x00000555;
/* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */
info->manufacturer_id = 0x22;
info->device_id = 0xBA;
info->device_id2 = 0;
info->cfi_version = 0x3133;
info->cfi_offset = 0x0000;
info->name = "MX29LV400CB";
return 1;
}
#endif /* CONFIG_SYS_FLASH_CFI */
int board_init(void)
{
/* arch number of board */
@ -83,3 +35,21 @@ void reset_phy(void)
mv_phy_88e1116_init("egiga0", 8);
}
#endif /* CONFIG_RESET_PHY_R */
/*
* SPL serial setup and NOR boot device selection
*/
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
preloader_console_init();
}
u32 spl_boot_device(void)
{
return BOOT_DEVICE_NOR;
}
#endif /* CONFIG_SPL_BUILD */

9
board/nvidia/common/board.c
View file

@ -21,6 +21,7 @@
#include <asm/arch/pwm.h>
#endif
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
@ -179,6 +180,14 @@ int board_late_init(void)
#ifdef CONFIG_LCD
/* Make sure we finish initing the LCD */
tegra_lcd_check_next_stage(gd->fdt_blob, 1);
#endif
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
if (tegra_cpu_is_non_secure()) {
printf("CPU is in NS mode\n");
setenv("cpu_ns_mode", "1");
} else {
setenv("cpu_ns_mode", "");
}
#endif
return 0;
}

2
board/nvidia/jetson-tk1/jetson-tk1.c
View file

@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR;
*/
void pinmux_init(void)
{
pinmux_set_tristate_input_clamping();
pinmux_clear_tristate_input_clamping();
gpio_config_table(jetson_tk1_gpio_inits,
ARRAY_SIZE(jetson_tk1_gpio_inits));

303
board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -15,77 +15,47 @@
static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
/* gpio, init_val */
GPIO_INIT(C7, IN),
GPIO_INIT(G0, OUT0),
GPIO_INIT(G1, OUT0),
GPIO_INIT(G0, IN),
GPIO_INIT(G1, IN),
GPIO_INIT(G2, IN),
GPIO_INIT(G3, IN),
GPIO_INIT(G4, IN),
GPIO_INIT(H2, OUT0),
GPIO_INIT(H3, OUT0),
GPIO_INIT(H4, IN),
GPIO_INIT(H5, OUT0),
GPIO_INIT(H6, IN),
GPIO_INIT(H7, OUT0),
GPIO_INIT(H7, IN),
GPIO_INIT(I0, OUT0),
GPIO_INIT(I2, OUT0),
GPIO_INIT(I4, OUT0),
GPIO_INIT(I5, IN),
GPIO_INIT(I1, IN),
GPIO_INIT(I6, IN),
GPIO_INIT(J0, IN),
GPIO_INIT(J2, IN),
GPIO_INIT(K1, OUT0),
GPIO_INIT(K2, IN),
GPIO_INIT(K3, IN),
GPIO_INIT(K4, OUT0),
GPIO_INIT(K5, OUT0),
GPIO_INIT(K6, OUT0),
GPIO_INIT(N7, IN),
GPIO_INIT(O0, IN),
GPIO_INIT(O1, IN),
GPIO_INIT(O2, IN),
GPIO_INIT(O3, IN),
GPIO_INIT(O4, IN),
GPIO_INIT(O5, IN),
GPIO_INIT(O6, OUT0),
GPIO_INIT(O7, IN),
GPIO_INIT(P0, OUT0),
GPIO_INIT(P1, OUT0),
GPIO_INIT(P2, OUT0),
GPIO_INIT(Q0, IN),
GPIO_INIT(Q1, IN),
GPIO_INIT(Q2, IN),
GPIO_INIT(Q3, IN),
GPIO_INIT(Q5, IN),
GPIO_INIT(Q6, IN),
GPIO_INIT(Q7, IN),
GPIO_INIT(R0, OUT0),
GPIO_INIT(R1, OUT0),
GPIO_INIT(R2, OUT0),
GPIO_INIT(R4, IN),
GPIO_INIT(R5, OUT0),
GPIO_INIT(R7, IN),
GPIO_INIT(S0, IN),
GPIO_INIT(S3, OUT0),
GPIO_INIT(S4, OUT0),
GPIO_INIT(S5, IN),
GPIO_INIT(S6, OUT0),
GPIO_INIT(S7, IN),
GPIO_INIT(T0, OUT0),
GPIO_INIT(T1, OUT0),
GPIO_INIT(U0, OUT0),
GPIO_INIT(T1, IN),
GPIO_INIT(U0, IN),
GPIO_INIT(U1, IN),
GPIO_INIT(U2, IN),
GPIO_INIT(U3, OUT0),
GPIO_INIT(U4, OUT0),
GPIO_INIT(U3, IN),
GPIO_INIT(U4, IN),
GPIO_INIT(U5, IN),
GPIO_INIT(U6, IN),
GPIO_INIT(V0, IN),
GPIO_INIT(V1, IN),
GPIO_INIT(W2, IN),
GPIO_INIT(W3, IN),
GPIO_INIT(X1, OUT0),
GPIO_INIT(X3, IN),
GPIO_INIT(X4, OUT0),
GPIO_INIT(X5, IN),
GPIO_INIT(X6, IN),
GPIO_INIT(X1, IN),
GPIO_INIT(X4, IN),
GPIO_INIT(X7, OUT0),
GPIO_INIT(BB3, OUT0),
GPIO_INIT(BB5, OUT0),
@ -93,10 +63,7 @@ static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
GPIO_INIT(BB7, OUT0),
GPIO_INIT(CC1, IN),
GPIO_INIT(CC2, IN),
GPIO_INIT(CC5, OUT0),
GPIO_INIT(EE1, OUT0),
GPIO_INIT(FF1, OUT0),
GPIO_INIT(FF2, IN),
GPIO_INIT(EE2, OUT1),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
@ -114,152 +81,152 @@ static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
/* pingrp, mux, pull, tri, e_input, od, rcv_sel */
PINCFG(CLK_32K_OUT_PA0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(UART3_CTS_N_PA1, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK_32K_OUT_PA0, SOC, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PB0, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PB1, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PB0, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PB1, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART2_RXD_PC3, IRDA, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(UART2_RXD_PC3, IRDA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(PC7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PG0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PG3, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PG1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PG2, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PG3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PG4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PG7, SPI4, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PI6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI6, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PJ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(UART2_CTS_N_PJ5, UARTB, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PJ0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART2_CTS_N_PJ5, UARTB, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PK3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SPDIF_OUT_PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SPDIF_IN_PK6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_FS_PN0, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_DIN_PN1, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_SCLK_PN3, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(USB_VBUS_EN0_PN4, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(USB_VBUS_EN1_PN5, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
PINCFG(ULPI_DATA7_PO0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA0_PO1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA1_PO2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA2_PO3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA3_PO4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA6_PO7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_FS_PP0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_DIN_PP1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, TRISTATE, INPUT, DEFAULT, NORMAL),
PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA0_PO1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA3_PO4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_DOUT_PP6, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_SCLK_PP7, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL0_PQ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL1_PQ1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL5_PQ5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL0_PQ0, DEFAULT, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL2_PQ2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL4_PQ4, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL5_PQ5, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL6_PQ6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL7_PQ7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW1_PR1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW2_PR2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW3_PR3, SYS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW4_PR4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW5_PR5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW7_PR7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW8_PS0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW9_PS1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW10_PS2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW13_PS5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW14_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW15_PS7, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW11_PS3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW12_PS4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW16_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PV0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PV1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU5, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PV0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PV1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
PINCFG(GPIO_W2_AUD_PW2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_W3_AUD_PW3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_W3_AUD_PW3, SPI6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X3_AUD_PX3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X5_AUD_PX5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X6_AUD_PX6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DIR_PY1, SPI1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_DAT3_PY4, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_DAT2_PY5, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_DAT1_PY6, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_DAT0_PY7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_CLK_PZ0, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_CMD_PZ1, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
@ -279,30 +246,30 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
PINCFG(PBB6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PCC1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PCC2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PCC1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PCC2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PEX_L0_RST_N_PDD1, PE0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PEX_WAKE_N_PDD3, PE, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PEX_WAKE_N_PDD3, PE, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PEX_L1_RST_N_PDD5, PE1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK3_REQ_PEE1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP_MCLK1_REQ_PEE2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(USB_VBUS_EN2_PFF1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(PFF2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DP_HPD_PFF0, DP, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CPU_PWR_REQ, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
PINCFG(CLK_32K_IN, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
};

12
common/board_f.c
View file

@ -360,6 +360,18 @@ static int setup_fdt(void)
/* Get the top of usable RAM */
__weak ulong board_get_usable_ram_top(ulong total_size)
{
#ifdef CONFIG_SYS_SDRAM_BASE
/*
* Detect whether we have so much RAM it goes past the end of our
* 32-bit address space. If so, clip the usable RAM so it doesn't.
*/
if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
/*
* Will wrap back to top of 32-bit space when reservations
* are made.
*/
return 0;
#endif
return gd->ram_top;
}

7
configs/edminiv2_defconfig
View file

@ -1,3 +1,4 @@
CONFIG_ARM=y
CONFIG_ORION5X=y
CONFIG_TARGET_EDMINIV2=y
CONFIG_SPL=y
+S:CONFIG_ARM=y
+S:CONFIG_ORION5X=y
+S:CONFIG_TARGET_EDMINIV2=y

31
include/configs/apalis_t30.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014 Marcel Ziswiler
* Copyright (c) 2014-2015 Marcel Ziswiler
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -22,8 +22,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_APALIS_T30
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C
@ -47,12 +45,8 @@
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
/* USB networking support */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
/* PCI host support */
#undef CONFIG_PCI /* just define once Tegra PCIe support got merged */
#define CONFIG_PCI
#define CONFIG_PCI_TEGRA
#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
@ -60,12 +54,31 @@
/* PCI networking support */
#define CONFIG_E1000
#undef CONFIG_E1000_NO_NVM /* just define once E1000 driver got fixed */
#define CONFIG_E1000_NO_NVM
/* General networking support */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
/* Miscellaneous commands */
#define CONFIG_CMD_SETEXPR
#define CONFIG_FAT_WRITE
/* Increase console I/O buffer size */
#undef CONFIG_SYS_CBSIZE
#define CONFIG_SYS_CBSIZE 1024
/* Increase arguments buffer size */
#undef CONFIG_SYS_BARGSIZE
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Increase print buffer size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Increase maximum number of arguments */
#undef CONFIG_SYS_MAXARGS
#define CONFIG_SYS_MAXARGS 32
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"

2
include/configs/beaver.h
View file

@ -36,8 +36,6 @@
#define MACH_TYPE_BEAVER 4597 /* not yet in mach-types.h */
#define CONFIG_MACH_TYPE MACH_TYPE_BEAVER
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C

2
include/configs/cardhu.h
View file

@ -39,8 +39,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C

2
include/configs/colibri_t20_iris.h
View file

@ -18,8 +18,6 @@
#define CONFIG_TEGRA_UARTA_SDIO1
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_BOARD_EARLY_INIT_F
/* SD/MMC support */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC

26
include/configs/colibri_t30.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014 Stefan Agner
* Copyright (c) 2013-2015 Stefan Agner
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -11,18 +11,17 @@
#include "tegra30-common.h"
/* High-level configuration options */
#define V_PROMPT "Colibri T30 # "
#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T30"
/* Board-specific config */
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T30
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C
@ -54,6 +53,25 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
/* Miscellaneous commands */
#define CONFIG_CMD_SETEXPR
#define CONFIG_FAT_WRITE
/* Increase console I/O buffer size */
#undef CONFIG_SYS_CBSIZE
#define CONFIG_SYS_CBSIZE 1024
/* Increase arguments buffer size */
#undef CONFIG_SYS_BARGSIZE
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Increase print buffer size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Increase maximum number of arguments */
#undef CONFIG_SYS_MAXARGS
#define CONFIG_SYS_MAXARGS 32
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"

2
include/configs/dalmore.h
View file

@ -32,8 +32,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_DALMORE
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C

29
include/configs/edminiv2.h
View file

@ -12,6 +12,31 @@
#ifndef _CONFIG_EDMINIV2_H
#define _CONFIG_EDMINIV2_H
/* general settings */
#define CONFIG_SYS_GENERIC_BOARD
/*
* SPL
*/
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NOR_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0xffff0000
#define CONFIG_SPL_MAX_SIZE 0x0000fff0
#define CONFIG_SPL_STACK 0x00020000
#define CONFIG_SPL_BSS_START_ADDR 0x00020000
#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff
#define CONFIG_SYS_SPL_MALLOC_START 0x00040000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds"
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_UBOOT_BASE 0xfff90000
#define CONFIG_SYS_UBOOT_START 0x00800000
#define CONFIG_SYS_TEXT_BASE 0x00800000
/*
* Version number information
*/
@ -89,13 +114,9 @@
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BASE 0xfff80000
#define CONFIG_SYS_FLASH_SECTSZ \
{16384, 8192, 8192, 32768, \
65536, 65536, 65536, 65536, 65536, 65536, 65536}
/* auto boot */
#define CONFIG_BOOTDELAY 3 /* default enable autoboot */

3
include/configs/harmony.h
View file

@ -27,9 +27,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC

2
include/configs/jetson-tk1.h
View file

@ -24,8 +24,6 @@
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C

4
include/configs/ls2085a_common.h
View file

@ -15,6 +15,10 @@
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
/* Errata fixes */
#define CONFIG_ARM_ERRATA_828024
#define CONFIG_ARM_ERRATA_826974
/* Link Definitions */
#define CONFIG_SYS_TEXT_BASE 0x30001000

3
include/configs/medcom-wide.h
View file

@ -20,9 +20,6 @@
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC

2
include/configs/nyan-big.h
View file

@ -21,8 +21,6 @@
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C

3
include/configs/paz00.h
View file

@ -30,9 +30,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC

3
include/configs/plutux.h
View file

@ -20,9 +20,6 @@
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC

3
include/configs/seaboard.h
View file

@ -32,9 +32,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C

2
include/configs/tec-ng.h
View file

@ -19,8 +19,6 @@
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C

3
include/configs/tec.h
View file

@ -20,9 +20,6 @@
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC

2
include/configs/tegra-common.h
View file

@ -150,6 +150,8 @@
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
/* Misc utility code */
#define CONFIG_BOUNCE_BUFFER

2
include/configs/trimslice.h
View file

@ -22,8 +22,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE
#define CONFIG_BOARD_EARLY_INIT_F
/* SPI */
#define CONFIG_TEGRA20_SFLASH
#define CONFIG_SPI_FLASH

2
include/configs/venice2.h
View file

@ -21,8 +21,6 @@
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C

3
include/configs/ventana.h
View file

@ -21,9 +21,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC

2
include/configs/whistler.h
View file

@ -22,8 +22,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C