Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-10 23:24:38 +00:00
Code Issues Projects Releases Packages Wiki Activity

Merge branch 'master' of git://git.denx.de/u-boot

Browse source
This commit is contained in:
Stefano Babic 2020-05-10 13:03:56 +02:00
commit b77d0292ca
845 changed files with 12206 additions and 6812 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.readthedocs.yml
View file

@ -7,7 +7,7 @@ version: 2
# Build documentation in the docs/ directory with Sphinx
sphinx:
configuration: docs/conf.py
configuration: doc/conf.py
# Optionally build your docs in additional formats such as PDF and ePub
formats: []

14
Kconfig
View file

@ -209,6 +209,20 @@ if EXPERT
When disabling this, please check if malloc calls, maybe
should be replaced by calloc - if one expects zeroed memory.
config SYS_MALLOC_DEFAULT_TO_INIT
bool "Default malloc to init while reserving the memory for it"
default n
help
It may happen that one needs to move the dynamic allocation
from one to another memory range, eg. when moving the malloc
from the limited static to a potentially large dynamic (DDR)
memory.
If so then on top of setting the updated memory aside one
needs to bring the malloc init.
If such a scenario is sought choose yes.
config TOOLS_DEBUG
bool "Enable debug information for tools"
help

3
MAINTAINERS
View file

@ -244,9 +244,12 @@ S: Maintained
F: arch/arm/mach-mediatek/
F: arch/arm/include/asm/arch-mediatek/
F: board/mediatek/
F: doc/device-tree-bindings/phy/phy-mtk-*
F: doc/device-tree-bindings/usb/mediatek,*
F: doc/README.mediatek
F: drivers/clk/mediatek/
F: drivers/mmc/mtk-sd.c
F: drivers/phy/phy-mtk-*
F: drivers/pinctrl/mediatek/
F: drivers/power/domain/mtk-power-domain.c
F: drivers/ram/mediatek/

6
Makefile
View file

@ -926,6 +926,9 @@ ALL-$(CONFIG_EFI_STUB) += u-boot-payload.efi
ifneq ($(BUILD_ROM)$(CONFIG_BUILD_ROM),)
ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
endif
ifeq ($(CONFIG_SYS_COREBOOT)$(CONFIG_SPL),yy)
ALL-$(CONFIG_BINMAN) += u-boot-x86-with-spl.bin
endif
# Build a combined spl + u-boot image for sunxi
ifeq ($(CONFIG_ARCH_SUNXI)$(CONFIG_SPL),yy)
@ -1626,6 +1629,9 @@ u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE
endif
endif
u-boot-x86-with-spl.bin: spl/u-boot-spl.bin u-boot.bin FORCE
$(call if_changed,binman)
ifneq ($(CONFIG_TEGRA),)
ifneq ($(CONFIG_BINMAN),)
# Makes u-boot-dtb-tegra.bin u-boot-tegra.bin u-boot-nodtb-tegra.bin

10
README
View file

@ -896,8 +896,6 @@ The following options need to be configured:
CONFIG_TULIP
Support for Digital 2114x chips.
Optional CONFIG_TULIP_SELECT_MEDIA for board specific
modem chip initialisation (KS8761/QS6611).
CONFIG_NATSEMI
Support for National dp83815 chips.
@ -2475,14 +2473,6 @@ Configuration Settings:
- CONFIG_SYS_BAUDRATE_TABLE:
List of legal baudrate settings for this board.
- CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END:
Begin and End addresses of the area used by the
simple memory test.
- CONFIG_SYS_MEMTEST_SCRATCH:
Scratch address used by the alternate memory test
You only need to set this if address zero isn't writeable
- CONFIG_SYS_MEM_RESERVE_SECURE
Only implemented for ARMv8 for now.
If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory

41
arch/arm/Kconfig
View file

@ -340,6 +340,34 @@ config SYS_CACHELINE_SIZE
default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
choice
prompt "Select the ARM data write cache policy"
default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
TARGET_BCMNSP || CPU_PXA || RZA1
default SYS_ARM_CACHE_WRITEBACK
config SYS_ARM_CACHE_WRITEBACK
bool "Write-back (WB)"
help
A write updates the cache only and marks the cache line as dirty.
External memory is updated only when the line is evicted or explicitly
cleaned.
config SYS_ARM_CACHE_WRITETHROUGH
bool "Write-through (WT)"
help
A write updates both the cache and the external memory system.
This does not mark the cache line as dirty.
config SYS_ARM_CACHE_WRITEALLOC
bool "Write allocation (WA)"
help
A cache line is allocated on a write miss. This means that executing a
store instruction on the processor might cause a burst read to occur.
There is a linefill to obtain the data for the cache line, before the
write is performed.
endchoice
config ARCH_CPU_INIT
bool "Enable ARCH_CPU_INIT"
help
@ -881,7 +909,7 @@ config ARCH_OWL
select CLK
select CLK_OWL
select OF_CONTROL
select CONFIG_SYS_RELOC_GD_ENV_ADDR
select SYS_RELOC_GD_ENV_ADDR
imply CMD_DM
config ARCH_QEMU
@ -1134,6 +1162,17 @@ config TARGET_VEXPRESS64_JUNO
bool "Support Versatile Express Juno Development Platform"
select ARM64
select PL01X_SERIAL
select DM
select OF_CONTROL
select OF_BOARD
select CLK
select DM_SERIAL
select ARM_PSCI_FW
select PSCI_RESET
select DM
select BLK
select USB
select DM_USB
config TARGET_LS2080A_EMU
bool "Support ls2080a_emu"

3
arch/arm/dts/Makefile
View file

@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-roc-cc.dtb \
rk3328-rock64.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \
@ -125,12 +126,14 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-leez-p710.dtb \
rk3399-nanopc-t4.dtb \
rk3399-nanopi-m4.dtb \
rk3399-nanopi-m4-2gb.dtb \
rk3399-nanopi-neo4.dtb \
rk3399-orangepi.dtb \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
rk3399-roc-pc.dtb \
rk3399-roc-pc-mezzanine.dtb \
rk3399-rock-pi-4.dtb \
rk3399-rock960.dtb \
rk3399-rockpro64.dtb

18
arch/arm/dts/armada-3720-uDPU.dts
View file

@ -109,11 +109,11 @@
&comphy {
phy0 {
phy-type = <PHY_TYPE_SGMII1>;
phy-speed = <PHY_SPEED_1_25G>;
phy-speed = <PHY_SPEED_3_125G>;
};
phy1 {
phy-type = <PHY_TYPE_SGMII0>;
phy-speed = <PHY_SPEED_1_25G>;
phy-speed = <PHY_SPEED_3_125G>;
};
phy2 {
@ -125,22 +125,16 @@
&eth0 {
pinctrl-0 = <&pcie_pins>;
status = "okay";
phy-mode = "sgmii";
phy-mode = "2500base-x";
managed = "in-band-status";
phy = <&ethphy0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&eth1 {
status = "okay";
phy-mode = "sgmii";
phy-mode = "2500base-x";
managed = "in-band-status";
phy = <&ethphy1>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&i2c0 {

10
arch/arm/dts/cros-ec-keyboard.dtsi
View file

@ -1,11 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Keyboard dts fragment for devices that use cros-ec-keyboard
*
* Copyright (c) 2014 Google, Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/input/input.h>
@ -22,6 +19,7 @@
MATRIX_KEY(0x00, 0x02, KEY_F1)
MATRIX_KEY(0x00, 0x03, KEY_B)
MATRIX_KEY(0x00, 0x04, KEY_F10)
MATRIX_KEY(0x00, 0x05, KEY_RO)
MATRIX_KEY(0x00, 0x06, KEY_N)
MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
@ -34,6 +32,7 @@
MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
MATRIX_KEY(0x01, 0x09, KEY_F9)
MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
MATRIX_KEY(0x01, 0x0c, KEY_HENKAN)
MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
MATRIX_KEY(0x02, 0x01, KEY_TAB)
@ -45,6 +44,7 @@
MATRIX_KEY(0x02, 0x07, KEY_102ND)
MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
MATRIX_KEY(0x02, 0x09, KEY_F8)
MATRIX_KEY(0x02, 0x0a, KEY_YEN)
MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
MATRIX_KEY(0x03, 0x02, KEY_F2)
@ -52,7 +52,9 @@
MATRIX_KEY(0x03, 0x04, KEY_F5)
MATRIX_KEY(0x03, 0x06, KEY_6)
MATRIX_KEY(0x03, 0x08, KEY_MINUS)
MATRIX_KEY(0x03, 0x09, KEY_F13)
MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
MATRIX_KEY(0x03, 0x0c, KEY_MUHENKAN)
MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
MATRIX_KEY(0x04, 0x01, KEY_A)

39
arch/arm/dts/cros-ec-sbs.dtsi
View file

@ -1,8 +1,45 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Smart battery dts fragment for devices that use cros-ec-sbs
*
* Copyright (c) 2015 Google, Inc
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
&i2c_tunnel {

8
arch/arm/dts/mt7629-rfb.dts
View file

@ -82,6 +82,14 @@
status = "okay";
};
&xhci {
status = "okay";
};
&u3phy {
status = "okay";
};
&watchdog {
pinctrl-names = "default";
pinctrl-0 = <&watchdog_pins>;

41
arch/arm/dts/mt7629.dtsi
View file

@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/mt7629-power.h>
#include <dt-bindings/reset/mt7629-reset.h>
#include <dt-bindings/phy/phy.h>
#include "skeleton.dtsi"
/ {
@ -222,6 +223,46 @@
#size-cells = <0>;
};
ssusbsys: ssusbsys@1a000000 {
compatible = "mediatek,mt7629-ssusbsys", "syscon";
reg = <0x1a000000 0x1000>;
#clock-cells = <1>;
};
xhci: usb@1a0c0000 {
compatible = "mediatek,mt7629-xhci", "mediatek,mtk-xhci";
reg = <0x1a0c0000 0x1000>, <0x1a0c3e00 0x0100>;
reg-names = "mac", "ippc";
power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
<&ssusbsys CLK_SSUSB_REF_EN>,
<&ssusbsys CLK_SSUSB_MCU_EN>,
<&ssusbsys CLK_SSUSB_DMA_EN>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
status = "disabled";
};
u3phy: usb-phy@1a0c4000 {
compatible = "mediatek,mt7629-tphy", "mediatek,generic-tphy-v2";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1a0c4000 0x1000>;
status = "disabled";
u2port0: usb-phy@0 {
reg = <0x0 0x0700>;
#phy-cells = <1>;
clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
clock-names = "ref";
};
u3port0: usb-phy@700 {
reg = <0x0700 0x0700>;
#phy-cells = <1>;
};
};
ethsys: syscon@1b000000 {
compatible = "mediatek,mt7629-ethsys", "syscon";
reg = <0x1b000000 0x1000>;

80
arch/arm/dts/px30-evb-u-boot.dtsi
View file

@ -1,84 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
* (C) Copyright 2020 Rockchip Electronics Co., Ltd
*/
/ {
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
};
#include "px30-u-boot.dtsi"
chosen {
u-boot,spl-boot-order = &emmc, &sdmmc;
};
};
&dmc {
u-boot,dm-pre-reloc;
};
&uart2 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&uart5 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
/* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
u-boot,spl-fifo-mode;
};
&emmc {
u-boot,dm-pre-reloc;
/* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
u-boot,spl-fifo-mode;
};
&grf {
u-boot,dm-pre-reloc;
};
&pmugrf {
u-boot,dm-pre-reloc;
};
&xin24m {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
&pmucru {
u-boot,dm-pre-reloc;
};
&saradc {
u-boot,dm-pre-reloc;
&rng {
status = "okay";
};
&gpio0 {
u-boot,dm-pre-reloc;
};
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpio2 {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};

1
arch/arm/dts/px30-evb.dts
View file

@ -8,7 +8,6 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "px30.dtsi"
#include "px30-evb-u-boot.dtsi"
/ {
model = "Rockchip PX30 EVB";

82
arch/arm/dts/px30-firefly-u-boot.dtsi
View file

@ -1,84 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
* (C) Copyright 2020 Rockchip Electronics Co., Ltd
*/
/ {
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
};
chosen {
u-boot,spl-boot-order = &emmc, &sdmmc;
};
};
&dmc {
u-boot,dm-pre-reloc;
};
&uart2 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&uart5 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&emmc {
u-boot,dm-pre-reloc;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&grf {
u-boot,dm-pre-reloc;
};
&pmugrf {
u-boot,dm-pre-reloc;
};
&xin24m {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
&pmucru {
u-boot,dm-pre-reloc;
};
&saradc {
u-boot,dm-pre-reloc;
status = "okay";
};
&gpio0 {
u-boot,dm-pre-reloc;
};
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpio2 {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
#include "px30-u-boot.dtsi"

90
arch/arm/dts/px30-u-boot.dtsi Normal file
View file

@ -0,0 +1,90 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
/ {
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
};
chosen {
u-boot,spl-boot-order = &emmc, &sdmmc;
};
rng: rng@ff0b0000 {
compatible = "rockchip,cryptov2-rng";
reg = <0x0 0xff0b0000 0x0 0x4000>;
status = "disabled";
};
};
&dmc {
u-boot,dm-pre-reloc;
};
&uart2 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&uart5 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&emmc {
u-boot,dm-pre-reloc;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&grf {
u-boot,dm-pre-reloc;
};
&pmugrf {
u-boot,dm-pre-reloc;
};
&xin24m {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
&pmucru {
u-boot,dm-pre-reloc;
};
&saradc {
u-boot,dm-pre-reloc;
status = "okay";
};
&gpio0 {
u-boot,dm-pre-reloc;
};
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpio2 {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};

39
arch/arm/dts/rk3328-evb-u-boot.dtsi
View file

@ -6,6 +6,45 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr3-666.dtsi"
/{
gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_clkin";
#clock-cells = <0>;
};
vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
regulator-name = "vcc5v0_host_xhci";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&gmac2io {
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
pinctrl-names = "default";
pinctrl-0 = <&rgmiim1_pins>;
tx_delay = <0x26>;
rx_delay = <0x11>;
status = "okay";
};
&gmac2phy {
/* Integrated PHY unsupported by U-boot */
status = "broken";
};
&usb_host0_xhci {
vbus-supply = <&vcc5v0_host_xhci>;
status = "okay";

222
arch/arm/dts/rk3328-evb.dts
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
@ -11,40 +11,51 @@
compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
chosen {
stdout-path = &uart2;
stdout-path = "serial2:1500000n8";
};
gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_clkin";
#clock-cells = <0>;
};
vcc3v3_sdmmc: sdmmc-pwren {
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_otg: vcc5v0-otg-drv {
compatible = "regulator-fixed";
enable-active-high;
regulator-name = "vcc5v0_otg";
gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
};
vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
enable-active-high;
regulator-name = "vcc5v0_host_xhci";
gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0m1_gpio>;
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_io>;
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc_phy: vcc-phy-regulator {
@ -55,96 +66,60 @@
};
};
&saradc {
status = "okay";
};
&uart2 {
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
status = "okay";
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
supports-emmc;
disable-wp;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
&gmac2io {
&gmac2phy {
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
pinctrl-names = "default";
pinctrl-0 = <&rgmiim1_pins>;
tx_delay = <0x26>;
rx_delay = <0x11>;
status = "okay";
};
clock_in_out = "output";
assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
assigned-clock-rate = <50000000>;
assigned-clocks = <&cru SCLK_MAC2PHY>;
assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb20_otg {
vbus-supply = <&vcc5v0_otg>;
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
i2c-scl-falling-time-ns = <4>;
status = "okay";
rk805: pmic@18 {
compatible = "rockchip,rk805";
status = "okay";
reg = <0x18>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
gpio-controller;
#gpio-cells = <2>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_io>;
vcc6-supply = <&vcc_io>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <6001>;
regulator-boot-on;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
@ -155,19 +130,18 @@
regulator-name = "vdd_arm";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <6001>;
regulator-boot-on;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-boot-on;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
@ -177,32 +151,32 @@
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vdd_18: LDO_REG1 {
regulator-name = "vdd_18";
vcc_18: LDO_REG1 {
regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_18emmc: LDO_REG2 {
regulator-name = "vcc_18emmc";
vcc18_emmc: LDO_REG2 {
regulator-name = "vcc18_emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
@ -213,8 +187,8 @@
regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
@ -227,9 +201,71 @@
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins =
<2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio2_a6 */
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdio {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
max-frequency = <150000000>;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
vmmc-supply = <&vcc_sd>;
status = "okay";
};
&tsadc {
status = "okay";
};
&uart2 {
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_host {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&usb20_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};

47
arch/arm/dts/rk3328-roc-cc-u-boot.dtsi Normal file
View file

@ -0,0 +1,47 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
*/
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr4-666.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
};
};
&gpio0 {
u-boot,dm-spl;
};
&pinctrl {
u-boot,dm-spl;
};
&sdmmc0m1_gpio {
u-boot,dm-spl;
};
&pcfg_pull_up_4ma {
u-boot,dm-spl;
};
&usb_host0_xhci {
vbus-supply = <&vcc_host1_5v>;
status = "okay";
};
/*
* This makes XHCI responsible for toggling VBUS. This is needed to work
* around an issue where either XHCI only works with USB 2.0 or OTG doesn't
* work, depending on how VBUS is configured. Having USB 3.0 seems better.
*/
&vcc_host1_5v {
/delete-property/ regulator-always-on;
};
/* Need this and all the pinctrl/gpio stuff above to set pinmux */
&vcc_sd {
u-boot,dm-spl;
};

354
arch/arm/dts/rk3328-roc-cc.dts Normal file
View file

@ -0,0 +1,354 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
*/
/dts-v1/;
#include "rk3328.dtsi"
/ {
model = "Firefly roc-rk3328-cc";
compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
chosen {
stdout-path = "serial2:1500000n8";
};
gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_clkin";
#clock-cells = <0>;
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0m1_gpio>;
regulator-boot-on;
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_io>;
};
vcc_sdio: sdmmcio-regulator {
compatible = "regulator-gpio";
gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>;
states = <1800000 0x1
3300000 0x0>;
regulator-name = "vcc_sdio";
regulator-type = "voltage";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb20_host_drv>;
regulator-name = "vcc_host1_5v";
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
power {
label = "firefly:blue:power";
linux,default-trigger = "heartbeat";
gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
default-state = "on";
mode = <0x23>;
};
user {
label = "firefly:yellow:user";
linux,default-trigger = "mmc1";
gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
default-state = "off";
mode = <0x05>;
};
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
max-frequency = <150000000>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vcc18_emmc>;
status = "okay";
};
&gmac2io {
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
clock_in_out = "input";
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmiim1_pins>;
snps,aal;
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
snps,rxpbl = <0x4>;
snps,txpbl = <0x4>;
tx_delay = <0x24>;
rx_delay = <0x18>;
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmiphy {
status = "okay";
};
&i2c1 {
status = "okay";
rk805: pmic@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
interrupt-parent = <&gpio1>;
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_io>;
vcc6-supply = <&vcc_io>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_io: DCDC_REG4 {
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_18: LDO_REG1 {
regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc18_emmc: LDO_REG2 {
regulator-name = "vcc18_emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_10: LDO_REG3 {
regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
};
};
};
&io_domains {
status = "okay";
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc18_emmc>;
vccio3-supply = <&vcc_sdio>;
vccio4-supply = <&vcc_18>;
vccio5-supply = <&vcc_io>;
vccio6-supply = <&vcc_io>;
pmuio-supply = <&vcc_io>;
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
usb20_host_drv: usb20-host-drv {
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vcc_sdio>;
status = "okay";
};
&tsadc {
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_host {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&uart2 {
status = "okay";
};
&usb20_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};

11
arch/arm/dts/rk3328-rock64-u-boot.dtsi
View file

@ -12,5 +12,16 @@
};
&usb_host0_xhci {
vbus-supply = <&vcc_host_5v>;
status = "okay";
};
/*
* This makes XHCI responsible for toggling VBUS. This is needed to work
* around an issue where either XHCI only works with USB 2.0 or OTG doesn't
* work, depending on how VBUS is configured. Having USB 3.0 seems better.
*/
&vcc_host_5v {
/delete-property/ regulator-always-on;
/delete-property/ regulator-boot-on;
};

132
arch/arm/dts/rk3328-rock64.dts
View file

@ -43,6 +43,17 @@
vin-supply = <&vcc_sys>;
};
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&usb20_host_drv>;
regulator-name = "vcc_host1_5v";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
@ -51,6 +62,56 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&ir_int>;
pinctrl-names = "default";
};
leds {
compatible = "gpio-leds";
power {
gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
linux,default-trigger = "mmc0";
};
standby {
gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
sound {
compatible = "audio-graph-card";
label = "rockchip,rk3328";
dais = <&i2s1_p0
&spdif_p0>;
};
spdif-dit {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
port {
dit_p0_0: endpoint {
remote-endpoint = <&spdif_p0_0>;
};
};
};
};
&codec {
mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
status = "okay";
port@0 {
codec_p0_0: endpoint {
remote-endpoint = <&i2s1_p0_0>;
};
};
};
&cpu0 {
@ -98,16 +159,26 @@
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmiphy {
status = "okay";
};
&i2c1 {
status = "okay";
rk805: rk805@18 {
rk805: pmic@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
@ -169,7 +240,7 @@
};
vcc_18: LDO_REG1 {
regulator-name = "vdd_18";
regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
@ -181,7 +252,7 @@
};
vcc18_emmc: LDO_REG2 {
regulator-name = "vcc_18emmc";
regulator-name = "vcc18_emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
@ -207,6 +278,18 @@
};
};
&i2s1 {
status = "okay";
i2s1_p0: port {
i2s1_p0_0: endpoint {
dai-format = "i2s";
mclk-fs = <256>;
remote-endpoint = <&codec_p0_0>;
};
};
};
&io_domains {
status = "okay";
@ -220,6 +303,12 @@
};
&pinctrl {
ir {
ir_int: ir-int {
rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
@ -245,6 +334,17 @@
status = "okay";
};
&spdif {
pinctrl-0 = <&spdifm0_tx>;
status = "okay";
spdif_p0: port {
spdif_p0_0: endpoint {
remote-endpoint = <&dit_p0_0>;
};
};
};
&spi0 {
status = "okay";
@ -257,10 +357,28 @@
};
};
&tsadc {
rockchip,hw-tshut-mode = <0>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart2 {
status = "okay";
};
&u2phy {
status = "okay";
u2phy_host: host-port {
status = "okay";
};
u2phy_otg: otg-port {
status = "okay";
};
};
&usb20_otg {
dr_mode = "host";
status = "okay";
@ -273,3 +391,11 @@
&usb_host0_ohci {
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};

4
arch/arm/dts/rk3328-u-boot.dtsi
View file

@ -62,3 +62,7 @@
/* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
u-boot,spl-fifo-mode;
};
&usb20_otg {
hnp-srp-disable;
};

1415
arch/arm/dts/rk3328.dtsi
View file

File diff suppressed because it is too large Load diff

12
arch/arm/dts/rk3399-evb-u-boot.dtsi
View file

@ -11,3 +11,15 @@
u-boot,spl-boot-order = &sdhci, &sdmmc;
};
};
&rng {
status = "okay";
};
&i2c0 {
u-boot,dm-pre-reloc;
};
&rk808 {
u-boot,dm-pre-reloc;
};

540
arch/arm/dts/rk3399-evb.dts
View file

@ -1,86 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
/ {
model = "Rockchip RK3399 Evaluation Board";
compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
"google,rk3399evb-rev2";
chosen {
stdout-path = &uart2;
};
vdd_center: vdd-center {
compatible = "pwm-regulator";
pwms = <&pwm3 0 25000 1>;
regulator-name = "vdd_center";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-init-microvolt = <950000>;
regulator-always-on;
regulator-boot-on;
status = "okay";
};
vccsys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vccsys";
regulator-boot-on;
regulator-always-on;
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
vcc5v0_host: vcc5v0-host-en {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
};
vcc5v0_typec0: vcc5v0-typec0-en {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_typec0";
gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
};
vcc5v0_typec1: vcc5v0-typec1-en {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_typec1";
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
backlight: backlight {
compatible = "pwm-backlight";
power-supply = <&vccsys>;
enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
@ -116,18 +48,98 @@
248 249 250 251 252 253 254 255>;
default-brightness-level = <200>;
pwms = <&pwm0 0 25000 0>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
pwm-delay-us = <10000>;
status = "disabled";
};
panel:panel {
compatible = "simple-panel";
power-supply = <&vcc33_lcd>;
edp_panel: edp-panel {
compatible ="lg,lp079qx1-sp0v";
backlight = <&backlight>;
/*enable-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;*/
status = "disabled";
enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
power-supply = <&vcc3v3_s0>;
port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
};
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
vdd_center: vdd-center {
compatible = "pwm-regulator";
pwms = <&pwm3 0 25000 0>;
regulator-name = "vdd_center";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
status = "okay";
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
vin-supply = <&vcc5v0_sys>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
};
&edp {
status = "okay";
force-hpd;
ports {
edp_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
edp_out_panel: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in_edp>;
};
};
};
};
@ -135,6 +147,244 @@
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
};
&i2c0 {
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio1>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
vcc10-supply = <&vcc3v3_sys>;
vcc11-supply = <&vcc3v3_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc1v8_pmu>;
regulators {
vdd_log: DCDC_REG1 {
regulator-name = "vdd_log";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-name = "vdd_cpu_l";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-name = "vcc_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc1v8_dvp: LDO_REG1 {
regulator-name = "vcc1v8_dvp";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v0_tp: LDO_REG2 {
regulator-name = "vcc3v0_tp";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_pmu: LDO_REG3 {
regulator-name = "vcc1v8_pmu";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_sd: LDO_REG4 {
regulator-name = "vcc_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcca3v0_codec: LDO_REG5 {
regulator-name = "vcca3v0_codec";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v5: LDO_REG6 {
regulator-name = "vcc_1v5";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcca1v8_codec: LDO_REG7 {
regulator-name = "vcca1v8_codec";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v0: LDO_REG8 {
regulator-name = "vcc_3v0";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc3v3_s3: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&pwm0 {
status = "okay";
};
@ -147,15 +397,6 @@
status = "okay";
};
&saradc {
status = "okay";
};
&sdmmc {
bus-width = <4>;
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
@ -164,6 +405,36 @@
status = "okay";
};
&pcie_phy {
status = "disabled";
};
&pcie0 {
ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>;
status = "disabled";
};
&u2phy0 {
status = "okay";
};
&u2phy0_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&u2phy1 {
status = "okay";
};
&u2phy1_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&uart2 {
status = "okay";
};
@ -176,11 +447,6 @@
status = "okay";
};
&usbdrd3_0 {
vbus-supply = <&vcc5v0_typec0>;
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
@ -189,92 +455,26 @@
status = "okay";
};
&usbdrd3_1 {
vbus-supply = <&vcc5v0_typec1>;
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
i2c-scl-falling-time-ns = <50>;
i2c-scl-rising-time-ns = <100>;
u-boot,dm-pre-reloc;
rk808: pmic@1b {
compatible = "rockchip,rk808";
clock-output-names = "xin32k", "wifibt_32kin";
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
reg = <0x1b>;
rockchip,system-power-controller;
#clock-cells = <1>;
u-boot,dm-pre-reloc;
status = "okay";
vcc12-supply = <&vcc3v3_sys>;
regulators {
vcc33_lcd: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc33_lcd";
};
};
};
};
&mipi_dsi {
status = "disabled";
rockchip,panel = <&panel>;
display-timings {
timing0 {
bits-per-pixel = <24>;
clock-frequency = <160000000>;
hfront-porch = <120>;
hsync-len = <20>;
hback-porch = <21>;
hactive = <1200>;
vfront-porch = <21>;
vsync-len = <3>;
vback-porch = <18>;
vactive = <1920>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
<1 21 RK_FUNC_GPIO &pcfg_pull_up>;
<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
pmic_dvs2: pmic-dvs2 {
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins =
<1 18 RK_FUNC_GPIO &pcfg_pull_down>;
<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&gmac {
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
tx_delay = <0x28>;
rx_delay = <0x11>;
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};

6
arch/arm/dts/rk3399-ficus.dts
View file

@ -146,6 +146,12 @@
};
};
&spi1 {
/* On both Low speed and High speed expansion */
cs-gpios = <0>, <&gpio4 RK_PA6 0>, <&gpio4 RK_PA7 0>;
status = "okay";
};
&usbdrd_dwc3_0 {
dr_mode = "host";
};

251
arch/arm/dts/rk3399-firefly.dts
View file

@ -1,19 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
/ {
model = "Firefly-RK3399 Board";
compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
chosen {
stdout-path = &uart2;
stdout-path = "serial2:1500000n8";
};
backlight: backlight {
@ -63,6 +64,48 @@
#clock-cells = <0>;
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
linux,code = <KEY_POWER>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
work-led {
label = "work";
default-state = "on";
gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
};
diy-led {
label = "diy";
default-state = "off";
gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
};
};
rt5640-sound {
compatible = "simple-audio-card";
simple-audio-card,name = "rockchip,rt5640-codec";
@ -102,15 +145,27 @@
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8>;
};
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_drv>;
pinctrl-0 = <&pcie_pwr_en>;
regulator-name = "vcc3v3_pcie";
regulator-always-on;
regulator-boot-on;
vin-supply = <&dc_12v>;
};
vcc3v3_sys: vcc3v3-sys {
@ -120,32 +175,29 @@
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_sys>;
};
/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc5v0_sys: vcc5v0-sys {
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
vin-supply = <&dc_12v>;
};
vdd_log: vdd-log {
@ -156,16 +208,7 @@
regulator-boot-on;
regulator-min-microvolt = <430000>;
regulator-max-microvolt = <1400000>;
regulator-init-microvolt = <950000>;
};
vccadc_ref: vccadc-ref {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_sys>;
};
};
@ -201,15 +244,22 @@
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc_phy>;
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x33>;
rx_delay = <0x45>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
@ -231,16 +281,16 @@
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
vcc10-supply = <&vcc3v3_sys>;
vcc11-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc_sys>;
vcc10-supply = <&vcc_sys>;
vcc11-supply = <&vcc_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc1v8_pmu>;
@ -301,12 +351,12 @@
};
};
vcc3v0_tp: LDO_REG2 {
regulator-name = "vcc3v0_tp";
vcc2v8_dvp: LDO_REG2 {
regulator-name = "vcc2v8_dvp";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
@ -324,8 +374,8 @@
};
};
vcc_sd: LDO_REG4 {
regulator-name = "vcc_sd";
vcc_sdio: LDO_REG4 {
regulator-name = "vcc_sdio";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
@ -382,7 +432,7 @@
};
};
vcc3v3_s3: SWITCH_REG1 {
vcc3v3_s3: vcc_lan: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
@ -412,7 +462,7 @@
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
@ -429,7 +479,7 @@
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
@ -476,19 +526,16 @@
&i2s0 {
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
#sound-dai-cells = <0>;
status = "okay";
};
&i2s1 {
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
#sound-dai-cells = <0>;
status = "okay";
};
&i2s2 {
#sound-dai-cells = <0>;
status = "okay";
};
@ -497,7 +544,7 @@
bt656-supply = <&vcc1v8_dvp>;
audio-supply = <&vcca1v8_codec>;
sdmmc-supply = <&vcc_sd>;
sdmmc-supply = <&vcc_sdio>;
gpio1830-supply = <&vcc_3v0>;
};
@ -509,7 +556,7 @@
ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn>;
pinctrl-0 = <&pcie_clkreqn_cpm>;
status = "okay";
};
@ -532,7 +579,7 @@
};
pcie {
pcie_drv: pcie-drv {
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
@ -570,10 +617,26 @@
};
usb2 {
host_vbus_drv: host-vbus-drv {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
wifi_host_wake_l: wifi-host-wake-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
work_led_gpio: work_led-gpio {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
diy_led_gpio: diy_led-gpio {
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {
@ -585,24 +648,70 @@
};
&saradc {
vref-supply = <&vccadc_ref>;
vref-supply = <&vcca1v8_s3>;
status = "okay";
};
&sdio0 {
/* WiFi & BT combo module Ampak AP6356S */
bus-width = <4>;
cap-sdio-irq;
cap-sd-highspeed;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
/* Power supply */
vqmmc-supply = &vcc1v8_s3; /* IO line */
vmmc-supply = &vcc_sdio; /* card's power */
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wake";
brcm,drive-strength = <5>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
status = "okay";
};
&sdhci {
bus-width = <8>;
keep-power-in-suspend;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&tcphy0 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
@ -662,3 +771,37 @@
&usb_host1_ohci {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "otg";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

16
arch/arm/dts/rk3399-gru-bob.dts
View file

@ -18,11 +18,11 @@
"google,bob", "google,gru", "rockchip,rk3399";
edp_panel: edp-panel {
compatible = "boe,nv101wxmn51", "simple-panel";
compatible = "boe,nv101wxmn51";
backlight = <&backlight>;
power-supply = <&pp3300_disp>;
ports {
port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
@ -68,12 +68,22 @@
&spi0 {
status = "okay";
cr50@0 {
compatible = "google,cr50";
reg = <0>;
interrupt-parent = <&gpio0>;
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&h1_int_od_l>;
spi-max-frequency = <800000>;
};
};
&pinctrl {
tpm {
h1_int_od_l: h1-int-od-l {
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};

40
arch/arm/dts/rk3399-gru-chromebook.dtsi
View file

@ -194,20 +194,25 @@
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44
45 46 47 48 49 50 51 52 53 54 55 56 57 58
59 60 61 62 63 64 65 66 67 68 69 70 71 72
73 74 75 76 77 78 79 80 81 82 83 84 85 86
87 88 89 90 91 92 93 94 95 96 97 98 99 100>;
default-brightness-level = <51>;
enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
power-supply = <&pp3300_disp>;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwm-delay-us = <10000>;
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l>;
wake_on_bt: wake-on-bt {
label = "Wake-on-Bluetooth";
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
wakeup-source;
};
};
};
&ppvar_bigcpu {
@ -232,7 +237,6 @@
&edp {
status = "okay";
rockchip,panel = <&edp_panel>;
ports {
edp_out: port@1 {
reg = <1>;
@ -287,11 +291,9 @@ ap_i2c_tp: &i2c5 {
#pwm-cells = <1>;
};
usbc_extcon1: extcon@1 {
usbc_extcon1: extcon1 {
compatible = "google,extcon-usbc-cros-ec";
google,usb-port-id = <1>;
#extcon-cells = <0>;
};
};
@ -361,27 +363,27 @@ ap_i2c_tp: &i2c5 {
&pinctrl {
discrete-regulators {
pp1500_en: pp1500-en {
rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO
&pcfg_pull_none>;
};
pp1800_audio_en: pp1800-audio-en {
rockchip,pins = <RK_GPIO0 2 RK_FUNC_GPIO
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO
&pcfg_pull_down>;
};
pp3000_en: pp3000-en {
rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO
&pcfg_pull_none>;
};
pp3300_disp_en: pp3300-disp-en {
rockchip,pins = <RK_GPIO4 27 RK_FUNC_GPIO
rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO
&pcfg_pull_none>;
};
wlan_module_pd_l: wlan-module-pd-l {
rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO
&pcfg_pull_down>;
};
};
@ -389,10 +391,10 @@ ap_i2c_tp: &i2c5 {
&wifi {
wifi_perst_l: wifi-perst-l {
rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
wlan_host_wake_l: wlan-host-wake-l {
rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};

34
arch/arm/dts/rk3399-gru-kevin.dts
View file

@ -39,11 +39,25 @@
};
edp_panel: edp-panel {
compatible = "sharp,lq123p1jx31", "simple-panel";
compatible = "sharp,lq123p1jx31";
backlight = <&backlight>;
power-supply = <&pp3300_disp>;
ports {
panel-timing {
clock-frequency = <266666667>;
hactive = <2400>;
hfront-porch = <48>;
hback-porch = <84>;
hsync-len = <32>;
hsync-active = <0>;
vactive = <1600>;
vfront-porch = <3>;
vback-porch = <120>;
vsync-len = <10>;
vsync-active = <0>;
};
port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
@ -118,13 +132,17 @@
map0 {
trip = <&ppvar_bigcpu_alert>;
cooling-device =
<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <4096>;
};
map1 {
trip = <&ppvar_bigcpu_alert>;
cooling-device =
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
@ -286,24 +304,24 @@ ap_i2c_dig: &i2c2 {
digitizer {
/* Has external pullup */
cpu1_dig_irq_l: cpu1-dig-irq-l {
rockchip,pins = <2 4 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
/* Has external pullup */
cpu1_dig_pdct_l: cpu1-dig-pdct-l {
rockchip,pins = <2 5 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
discrete-regulators {
cpu3_pen_pwr_en: cpu3-pen-pwr-en {
rockchip,pins = <4 30 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pen {
cpu1_pen_eject: cpu1-pen-eject {
rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};

89
arch/arm/dts/rk3399-gru.dtsi
View file

@ -11,13 +11,7 @@
/ {
chosen {
u-boot,dm-pre-reloc;
stdout-path = "serial2:115200n8";
u-boot,spl-boot-order = &spi_flash;
};
config {
u-boot,spl-payload-offset = <0x40000>;
};
/*
@ -268,17 +262,11 @@
pp5000_usb_a_vbus: pp5000 {
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l>;
wake_on_bt: wake-on-bt {
label = "Wake-on-Bluetooth";
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
wakeup-source;
};
ap_rtc_clk: ap-rtc-clk {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "xin32k";
#clock-cells = <0>;
};
max98357a: max98357a {
@ -549,8 +537,7 @@ ap_i2c_audio: &i2c8 {
pinctrl-names = "default", "sleep";
pinctrl-1 = <&spi1_sleep>;
spi_flash: spiflash@0 {
u-boot,dm-pre-reloc;
spiflash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
@ -565,16 +552,12 @@ ap_i2c_audio: &i2c8 {
&spi5 {
status = "okay";
spi-activate-delay = <100>;
spi-max-frequency = <3000000>;
spi-deactivate-delay = <200>;
cros_ec: ec@0 {
compatible = "google,cros-ec-spi";
reg = <0>;
interrupt-parent = <&gpio0>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
ec-interrupt = <&gpio0 1 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ec_ap_int_l>;
spi-max-frequency = <3000000>;
@ -586,11 +569,9 @@ ap_i2c_audio: &i2c8 {
#size-cells = <0>;
};
usbc_extcon0: extcon@0 {
usbc_extcon0: extcon0 {
compatible = "google,extcon-usbc-cros-ec";
google,usb-port-id = <0>;
#extcon-cells = <0>;
};
};
};
@ -692,29 +673,29 @@ ap_i2c_audio: &i2c8 {
backlight-enable {
bl_en: bl-en {
rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
cros-ec {
ec_ap_int_l: ec-ap-int-l {
rockchip,pins = <RK_GPIO0 1 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
discrete-regulators {
sd_io_pwr_en: sd-io-pwr-en {
rockchip,pins = <RK_GPIO2 2 RK_FUNC_GPIO
rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO
&pcfg_pull_none>;
};
sd_pwr_1800_sel: sd-pwr-1800-sel {
rockchip,pins = <RK_GPIO2 28 RK_FUNC_GPIO
rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO
&pcfg_pull_none>;
};
sd_slot_pwr_en: sd-slot-pwr-en {
rockchip,pins = <RK_GPIO4 29 RK_FUNC_GPIO
rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO
&pcfg_pull_none>;
};
};
@ -722,17 +703,17 @@ ap_i2c_audio: &i2c8 {
codec {
/* Has external pullup */
headset_int_l: headset-int-l {
rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
};
mic_int: mic-int {
rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>;
rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
max98357a {
sdmode_en: sdmode-en {
rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>;
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
@ -743,7 +724,7 @@ ap_i2c_audio: &i2c8 {
* to hack this as gpio, so the EP could be able to
* de-assert it along and make ClockPM(CPM) work.
*/
rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@ -754,20 +735,20 @@ ap_i2c_audio: &i2c8 {
*/
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins =
<4 8 RK_FUNC_1 &pcfg_pull_none_8ma>,
<4 9 RK_FUNC_1 &pcfg_pull_none_8ma>,
<4 10 RK_FUNC_1 &pcfg_pull_none_8ma>,
<4 11 RK_FUNC_1 &pcfg_pull_none_8ma>;
<4 RK_PB0 1 &pcfg_pull_none_8ma>,
<4 RK_PB1 1 &pcfg_pull_none_8ma>,
<4 RK_PB2 1 &pcfg_pull_none_8ma>,
<4 RK_PB3 1 &pcfg_pull_none_8ma>;
};
sdmmc_clk: sdmmc-clk {
rockchip,pins =
<4 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
<4 RK_PB4 1 &pcfg_pull_none_8ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins =
<4 13 RK_FUNC_1 &pcfg_pull_none_8ma>;
<4 RK_PB5 1 &pcfg_pull_none_8ma>;
};
/*
@ -781,12 +762,12 @@ ap_i2c_audio: &i2c8 {
*/
sdmmc_cd: sdmmc-cd {
rockchip,pins =
<0 7 RK_FUNC_1 &pcfg_pull_none>;
<0 RK_PA7 1 &pcfg_pull_none>;
};
/* This is where we actually hook up CD; has external pull */
sdmmc_cd_gpio: sdmmc-cd-gpio {
rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@ -796,47 +777,47 @@ ap_i2c_audio: &i2c8 {
* Pull down SPI1 CLK/CS/RX/TX during suspend, to
* prevent leakage.
*/
rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>,
<1 10 RK_FUNC_GPIO &pcfg_pull_down>,
<1 7 RK_FUNC_GPIO &pcfg_pull_down>,
<1 8 RK_FUNC_GPIO &pcfg_pull_down>;
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>,
<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>,
<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>,
<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
touchscreen {
touch_int_l: touch-int-l {
rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
};
touch_reset_l: touch-reset-l {
rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
trackpad {
ap_i2c_tp_pu_en: ap-i2c-tp-pu-en {
rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>;
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>;
};
trackpad_int_l: trackpad-int-l {
rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
wifi: wifi {
wlan_module_reset_l: wlan-module-reset-l {
rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
/* Kevin has an external pull up, but Gru does not */
rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
write-protect {
ap_fw_wp: ap-fw-wp {
rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};

3
arch/arm/dts/rk3399-khadas-edge.dtsi
View file

@ -654,9 +654,12 @@
sd-uhs-sdr104;
vqmmc-supply = <&vcc1v8_s3>;
vmmc-supply = <&vccio_sd>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;

36
arch/arm/dts/rk3399-leez-p710.dts
View file

@ -42,14 +42,14 @@
regulator-max-microvolt = <5000000>;
};
vcc5v0_sys: vcc5v0-sys {
vcc3v3_lan: vcc3v3-lan {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-name = "vcc3v3_lan";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc5v_adp>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vim-supply = <&vcc3v3_sys>;
};
vcc3v3_sys: vcc3v3-sys {
@ -83,14 +83,14 @@
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_lan: vcc3v3-lan {
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_lan";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vim-supply = <&vcc3v3_sys>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc5v_adp>;
};
vdd_log: vdd-log {
@ -510,6 +510,14 @@
};
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
@ -522,14 +530,6 @@
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&tcphy0 {
status = "okay";
};

47
arch/arm/dts/rk3399-nanopc-t4.dts
View file

@ -52,13 +52,58 @@
pinctrl-names = "default";
pinctrl-0 = <&ir_rx>;
};
fan: pwm-fan {
compatible = "pwm-fan";
/*
* With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels
* work out to 0, ~1200, ~3000, and 5000RPM respectively.
*/
cooling-levels = <0 12 18 255>;
#cooling-cells = <2>;
fan-supply = <&vcc12v0_sys>;
pwms = <&pwm1 0 50000 0>;
};
};
&cpu_thermal {
trips {
cpu_warm: cpu_warm {
temperature = <55000>;
hysteresis = <2000>;
type = "active";
};
cpu_hot: cpu_hot {
temperature = <65000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map2 {
trip = <&cpu_warm>;
cooling-device = <&fan THERMAL_NO_LIMIT 1>;
};
map3 {
trip = <&cpu_hot>;
cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
};
};
};
&pcie0 {
num-lanes = <4>;
vpcie3v3-supply = <&vcc3v3_sys>;
};
&pinctrl {
ir {
ir_rx: ir-rx {
/* external pullup to VCC3V3_SYS, despite being 1.8V :/ */
rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>;
};
};
};

8
arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi Normal file
View file

@ -0,0 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
* Copyright (C) 2020 Deepak Das <deepakdas.linux@gmail.com>
*/
#include "rk3399-nanopi4-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1866.dtsi"

66
arch/arm/dts/rk3399-nanopi-m4-2gb.dts Normal file
View file

@ -0,0 +1,66 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* FriendlyElec NanoPi M4 board device tree source
*
* Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyarm.com)
*
* Copyright (c) 2018 Collabora Ltd.
* Copyright (c) 2019 Arm Ltd.
*/
/dts-v1/;
#include "rk3399-nanopi4.dtsi"
/ {
model = "FriendlyElec NanoPi M4";
compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
vdd_5v: vdd-5v {
compatible = "regulator-fixed";
regulator-name = "vdd_5v";
regulator-always-on;
regulator-boot-on;
};
vcc5v0_core: vcc5v0-core {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_core";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vdd_5v>;
};
vcc5v0_usb1: vcc5v0-usb1 {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb1";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_usb2: vcc5v0-usb2 {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb2";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
};
&vcc3v3_sys {
vin-supply = <&vcc5v0_core>;
};
&u2phy0_host {
phy-supply = <&vcc5v0_usb1>;
};
&u2phy1_host {
phy-supply = <&vcc5v0_usb2>;
};
&vbus_typec {
regulator-always-on;
vin-supply = <&vdd_5v>;
};

66
arch/arm/dts/rk3399-nanopi4.dtsi
View file

@ -48,7 +48,7 @@
};
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
vcc1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
@ -71,6 +71,27 @@
vin-supply = <&vcc3v3_sys>;
};
/*
* Really, this is supplied by vcc_1v8, and vcc1v8_s3 only
* drives the enable pin, but we can't quite model that.
*/
vcca0v9_s3: vcca0v9-s3 {
compatible = "regulator-fixed";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vcca0v9_s3";
vin-supply = <&vcc1v8_s3>;
};
/* As above, actually supplied by vcc3v3_sys */
vcca1v8_s3: vcca1v8-s3 {
compatible = "regulator-fixed";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_s3";
vin-supply = <&vcc1v8_s3>;
};
vbus_typec: vbus-typec {
compatible = "regulator-fixed";
regulator-min-microvolt = <5000000>;
@ -148,15 +169,28 @@
assigned-clocks = <&cru SCLK_RMII_SRC>;
clock_in_out = "input";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
phy-handle = <&rtl8211e>;
phy-mode = "rgmii";
phy-supply = <&vcc3v3_s3>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
rtl8211e: phy@1 {
reg = <1>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
};
};
};
&gpu {
@ -171,6 +205,10 @@
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <160>;
@ -446,6 +484,10 @@
status = "okay";
};
&i2s2 {
status = "okay";
};
&io_domains {
bt656-supply = <&vcc_1v8>;
audio-supply = <&vcca1v8_codec>;
@ -464,7 +506,9 @@
&pcie0 {
ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
max-link-speed = <2>;
num-lanes = <4>;
num-lanes = <2>;
vpcie0v9-supply = <&vcca0v9_s3>;
vpcie1v8-supply = <&vcca1v8_s3>;
status = "okay";
};
@ -481,6 +525,16 @@
};
};
phy {
phy_intb: phy-intb {
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
phy_rstb: phy-rstb {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
cpu_b_sleep: cpu-b-sleep {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;

79
arch/arm/dts/rk3399-orangepi.dts
View file

@ -136,13 +136,13 @@
vin-supply = <&vcc_sys>;
};
vcc5v0_typec0: vcc5v0-typec0-regulator {
vbus_typec: vbus-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec0_en>;
regulator-name = "vcc5v0_typec0";
pinctrl-0 = <&vcc5v0_typec_en>;
regulator-name = "vbus_typec";
vin-supply = <&vcc_sys>;
};
@ -202,14 +202,27 @@
clock_in_out = "input";
phy-supply = <&vcc3v3_s3>;
phy-mode = "rgmii";
phy-handle = <&rtl8211e>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
rtl8211e: phy@1 {
reg = <1>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
};
};
};
&gpu {
@ -419,6 +432,8 @@
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&cpu_b_sleep>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@ -436,6 +451,8 @@
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&gpu_sleep>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@ -472,6 +489,7 @@
compatible = "asahi-kasei,ak09911";
reg = <0x0c>;
vdd-supply = <&vcc3v3_s3>;
vid-supply = <&vcc3v3_s3>;
};
mpu6500@68 {
@ -504,6 +522,16 @@
pinctrl-0 = <&light_int_l>;
vdd-supply = <&vcc3v3_s3>;
};
fusb302@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&chg_cc_int_l>;
vbus-supply = <&vbus_typec>;
};
};
&io_domains {
@ -526,7 +554,25 @@
};
};
phy {
phy_intb: phy-intb {
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
phy_rstb: phy-rstb {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
cpu_b_sleep: cpu-b-sleep {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
gpu_sleep: gpu-sleep {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
pmic_int_l: pmic-int-l {
rockchip,pins =
<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
@ -536,7 +582,7 @@
sd {
sdmmc0_pwr_h: sdmmc0-pwr-h {
rockchip,pins =
<RK_GPIO0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
<0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@ -546,7 +592,7 @@
<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_typec0_en: vcc5v0-typec0-en {
vcc5v0_typec_en: vcc5v0-typec-en {
rockchip,pins =
<1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
@ -595,6 +641,12 @@
rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
fusb302 {
chg_cc_int_l: chg-cc-int-l {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pwm0 {
@ -631,9 +683,12 @@
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
@ -676,7 +731,7 @@
status = "okay";
u2phy0_otg: otg-port {
phy-supply = <&vcc5v0_typec0>;
phy-supply = <&vbus_typec>;
status = "okay";
};
@ -707,12 +762,14 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
clock-names = "ext_clock";
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>;
vbat-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8>;
};
};

31
arch/arm/dts/rk3399-puma-u-boot.dtsi
View file

@ -13,7 +13,7 @@
chosen {
stdout-path = "serial0:115200n8";
u-boot,spl-boot-order = \
"same-as-spl", &spiflash, &sdhci, &sdmmc;
"same-as-spl", &norflash, &sdhci, &sdmmc;
};
aliases {
@ -21,4 +21,33 @@
spi1 = &spi5;
};
/*
* The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
* eMMC and SPI flash powered-down initially (in fact it keeps the
* reset signal asserted). Even though it is an enable signal, we
* model this as a regulator.
*/
bios_enable: bios_enable {
compatible = "regulator-fixed";
u-boot,dm-pre-reloc;
regulator-name = "bios_enable";
enable-active-high;
gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&norflash {
u-boot,dm-pre-reloc;
};

602
arch/arm/dts/rk3399-puma.dtsi
View file

@ -1,30 +1,74 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
*/
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
/ {
model = "Theobroma Systems RK3399-Q7 SoM";
compatible = "tsd,rk3399-q7", "tsd,puma", "rockchip,rk3399";
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins_puma>;
pinctrl-0 = <&led_pin_module>;
module_led {
module-led {
label = "module_led";
gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
panic-indicator;
};
};
sd_card_led {
label = "sd_card_led";
gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
/*
* Overwrite the opp-table for CPUB as this board uses a different
* regulator (FAN53555) that only allows 10mV steps and therefore
* can't reach the operation point target voltages from rk3399-opp.dtsi
*/
/delete-node/ opp-table1;
cluster1_opp: opp-table1 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <800000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <800000>;
};
opp02 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <830000>;
opp-suspend;
};
opp03 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <880000>;
};
opp04 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <950000>;
};
opp05 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1030000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <1100000>;
};
opp07 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1200000>;
};
opp08 {
opp-hz = /bits/ 64 <1992000000>;
opp-microvolt = <1230000>;
turbo-mode;
};
};
@ -35,79 +79,14 @@
#clock-cells = <0>;
};
dw_hdmi_audio: dw-hdmi-audio {
status = "enabled";
compatible = "rockchip,dw-hdmi-audio";
#sound-dai-cells = <0>;
};
hdmi_codec: hdmi-codec {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "HDMI-CODEC";
simple-audio-card,cpu {
sound-dai = <&i2s2>;
};
simple-audio-card,codec {
sound-dai = <&hdmi>;
};
};
hdmi_sound: hdmi-sound {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,hdmi";
simple-audio-card,cpu {
sound-dai = <&i2s2>;
};
simple-audio-card,codec {
sound-dai = <&hdmi>;
};
};
usbhub_enable: usbhub_enable {
vcc1v2_phy: vcc1v2-phy {
compatible = "regulator-fixed";
regulator-name = "usbhub_enable";
enable-active-low;
gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
/*
* The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
* eMMC and SPI flash powered-down initially (in fact it keeps the
* reset signal asserted). Even though it is an enable signal, we
* model this as a regulator.
*/
bios_enable: bios_enable {
compatible = "regulator-fixed";
u-boot,dm-pre-reloc;
regulator-name = "bios_enable";
enable-active-high;
gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
regulator-name = "vcc1v2_phy";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vccadc_ref: vccadc-ref {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_sys: vcc3v3-sys {
@ -117,16 +96,18 @@
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_otg: vcc5v0-otg-regulator {
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
enable-active-low;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc5v0_otg";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
regulator-always-on;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_sys: vcc5v0-sys {
@ -137,48 +118,55 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
regulator-name = "vdd_log";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <950000>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&emmc_phy {
status = "okay";
drive-impedance-ohm = <33>;
};
&gmac {
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <2 10000 50000>;
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc1v2_phy>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x10>;
rx_delay = <0x10>;
status = "okay";
};
&hdmi {
#sound-dai-cells = <0>;
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
@ -188,37 +176,17 @@
i2c-scl-falling-time-ns = <4>;
clock-frequency = <400000>;
vdd_gpu: vdd_gpu {
status = "okay";
compatible = "fcs,fan53555";
reg = <0x60>;
vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_sys>;
regulator-compatible = "fan53555-reg";
regulator-name = "vdd_gpu";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1230000>;
regulator-ramp-delay = <1000>;
fcs,suspend-voltage-selector = <1>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio1>;
interrupts = <22 IRQ_TYPE_LEVEL_LOW>; // TODO check interrupt?
interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
@ -235,44 +203,44 @@
regulators {
vdd_center: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd_center";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-name = "vdd_center";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd_cpu_l";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-name = "vdd_cpu_l";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
@ -280,32 +248,32 @@
};
vcc_ldo1: LDO_REG1 {
regulator-boot-on;
regulator-name = "vcc_ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_ldo1";
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_hdmi: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc1v8_hdmi";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_hdmi";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_pmu: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc1v8_pmu";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
@ -313,11 +281,11 @@
};
vcc_sd: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc_sd";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
@ -325,79 +293,105 @@
};
vcc_ldo5: LDO_REG5 {
regulator-boot-on;
regulator-name = "vcc_ldo5";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc_ldo5";
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ldo6: LDO_REG6 {
regulator-boot-on;
regulator-name = "vcc_ldo6";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc_ldo6";
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc0v9_hdmi: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc0v9_hdmi";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vcc0v9_hdmi";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_efuse: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_efuse";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_efuse";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s3: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc3v3_s3";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_gpu: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1230000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
};
&i2c7 {
status = "okay";
clock-frequency = <400000>;
fan: fan@18 {
compatible = "ti,amc6821";
reg = <0x18>;
#cooling-cells = <2>;
};
rtc_twi: rtc@6f {
compatible = "isil,isl1208";
reg = <0x6f>;
};
};
&i2c8 {
status = "okay";
clock-frequency = <400000>;
vdd_cpu_b: vdd_cpu_b {
status = "okay";
vdd_cpu_b: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
vsel-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_sys>;
regulator-compatible = "fan53555-reg";
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1230000>;
@ -405,48 +399,36 @@
fcs,suspend-voltage-selector = <1>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2s0 {
pinctrl-0 = <&i2s0_2ch_bus>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "okay";
rockchip,i2s-broken-burst-len;
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
#sound-dai-cells = <0>;
};
&i2s2 {
#sound-dai-cells = <0>;
status = "okay";
/*
* As Q7 does not specify neither a global nor a RX clock for I2S these
* signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO.
* Therefore we have to redefine the i2s0_2ch_bus definition to prevent
* conflicts.
*/
&i2s0_2ch_bus {
rockchip,pins =
<3 RK_PD0 1 &pcfg_pull_none>,
<3 RK_PD2 1 &pcfg_pull_none>,
<3 RK_PD3 1 &pcfg_pull_none>,
<3 RK_PD7 1 &pcfg_pull_none>;
};
&io_domains {
status = "okay";
bt656-supply = <&vcc_1v8>; /* bt656_gpio2ab_ms */
audio-supply = <&vcc_1v8>; /* audio_gpio3d4a_ms */
sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
gpio1830-supply = <&vcc_1v8>; /* gpio1833_gpio4cd_ms */
};
&pcie0 {
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
assigned-clock-rates = <100000000>;
ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn>;
status = "okay";
};
&pcie_phy {
status = "okay";
bt656-supply = <&vcc_1v8>;
audio-supply = <&vcc_1v8>;
sdmmc-supply = <&vcc_sd>;
gpio1830-supply = <&vcc_1v8>;
};
&pmu_io_domains {
@ -454,195 +436,99 @@
pmu1830-supply = <&vcc_1v8>;
};
&pwm0 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
supports-emmc;
non-removable;
keep-power-in-suspend;
mmc-hs400-enhanced-strobe;
status = "okay";
};
&sdmmc {
clock-frequency = <150000000>;
max-frequency = <40000000>;
supports-sd;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
num-slots = <1>;
vqmmc-supply = <&vcc_sd>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "disabled";
};
&usb_host0_ohci {
status = "disabled";
};
&usbdrd3_0 {
status = "okay";
};
&usb_host1_ehci {
status = "disabled";
};
&usb_host1_ohci {
status = "disabled";
};
&usbdrd3_1 {
status = "okay";
tsd,usb-port-power = "usbhub_enable";
};
&vopb {
status = "okay";
};
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&pinctrl {
/* Pins that are not explicitely used by any devices */
pinctrl-names = "default";
pinctrl-0 = <&puma_pin_hog>;
hog {
puma_pin_hog: puma_pin_hog {
i2c8 {
i2c8_xfer_a: i2c8-xfer {
rockchip,pins =
/* We need pull-ups on Q7 buttons */
<RK_GPIO0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, /* LID_BTN# */
<RK_GPIO0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, /* BATLOW# */
<RK_GPIO0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, /* SLP_BTN# */
<RK_GPIO0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; /* BIOS_DISABLE# */
<1 RK_PC4 1 &pcfg_pull_up>,
<1 RK_PC5 1 &pcfg_pull_up>;
};
};
leds {
led_pin_module: led-module-gpio {
rockchip,pins =
<2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
<RK_GPIO1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
<1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds_pins_puma: led_pins@0 {
rockchip,pins =
<RK_GPIO2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>,
<RK_GPIO1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
usb2 {
otg_vbus_drv: otg-vbus-drv {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins =
<RK_GPIO0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
host_vbus_drv: host-vbus-drv {
rockchip,pins =
<RK_GPIO4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
i2c8 {
i2c8_xfer_a: i2c8-xfer {
rockchip,pins =
<RK_GPIO1 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
<RK_GPIO1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
<4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
};
&i2c2 {
status = "okay";
clock-frequency = <400000>;
};
&i2c4 {
status = "okay";
clock-frequency = <400000>;
};
&i2c6 {
status = "okay";
clock-frequency = <400000>;
};
&i2c6_xfer {
/* Enable pull-ups, the pins would float otherwise. */
rockchip,pins =
<RK_GPIO2 RK_PB2 RK_FUNC_2 &pcfg_pull_up>,
<RK_GPIO2 RK_PB1 RK_FUNC_2 &pcfg_pull_up>;
};
&i2c7 {
status = "okay";
clock-frequency = <400000>;
rtc_twi: rtc@6f {
compatible = "isil,isl1208";
reg = <0x6f>;
};
fan: fan@18 {
compatible = "ti,amc6821";
reg = <0x18>;
cooling-min-state = <0>;
cooling-max-state = <9>;
#cooling-cells = <2>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts>;
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&sdmmc {
vqmmc-supply = <&vcc_sd>;
};
&spi1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
spiflash: w25q32dw@0 {
u-boot,dm-pre-reloc;
norflash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <49500000>;
spi-cpol;
spi-cpha;
spi-max-frequency = <50000000>;
};
};
&spi5 {
&tcphy1 {
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy1 {
status = "okay";
u2phy1_otg: otg-port {
status = "okay";
};
u2phy1_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};

6
arch/arm/dts/rk3399-roc-pc-mezzanine-u-boot.dtsi Normal file
View file

@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2020 Amarula Solutions(India)
*/
#include "rk3399-roc-pc-u-boot.dtsi"

93
arch/arm/dts/rk3399-roc-pc-mezzanine.dts Normal file
View file

@ -0,0 +1,93 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
* Copyright (c) 2019 Markus Reichl <m.reichl@fivetechno.de>
*/
/dts-v1/;
#include "rk3399-roc-pc.dtsi"
/ {
model = "Firefly ROC-RK3399-PC Mezzanine Board";
compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
vcc3v3_ngff: vcc3v3-ngff {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_ngff";
enable-active-high;
gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_ngff_en>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
};
vcc3v3_pcie: vcc3v3-pcie {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
enable-active-high;
gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_pcie_en>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
};
};
&pcie_phy {
status = "okay";
};
&pcie0 {
ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_perst>;
vpcie3v3-supply = <&vcc3v3_pcie>;
vpcie1v8-supply = <&vcc1v8_pmu>;
vpcie0v9-supply = <&vcca_0v9>;
status = "okay";
};
&pinctrl {
ngff {
vcc3v3_ngff_en: vcc3v3-ngff-en {
rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
vcc3v3_pcie_en: vcc3v3-pcie-en {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_perst: pcie-perst {
rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdio0 {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_ngff>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
};

36
arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
View file

@ -14,9 +14,45 @@
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
vcc_hub_en: vcc_hub_en-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&hub_rst>;
regulator-name = "vcc_hub_en";
regulator-always-on;
};
};
/*
* should be placed inside mp8859, but not until mp8859 has
* its own dt-binding.
*/
&dc_12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
vin-supply = <&vcc_vbus_typec0>;
};
&vdd_log {
regulator-min-microvolt = <430000>;
regulator-init-microvolt = <950000>;
};
&vcc5v0_host {
regulator-always-on;
};
&vcc_sys {
regulator-always-on;
};
&vcc_sdio {
regulator-always-on;
};

3
arch/arm/dts/rk3399-roc-pc.dts
View file

@ -8,6 +8,5 @@
/ {
model = "Firefly ROC-RK3399-PC Board";
compatible = "libretech,roc-rk3399-pc", "firefly,roc-rk3399-pc",
"rockchip,rk3399";
compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
};

35
arch/arm/dts/rk3399-roc-pc.dtsi
View file

@ -110,20 +110,6 @@
regulator-max-microvolt = <5000000>;
};
/*
* should be placed inside mp8859, but not until mp8859 has
* its own dt-binding.
*/
dc_12v: mp8859-dcdc1 {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
vin-supply = <&vcc_vbus_typec0>;
};
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
@ -176,7 +162,6 @@
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en &hub_rst>;
regulator-name = "vcc5v0_host";
regulator-always-on;
vin-supply = <&vcc_sys>;
};
@ -198,7 +183,6 @@
pinctrl-names = "default";
pinctrl-0 = <&vcc_sys_en>;
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@ -392,7 +376,6 @@
vcc_sdio: LDO_REG4 {
regulator-name = "vcc_sdio";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
@ -549,6 +532,24 @@
vbus-supply = <&vcc_vbus_typec0>;
status = "okay";
};
mp8859: regulator@66 {
compatible = "mps,mp8859";
reg = <0x66>;
dc_12v: mp8859_dcdc {
regulator-name = "dc_12v";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_vbus_typec0>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
};
};
&i2s0 {

129
arch/arm/dts/rk3399-rock-pi-4.dts
View file

@ -25,6 +25,15 @@
#clock-cells = <0>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
vcc12v_dcin: dc-12v {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@ -44,6 +53,16 @@
vin-supply = <&vcc12v_dcin>;
};
vcc_0v9: vcc-0v9 {
compatible = "regulator-fixed";
regulator-name = "vcc_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vcc3v3_sys>;
};
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
@ -157,12 +176,22 @@
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
@ -444,13 +473,60 @@
pmu1830-supply = <&vcc_3v0>;
};
&pcie_phy {
status = "okay";
};
&pcie0 {
ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
max-link-speed = <2>;
num-lanes = <4>;
pinctrl-0 = <&pcie_clkreqnb_cpm>;
pinctrl-names = "default";
vpcie0v9-supply = <&vcc_0v9>;
vpcie1v8-supply = <&vcc_1v8>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_l: bt-wake-l {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio0 {
sdio0_bus4: sdio0-bus4 {
rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>,
<2 RK_PC5 1 &pcfg_pull_up_20ma>,
<2 RK_PC6 1 &pcfg_pull_up_20ma>,
<2 RK_PC7 1 &pcfg_pull_up_20ma>;
};
sdio0_cmd: sdio0-cmd {
rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up_20ma>;
};
sdio0_clk: sdio0-clk {
rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none_20ma>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
@ -476,6 +552,16 @@
rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
wifi_host_wake_l: wifi-host-wake-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm2 {
@ -488,6 +574,32 @@
vref-supply = <&vcc_1v8>;
};
&sdio0 {
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
clock-frequency = <50000000>;
cap-sdio-irq;
cap-sd-highspeed;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
@ -551,6 +663,23 @@
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
clock-names = "ext_clock";
device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
};
};
&uart2 {
status = "okay";
};

49
arch/arm/dts/rk3399-rock960.dts
View file

@ -114,6 +114,55 @@
};
};
&spi0 {
/* On Low speed expansion (LS-SPI0) */
status = "okay";
};
&spi4 {
/* On High speed expansion (HS-SPI1) */
status = "okay";
};
&thermal_zones {
cpu_thermal: cpu {
polling-delay-passive = <100>;
polling-delay = <1000>;
thermal-sensors = <&tsadc 0>;
sustainable-power = <1550>;
trips {
cpu_alert0: cpu_alert0 {
temperature = <65000>;
hysteresis = <2000>;
type = "passive";
};
cpu_alert1: cpu_alert1 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu_crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert1>;
cooling-device =
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
&usbdrd_dwc3_0 {
dr_mode = "otg";
};

13
arch/arm/dts/rk3399-rock960.dtsi
View file

@ -76,6 +76,15 @@
regulator-always-on;
vin-supply = <&vcc5v0_sys>;
};
vcc_0v9: vcc-0v9 {
compatible = "regulator-fixed";
regulator-name = "vcc_0v9";
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vcc3v3_sys>;
};
};
&cpu_l0 {
@ -384,6 +393,8 @@
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>;
vpcie0v9-supply = <&vcc_0v9>;
vpcie1v8-supply = <&vcca_1v8>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
@ -531,7 +542,7 @@
cap-mmc-highspeed;
cap-sd-highspeed;
clock-frequency = <100000000>;
clock-freq-min-max = <100000 100000000>;
max-frequency = <100000000>;
cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
disable-wp;
sd-uhs-sdr104;

749
arch/arm/dts/rk3399-rockpro64.dts
View file

@ -2,752 +2,29 @@
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
* Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
* Copyright (c) 2019 Katsuhiro Suzuki <katsuhiro@katsuster.net>
*/
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
#include "rk3399-rockpro64.dtsi"
/ {
model = "Pine64 RockPro64";
compatible = "pine64,rockpro64", "rockchip,rk3399";
chosen {
stdout-path = "serial2:1500000n8";
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
linux,code = <KEY_POWER>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
work-led {
label = "work";
default-state = "on";
gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
};
diy-led {
label = "diy";
default-state = "off";
gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
};
};
fan: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
fan-supply = <&vcc12v_dcin>;
pwms = <&pwm1 0 50000 0>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8>;
};
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_pwr_en>;
regulator-name = "vcc3v3_pcie";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc12v_dcin>;
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
regulator-always-on;
vin-supply = <&vcc5v0_usb>;
};
vcc5v0_typec: vcc5v0-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec_en>;
regulator-name = "vcc5v0_typec";
regulator-always-on;
vin-supply = <&vcc5v0_usb>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb: vcc5v0-usb {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1700000>;
vin-supply = <&vcc5v0_sys>;
};
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&emmc_phy {
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
i2c-scl-falling-time-ns = <4>;
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio3>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc5v0_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcca_1v8>;
regulators {
vdd_center: DCDC_REG1 {
regulator-name = "vdd_center";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-name = "vdd_cpu_l";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc1v8_dvp: LDO_REG1 {
regulator-name = "vcc1v8_dvp";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v0_touch: LDO_REG2 {
regulator-name = "vcc3v0_touch";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca_1v8: LDO_REG3 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_sdio: LDO_REG4 {
regulator-name = "vcc_sdio";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcca3v0_codec: LDO_REG5 {
regulator-name = "vcca3v0_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v5: LDO_REG6 {
regulator-name = "vcc_1v5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcca1v8_codec: LDO_REG7 {
regulator-name = "vcca1v8_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v0: LDO_REG8 {
regulator-name = "vcc_3v0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc3v3_s3: vcc_lan: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&vsel1_gpio>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&vsel2_gpio>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
model = "Pine64 RockPro64 v2.1";
compatible = "pine64,rockpro64-v2.1", "pine64,rockpro64", "rockchip,rk3399";
};
&i2c1 {
i2c-scl-rising-time-ns = <300>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
es8316: codec@11 {
compatible = "everest,es8316";
reg = <0x11>;
clocks = <&cru SCLK_I2S_8CH_OUT>;
clock-names = "mclk";
#sound-dai-cells = <0>;
&i2c3 {
i2c-scl-rising-time-ns = <450>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&i2c4 {
i2c-scl-rising-time-ns = <600>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
fusb0: typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&fusb0_int>;
vbus-supply = <&vcc5v0_typec>;
status = "okay";
port {
es8316_p0_0: endpoint {
remote-endpoint = <&i2s1_p0_0>;
};
};
&i2s0 {
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
status = "okay";
};
&i2s1 {
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "okay";
};
&i2s2 {
status = "okay";
};
&io_domains {
status = "okay";
bt656-supply = <&vcc1v8_dvp>;
audio-supply = <&vcc_3v0>;
sdmmc-supply = <&vcc_sdio>;
gpio1830-supply = <&vcc_3v0>;
};
&pcie0 {
ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_perst>;
vpcie12v-supply = <&vcc12v_dcin>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pmu_io_domains {
pmu1830-supply = <&vcc_3v0>;
status = "okay";
};
&pinctrl {
buttons {
pwrbtn: pwrbtn {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
fusb302x {
fusb0_int: fusb0-int {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
work_led_gpio: work_led-gpio {
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
diy_led_gpio: diy_led-gpio {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_perst: pcie-perst {
rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
vsel1_gpio: vsel1-gpio {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_gpio: vsel2-gpio {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb-typec {
vcc5v0_typec_en: vcc5v0_typec_en {
rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {
status = "okay";
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&saradc {
vref-supply = <&vcca1v8_s3>;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
status = "okay";
};
&spi1 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
};
};
&tcphy0 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
/* tshut polarity 0:LOW 1:HIGH */
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy0 {
status = "okay";
u2phy0_otg: otg-port {
status = "okay";
};
u2phy0_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&u2phy1 {
status = "okay";
u2phy1_otg: otg-port {
status = "okay";
};
u2phy1_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "otg";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

797
arch/arm/dts/rk3399-rockpro64.dtsi Normal file
View file

@ -0,0 +1,797 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
* Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
*/
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
/ {
chosen {
stdout-path = "serial2:1500000n8";
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
linux,code = <KEY_POWER>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
work-led {
label = "work";
default-state = "on";
gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
};
diy-led {
label = "diy";
default-state = "off";
gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
};
};
fan: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
fan-supply = <&vcc12v_dcin>;
pwms = <&pwm1 0 50000 0>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
sound {
compatible = "audio-graph-card";
label = "rockchip,rk3399";
dais = <&i2s1_p0>;
};
vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8>;
};
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_pwr_en>;
regulator-name = "vcc3v3_pcie";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc12v_dcin>;
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
regulator-always-on;
vin-supply = <&vcc5v0_usb>;
};
vcc5v0_typec: vcc5v0-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec_en>;
regulator-name = "vcc5v0_typec";
regulator-always-on;
vin-supply = <&vcc5v0_usb>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb: vcc5v0-usb {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1700000>;
vin-supply = <&vcc5v0_sys>;
};
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&emmc_phy {
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
i2c-scl-falling-time-ns = <4>;
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio3>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc5v0_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcca_1v8>;
regulators {
vdd_center: DCDC_REG1 {
regulator-name = "vdd_center";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-name = "vdd_cpu_l";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc1v8_dvp: LDO_REG1 {
regulator-name = "vcc1v8_dvp";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v0_touch: LDO_REG2 {
regulator-name = "vcc3v0_touch";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca_1v8: LDO_REG3 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_sdio: LDO_REG4 {
regulator-name = "vcc_sdio";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcca3v0_codec: LDO_REG5 {
regulator-name = "vcca3v0_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v5: LDO_REG6 {
regulator-name = "vcc_1v5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcca1v8_codec: LDO_REG7 {
regulator-name = "vcca1v8_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v0: LDO_REG8 {
regulator-name = "vcc_3v0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc3v3_s3: vcc_lan: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&vsel1_gpio>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&vsel2_gpio>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c1 {
i2c-scl-rising-time-ns = <300>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&i2c3 {
i2c-scl-rising-time-ns = <450>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&i2c4 {
i2c-scl-rising-time-ns = <600>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
fusb0: typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&fusb0_int>;
vbus-supply = <&vcc5v0_typec>;
status = "okay";
};
};
&i2s0 {
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
status = "okay";
};
&i2s1 {
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "okay";
i2s1_p0: port {
i2s1_p0_0: endpoint {
dai-format = "i2s";
mclk-fs = <256>;
remote-endpoint = <&es8316_p0_0>;
};
};
};
&i2s2 {
status = "okay";
};
&io_domains {
status = "okay";
bt656-supply = <&vcc1v8_dvp>;
audio-supply = <&vcc_3v0>;
sdmmc-supply = <&vcc_sdio>;
gpio1830-supply = <&vcc_3v0>;
};
&pcie0 {
ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_perst>;
vpcie12v-supply = <&vcc12v_dcin>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pmu_io_domains {
pmu1830-supply = <&vcc_3v0>;
status = "okay";
};
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
};
bt_wake_l: bt-wake-l {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
buttons {
pwrbtn: pwrbtn {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
fusb302x {
fusb0_int: fusb0-int {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
work_led_gpio: work_led-gpio {
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
diy_led_gpio: diy_led-gpio {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_perst: pcie-perst {
rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
vsel1_gpio: vsel1-gpio {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_gpio: vsel2-gpio {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb-typec {
vcc5v0_typec_en: vcc5v0_typec_en {
rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {
status = "okay";
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&saradc {
vref-supply = <&vcca1v8_s3>;
status = "okay";
};
&sdio0 {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
disable-wp;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
status = "okay";
};
&spi1 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
};
};
&tcphy0 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
/* tshut polarity 0:LOW 1:HIGH */
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy0 {
status = "okay";
u2phy0_otg: otg-port {
status = "okay";
};
u2phy0_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&u2phy1 {
status = "okay";
u2phy1_otg: otg-port {
status = "okay";
};
u2phy1_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
vbat-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8>;
};
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "otg";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

7
arch/arm/dts/rk3399-u-boot.dtsi
View file

@ -25,6 +25,12 @@
clock-names = "pclk_ddr_mon";
};
rng: rng@ff8b8000 {
compatible = "rockchip,cryptov1-rng";
reg = <0x0 0xff8b8000 0x0 0x1000>;
status = "disabled";
};
dmc: dmc {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-dmc";
@ -79,6 +85,7 @@
};
&sdhci {
max-frequency = <200000000>;
u-boot,dm-pre-reloc;
};

573
arch/arm/dts/rk3399.dtsi
View file

File diff suppressed because it is too large Load diff

1
arch/arm/include/asm/iproc-common/configs.h
View file

@ -10,7 +10,6 @@
/* Architecture, CPU, chip, etc */
#define CONFIG_IPROC
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
/* Memory Info */
#define CONFIG_SYS_SDRAM_BASE 0x61000000

8
arch/arm/include/asm/system.h
View file

@ -485,6 +485,14 @@ enum dcache_option {
};
#endif
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
#endif
/* Size of an MMU section */
enum {
#ifdef CONFIG_ARMV7_LPAE

20
arch/arm/lib/cache-cp15.c
View file

@ -61,8 +61,11 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
unsigned long startpt, stoppt;
unsigned long upto, end;
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
/* div by 2 before start + size to avoid phys_addr_t overflow */
end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2)
>> (MMU_SECTION_SHIFT - 1);
start = start >> MMU_SECTION_SHIFT;
#ifdef CONFIG_ARMV7_LPAE
debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
option);
@ -91,19 +94,16 @@ __weak void dram_bank_mmu_setup(int bank)
bd_t *bd = gd->bd;
int i;
/* bd->bi_dram is available only after relocation */
if ((gd->flags & GD_FLG_RELOC) == 0)
return;
debug("%s: bank: %d\n", __func__, bank);
for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
(bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
i++) {
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
set_section_dcache(i, DCACHE_WRITETHROUGH);
#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
set_section_dcache(i, DCACHE_WRITEALLOC);
#else
set_section_dcache(i, DCACHE_WRITEBACK);
#endif
}
i++)
set_section_dcache(i, DCACHE_DEFAULT_OPTION);
}
/* to activate the MMU we need to set up virtual memory: use 1M areas */

13
arch/arm/lib/cache.c
View file

@ -75,6 +75,15 @@ static unsigned long noncached_start;
static unsigned long noncached_end;
static unsigned long noncached_next;
void noncached_set_region(void)
{
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
mmu_set_region_dcache_behaviour(noncached_start,
noncached_end - noncached_start,
DCACHE_OFF);
#endif
}
void noncached_init(void)
{
phys_addr_t start, end;
@ -91,9 +100,7 @@ void noncached_init(void)
noncached_end = end;
noncached_next = start;
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
#endif
noncached_set_region();
}
phys_addr_t noncached_alloc(size_t size, size_t align)

2
arch/arm/lib/interrupts.c
View file

@ -34,6 +34,8 @@ int interrupt_init(void)
*/
IRQ_STACK_START_IN = gd->irq_sp + 8;
enable_interrupts();
return 0;
}

2
arch/arm/lib/interrupts_64.c
View file

@ -13,6 +13,8 @@ DECLARE_GLOBAL_DATA_PTR;
int interrupt_init(void)
{
enable_interrupts();
return 0;
}

2
arch/arm/lib/interrupts_m.c
View file

@ -31,6 +31,8 @@ struct autosave_regs {
int interrupt_init(void)
{
enable_interrupts();
return 0;
}

2
arch/powerpc/dts/Makefile
View file

@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb

17
arch/powerpc/dts/p1010rdb-pa.dts Normal file
View file

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010 RDB Device Tree Source
*
* Copyright 2020 NXP
*/
/include/ "p1010si-pre.dtsi"
/ {
model = "fsl,P1010RDB";
compatible = "fsl,P1010RDB";
/include/ "p1010rdb_32b.dtsi"
};
/include/ "p1010si-post.dtsi"

17
arch/powerpc/dts/p1010rdb-pa_36b.dts Normal file
View file

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010 RDB Device Tree Source (36-bit address map)
*
* Copyright 2020 NXP
*/
/include/ "p1010si-pre.dtsi"
/ {
model = "fsl,P1010RDB";
compatible = "fsl,P1010RDB";
/include/ "p1010rdb_36b.dtsi"
};
/include/ "p1010si-post.dtsi"

18
arch/powerpc/dts/p1010rdb-pb.dts Normal file
View file

@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010RDB Device Tree Source
*
* Copyright 2020 NXP
*/
/include/ "p1010si-pre.dtsi"
/ {
model = "fsl,P1010RDB-PB";
compatible = "fsl,P1010RDB-PB";
/include/ "p1010rdb_32b.dtsi"
};
/include/ "p1010si-post.dtsi"
/include/ "p1010rdb.dtsi"

18
arch/powerpc/dts/p1010rdb-pb_36b.dts Normal file
View file

@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010 RDB Device Tree Source (36-bit address map)
*
* Copyright 2020 NXP
*/
/include/ "p1010si-pre.dtsi"
/ {
model = "fsl,P1010RDB-PB";
compatible = "fsl,P1010RDB-PB";
/include/ "p1010rdb_36b.dtsi"
};
/include/ "p1010si-post.dtsi"
/include/ "p1010rdb.dtsi"

14
arch/powerpc/dts/p1010rdb.dtsi Normal file
View file

@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010RDB Device Tree Source
*
* Copyright 2020 NXP
*/
&soc {
i2c@3000 {
rtc@68 {
compatible = "pericom,pt7c4338";
reg = <0x68>;
};
};
};

22
arch/powerpc/dts/p1010rdb_32b.dtsi Normal file
View file

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010RDB Device Tree Source
*
* Copyright 2020 NXP
*/
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
pci1: pcie@ffe09000 {
reg = <0 0xffe09000 0 0x1000>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
};
pci0: pcie@ffe0a000 {
reg = <0 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
};

22
arch/powerpc/dts/p1010rdb_36b.dtsi Normal file
View file

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010RDB Device Tree Source (36-bit address map)
*
* Copyright 2020 NXP
*/
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
pci1: pcie@fffe09000 {
reg = <0xf 0xffe09000 0 0x1000>;
ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
};
pci0: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
};

48
arch/powerpc/dts/p1010si-post.dtsi Normal file
View file

@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2020 NXP
*/
&soc {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,p1010-immr", "simple-bus";
bus-frequency = <0>;
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic";
device_type = "open-pic";
big-endian;
single-cpu-affinity;
last-interrupt-source = <255>;
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
};
/* controller at 0x9000 */
&pci1 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
};
/* controller at 0xa000 */
&pci0 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
};

27
arch/powerpc/dts/p1010si-pre.dtsi Normal file
View file

@ -0,0 +1,27 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2020 NXP
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
compatible = "fsl,P1010";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,P1010@0 {
device_type = "cpu";
reg = <0x0>;
};
};
};

2
arch/powerpc/dts/p1020-post.dtsi
View file

@ -44,6 +44,8 @@
clock-frequency = <0>;
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
};
/* PCIe controller base address 0x9000 */

3
arch/powerpc/dts/p2020-post.dtsi
View file

@ -37,6 +37,9 @@
/* Filled in by U-Boot */
clock-frequency = <0>;
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
};
/* PCIe controller base address 0x8000 */

5
arch/powerpc/dts/p2041.dtsi
View file

@ -3,7 +3,7 @@
* P2041 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/dts-v1/;
@ -86,6 +86,9 @@
reg = <0x114000 0x1000>;
clock-frequency = <0>;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe200000 {

4
arch/powerpc/dts/p3041.dtsi
View file

@ -3,7 +3,7 @@
* P3041 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2010 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/dts-v1/;
@ -86,6 +86,8 @@
reg = <0x114000 0x1000>;
clock-frequency = <0>;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe200000 {

4
arch/powerpc/dts/p4080.dtsi
View file

@ -3,7 +3,7 @@
* P4080/P4040 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/dts-v1/;
@ -97,6 +97,8 @@
reg = <0x211000 0x1000>;
phy_type = "ulpi";
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe200000 {

5
arch/powerpc/dts/p5040.dtsi
View file

@ -3,7 +3,7 @@
* P5040 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/dts-v1/;
@ -85,6 +85,9 @@
reg = <0x114000 0x1000>;
clock-frequency = <0>;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe200000 {

15
arch/powerpc/dts/pq3-i2c-0.dtsi Normal file
View file

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 I2C Device Tree stub
*
* Copyright 2020 NXP
*/
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
u-boot,dm-pre-reloc;
reg = <0x3000 0x100>;
interrupts = <43 2 0 0>;
};

15
arch/powerpc/dts/pq3-i2c-1.dtsi Normal file
View file

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 I2C Device Tree stub
*
* Copyright 2020 NXP
*/
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
u-boot,dm-pre-reloc;
reg = <0x3100 0x100>;
interrupts = <43 2 0 0>;
};

25
arch/powerpc/dts/qoriq-i2c-0.dtsi Normal file
View file

@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* QorIQ I2C Device Tree stub
*
* Copyright 2020 NXP
*/
i2c0: i2c@118000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
u-boot,dm-pre-reloc;
reg = <0x118000 0x100>;
interrupts = <38 2 0 0>;
};
i2c1: i2c@118100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
u-boot,dm-pre-reloc;
reg = <0x118100 0x100>;
interrupts = <38 2 0 0>;
};

25
arch/powerpc/dts/qoriq-i2c-1.dtsi Normal file
View file

@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* QorIQ I2C Device Tree stub
*
* Copyright 2020 NXP
*/
i2c2: i2c@119000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <2>;
compatible = "fsl-i2c";
u-boot,dm-pre-reloc;
reg = <0x119000 0x100>;
interrupts = <39 2 0 0>;
};
i2c3: i2c@119100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <3>;
compatible = "fsl-i2c";
u-boot,dm-pre-reloc;
reg = <0x119100 0x100>;
interrupts = <39 2 0 0>;
};

4
arch/powerpc/dts/t102x.dtsi
View file

@ -3,7 +3,7 @@
* T102X Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/dts-v1/;
@ -75,6 +75,8 @@
reg = <0x114000 0x1000>;
clock-frequency = <0>;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe240000 {

4
arch/powerpc/dts/t104x.dtsi
View file

@ -3,7 +3,7 @@
* T104X Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/dts-v1/;
@ -85,6 +85,8 @@
reg = <0x114000 0x1000>;
clock-frequency = <0>;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe240000 {

4
arch/powerpc/dts/t2080.dtsi
View file

@ -3,7 +3,7 @@
* T2080/T2081 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2018 NXP
* Copyright 2018,2020 NXP
*/
/dts-v1/;
@ -96,6 +96,8 @@
sata-number = <2>;
sata-fpdma = <0>;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe240000 {

5
arch/powerpc/dts/t4240.dtsi
View file

@ -3,7 +3,7 @@
* T4240 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/dts-v1/;
@ -125,6 +125,9 @@
reg = <0x114000 0x1000>;
clock-frequency = <0>;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe240000 {

11
arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi Normal file
View file

@ -0,0 +1,11 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
/ {
aliases {
spi0 = &qspi0;
spi2 = &qspi2;
};
};

29
arch/sandbox/dts/test.dts
View file

@ -159,12 +159,23 @@
broken;
};
phy_provider2: gen_phy@2 {
compatible = "sandbox,phy";
#phy-cells = <0>;
};
gen_phy_user: gen_phy_user {
compatible = "simple-bus";
phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
phy-names = "phy1", "phy2", "phy3";
};
gen_phy_user1: gen_phy_user1 {
compatible = "simple-bus";
phys = <&phy_provider0 0>, <&phy_provider2>;
phy-names = "phy1", "phy2";
};
some-bus {
#address-cells = <1>;
#size-cells = <0>;
@ -218,6 +229,24 @@
compatible = "denx,u-boot-fdt-test1";
};
i-test {
compatible = "mediatek,u-boot-fdt-test";
#address-cells = <1>;
#size-cells = <0>;
subnode@0 {
reg = <0>;
};
subnode@1 {
reg = <1>;
};
subnode@2 {
reg = <2>;
};
};
devres-test {
compatible = "denx,u-boot-devres-test";
};

4
arch/x86/cpu/Makefile
View file

@ -54,9 +54,11 @@ obj-$(CONFIG_INTEL_QUARK) += quark/
obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
obj-$(CONFIG_INTEL_TANGIER) += tangier/
obj-$(CONFIG_APIC) += lapic.o ioapic.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o
obj-$(CONFIG_$(SPL_TPL_)ACPI_GPE) += acpi_gpe.o
obj-$(CONFIG_QFW) += qfw_cpu.o
ifndef CONFIG_SYS_COREBOOT
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o
endif
ifndef CONFIG_$(SPL_)X86_64
obj-$(CONFIG_SMP) += mp_init.o
endif

1
arch/x86/cpu/coreboot/Kconfig
View file

@ -25,5 +25,6 @@ config SYS_COREBOOT
imply FS_CBFS
imply CBMEM_CONSOLE
imply X86_TSC_READ_BASE
select BINMAN if X86_64
endif

8
arch/x86/cpu/coreboot/Makefile
View file

@ -11,8 +11,14 @@
# (C) Copyright 2002
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
ifndef CONFIG_SPL
obj-y += car.o
endif
ifdef CONFIG_SPL_BUILD
obj-y += coreboot_spl.o
else
obj-y += sdram.o
endif
obj-y += coreboot.o
obj-y += tables.o
obj-y += sdram.o
obj-y += timestamp.o

3
arch/x86/cpu/coreboot/coreboot.c
View file

@ -27,7 +27,8 @@ int arch_cpu_init(void)
timestamp_init();
return x86_cpu_init_f();
return IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() :
x86_cpu_init_f();
}
int checkcpu(void)

12
arch/x86/cpu/coreboot/coreboot_spl.c Normal file
View file

@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 Google LLC
*/
#include <common.h>
#include <init.h>
int dram_init(void)
{
return 0;
}

25
arch/x86/cpu/cpu.c
View file

@ -290,3 +290,28 @@ int reserve_arch(void)
return 0;
}
#endif
long detect_coreboot_table_at(ulong start, ulong size)
{
u32 *ptr, *end;
size /= 4;
for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
if (*ptr == 0x4f49424c) /* "LBIO" */
return (long)ptr;
}
return -ENOENT;
}
long locate_coreboot_table(void)
{
long addr;
/* We look for LBIO in the first 4K of RAM and again at 960KB */
addr = detect_coreboot_table_at(0x0, 0x1000);
if (addr < 0)
addr = detect_coreboot_table_at(0xf0000, 0x1000);
return addr;
}

36
arch/x86/cpu/i386/cpu.c
View file

@ -24,6 +24,7 @@
#include <malloc.h>
#include <spl.h>
#include <asm/control_regs.h>
#include <asm/coreboot_tables.h>
#include <asm/cpu.h>
#include <asm/mp.h>
#include <asm/msr.h>
@ -447,31 +448,6 @@ int x86_cpu_init_f(void)
return 0;
}
long detect_coreboot_table_at(ulong start, ulong size)
{
u32 *ptr, *end;
size /= 4;
for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
if (*ptr == 0x4f49424c) /* "LBIO" */
return (long)ptr;
}
return -ENOENT;
}
long locate_coreboot_table(void)
{
long addr;
/* We look for LBIO in the first 4K of RAM and again at 960KB */
addr = detect_coreboot_table_at(0x0, 0x1000);
if (addr < 0)
addr = detect_coreboot_table_at(0xf0000, 0x1000);
return addr;
}
int x86_cpu_reinit_f(void)
{
setup_identity();
@ -638,16 +614,6 @@ int cpu_jump_to_64bit_uboot(ulong target)
func = (func_t)ptr;
/*
* Copy U-Boot from ROM
* TODO(sjg@chromium.org): Figure out a way to get the text base
* correctly here, and in the device-tree binman definition.
*
* Also consider using FIT so we get the correct image length and
* parameters.
*/
memcpy((char *)target, (char *)0xfff00000, 0x100000);
/* Jump to U-Boot */
func((ulong)pgtable, 0, (ulong)target);

2
arch/x86/cpu/intel_common/Makefile
View file

@ -32,6 +32,8 @@ obj-$(CONFIG_HAVE_P2SB) += p2sb.o
ifdef CONFIG_SPL
ifndef CONFIG_SPL_BUILD
ifndef CONFIG_SYS_COREBOOT
obj-y += cpu_from_spl.o
endif
endif
endif

2
arch/x86/cpu/x86_64/cpu.c
View file

@ -53,6 +53,7 @@ int misc_init_r(void)
return 0;
}
#ifndef CONFIG_SYS_COREBOOT
int checkcpu(void)
{
return 0;
@ -62,6 +63,7 @@ int print_cpuinfo(void)
{
return 0;
}
#endif
int x86_cpu_reinit_f(void)
{

18
arch/x86/dts/coreboot-u-boot.dtsi Normal file
View file

@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 Google LLC
* Written by Simon Glass <sjg@chromium.org>
*/
#include <config.h>
/ {
binman {
filename = "u-boot-x86-with-spl.bin";
u-boot-spl {
};
u-boot {
offset = <0x10000>;
};
};
};

23
arch/x86/lib/spl.c
View file

@ -63,7 +63,7 @@ static int x86_spl_init(void)
* is not needed. We could make this a CONFIG option or perhaps
* place it immediately below CONFIG_SYS_TEXT_BASE.
*/
char *ptr = (char *)0x110000;
__maybe_unused char *ptr = (char *)0x110000;
#else
struct udevice *punit;
#endif
@ -111,7 +111,8 @@ static int x86_spl_init(void)
__func__, ret);
}
#ifndef CONFIG_TPL
#ifndef CONFIG_SYS_COREBOOT
# ifndef CONFIG_TPL
memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
/* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
@ -140,7 +141,7 @@ static int x86_spl_init(void)
return ret;
}
mtrr_commit(true);
#else
# else
ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit);
if (ret)
debug("Could not find PUNIT (err=%d)\n", ret);
@ -148,6 +149,7 @@ static int x86_spl_init(void)
ret = set_max_freq();
if (ret)
debug("Failed to set CPU frequency (err=%d)\n", ret);
# endif
#endif
return 0;
@ -162,7 +164,7 @@ void board_init_f(ulong flags)
debug("Error %d\n", ret);
panic("x86_spl_init fail");
}
#ifdef CONFIG_TPL
#if IS_ENABLED(CONFIG_TPL) || IS_ENABLED(CONFIG_SYS_COREBOOT)
gd->bd = malloc(sizeof(*gd->bd));
if (!gd->bd) {
printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd));
@ -207,6 +209,19 @@ static int spl_board_load_image(struct spl_image_info *spl_image,
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
if (!IS_ENABLED(CONFIG_SYS_COREBOOT)) {
/*
* Copy U-Boot from ROM
* TODO(sjg@chromium.org): Figure out a way to get the text base
* correctly here, and in the device-tree binman definition.
*
* Also consider using FIT so we get the correct image length
* and parameters.
*/
memcpy((char *)spl_image->load_addr, (char *)0xfff00000,
0x100000);
}
debug("Loading to %lx\n", spl_image->load_addr);
return 0;

7
board/armltd/vexpress64/Kconfig
View file

@ -9,4 +9,11 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "vexpress_aemv8a"
config JUNO_DTB_PART
string "NOR flash partition holding DTB"
default "board.dtb"
help
The ARM partition name in the NOR flash memory holding the
device tree blob to configure U-Boot.
endif

61
board/armltd/vexpress64/vexpress64.c
View file

@ -82,9 +82,64 @@ int dram_init_banksize(void)
return 0;
}
/*
* Board specific reset that is system reset.
*/
#ifdef CONFIG_OF_BOARD
#define JUNO_FLASH_SEC_SIZE (256 * 1024)
static phys_addr_t find_dtb_in_nor_flash(const char *partname)
{
phys_addr_t sector = CONFIG_SYS_FLASH_BASE;
int i;
for (i = 0;
i < CONFIG_SYS_MAX_FLASH_SECT;
i++, sector += JUNO_FLASH_SEC_SIZE) {
int len = strlen(partname) + 1;
int offs;
phys_addr_t imginfo;
u32 reg;
reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x04);
/* This makes up the string "HSLFTOOF" flash footer */
if (reg != 0x464F4F54U)
continue;
reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x08);
if (reg != 0x464C5348U)
continue;
for (offs = 0; offs < 32; offs += 4, len -= 4) {
reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x30 + offs);
if (strncmp(partname + offs, (char *)&reg,
len > 4 ? 4 : len))
break;
if (len > 4)
continue;
reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x10);
imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg;
reg = readl(imginfo + 0x54);
return CONFIG_SYS_FLASH_BASE +
reg * JUNO_FLASH_SEC_SIZE;
}
}
printf("No DTB found\n");
return ~0;
}
void *board_fdt_blob_setup(void)
{
phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART);
if (fdt_rom_addr == ~0UL)
return NULL;
return (void *)fdt_rom_addr;
}
#endif
/* Actual reset is done via PSCI. */
void reset_cpu(ulong addr)
{
}

7
board/coreboot/coreboot/MAINTAINERS
View file

@ -4,3 +4,10 @@ S: Maintained
F: board/coreboot/coreboot/
F: include/configs/chromebook_link.h
F: configs/coreboot_defconfig
COREBOOT64 BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: board/coreboot/coreboot/
F: include/configs/chromebook_link.h
F: configs/coreboot64_defconfig

Some files were not shown because too many files have changed in this diff Show more