mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 22:20:45 +00:00
Merge git://git.denx.de/u-boot-sunxi
This commit is contained in:
commit
b75643ad0a
159 changed files with 442 additions and 160 deletions
3
Kconfig
3
Kconfig
|
@ -405,6 +405,9 @@ config SYS_TEXT_BASE
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||||||
depends on !NIOS2 && !XTENSA
|
depends on !NIOS2 && !XTENSA
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||||||
depends on !EFI_APP
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depends on !EFI_APP
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||||||
default 0x80800000 if ARCH_OMAP2PLUS
|
default 0x80800000 if ARCH_OMAP2PLUS
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||||||
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default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S
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||||||
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default 0x2a000000 if ARCH_SUNXI && MACH_SUN9I
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||||||
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default 0x42e00000 if ARCH_SUNXI && MACH_SUN8I_V3S
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||||||
hex "Text Base"
|
hex "Text Base"
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||||||
help
|
help
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||||||
The address in memory that U-Boot will be running from, initially.
|
The address in memory that U-Boot will be running from, initially.
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||||||
|
|
10
Makefile
10
Makefile
|
@ -800,6 +800,11 @@ ifneq ($(BUILD_ROM)$(CONFIG_BUILD_ROM),)
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||||||
ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
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ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
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||||||
endif
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endif
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||||||
|
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||||||
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# Build a combined spl + u-boot image for sunxi
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||||||
|
ifeq ($(CONFIG_ARCH_SUNXI)$(CONFIG_SPL),yy)
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ALL-y += u-boot-sunxi-with-spl.bin
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|
endif
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||||||
|
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||||||
# enable combined SPL/u-boot/dtb rules for tegra
|
# enable combined SPL/u-boot/dtb rules for tegra
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||||||
ifeq ($(CONFIG_TEGRA)$(CONFIG_SPL),yy)
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ifeq ($(CONFIG_TEGRA)$(CONFIG_SPL),yy)
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||||||
ALL-y += u-boot-tegra.bin u-boot-nodtb-tegra.bin
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ALL-y += u-boot-tegra.bin u-boot-nodtb-tegra.bin
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||||||
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@ -1186,8 +1191,13 @@ u-boot-x86-16bit.bin: u-boot FORCE
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||||||
endif
|
endif
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||||||
|
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||||||
ifneq ($(CONFIG_ARCH_SUNXI),)
|
ifneq ($(CONFIG_ARCH_SUNXI),)
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||||||
|
ifeq ($(CONFIG_ARM64),)
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||||||
u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE
|
u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE
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||||||
$(call if_changed,binman)
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$(call if_changed,binman)
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||||||
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else
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u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE
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||||||
|
$(call if_changed,cat)
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||||||
|
endif
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||||||
endif
|
endif
|
||||||
|
|
||||||
ifneq ($(CONFIG_TEGRA),)
|
ifneq ($(CONFIG_TEGRA),)
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||||||
|
|
4
README
4
README
|
@ -1420,10 +1420,6 @@ The following options need to be configured:
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||||||
be at least 4MB.
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be at least 4MB.
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||||||
|
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||||||
- MII/PHY support:
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- MII/PHY support:
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||||||
CONFIG_PHY_ADDR
|
|
||||||
|
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||||||
The address of PHY on MII bus.
|
|
||||||
|
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||||||
CONFIG_PHY_CLOCK_FREQ (ppc4xx)
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CONFIG_PHY_CLOCK_FREQ (ppc4xx)
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||||||
|
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||||||
The clock frequency of the MII bus
|
The clock frequency of the MII bus
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||||||
|
|
|
@ -1,6 +0,0 @@
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||||||
# Build a combined spl + u-boot image
|
|
||||||
ifdef CONFIG_SPL
|
|
||||||
ifndef CONFIG_SPL_BUILD
|
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||||||
ALL-y += u-boot-sunxi-with-spl.bin
|
|
||||||
endif
|
|
||||||
endif
|
|
|
@ -305,6 +305,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \
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||||||
sun7i-a20-m5.dtb \
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sun7i-a20-m5.dtb \
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||||||
sun7i-a20-mk808c.dtb \
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sun7i-a20-mk808c.dtb \
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||||||
sun7i-a20-olimex-som-evb.dtb \
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sun7i-a20-olimex-som-evb.dtb \
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||||||
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sun7i-a20-olimex-som204-evb.dtb \
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||||||
|
sun7i-a20-olimex-som204-evb-emmc.dtb \
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||||||
sun7i-a20-olinuxino-lime.dtb \
|
sun7i-a20-olinuxino-lime.dtb \
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||||||
sun7i-a20-olinuxino-lime2.dtb \
|
sun7i-a20-olinuxino-lime2.dtb \
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||||||
sun7i-a20-olinuxino-lime2-emmc.dtb \
|
sun7i-a20-olinuxino-lime2-emmc.dtb \
|
||||||
|
|
36
arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts
Normal file
36
arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts
Normal file
|
@ -0,0 +1,36 @@
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||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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||||||
|
/*
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||||||
|
* Device Tree Source for A20-SOM204-EVB-eMMC Board
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||||||
|
*
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||||||
|
* Copyright (C) 2018 Olimex Ltd.
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||||||
|
* Author: Stefan Mavrodiev <stefan@olimex.com>
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||||||
|
*/
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||||||
|
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||||||
|
/dts-v1/;
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||||||
|
#include "sun7i-a20-olimex-som204-evb.dts"
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||||||
|
|
||||||
|
/ {
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||||||
|
model = "Olimex A20-SOM204-EVB-eMMC";
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||||||
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compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20";
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||||||
|
|
||||||
|
mmc2_pwrseq: mmc2_pwrseq {
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||||||
|
compatible = "mmc-pwrseq-emmc";
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||||||
|
reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
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||||||
|
};
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||||||
|
};
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||||||
|
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||||||
|
&mmc2 {
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||||||
|
pinctrl-names = "default";
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||||||
|
pinctrl-0 = <&mmc2_pins_a>;
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||||||
|
vmmc-supply = <®_vcc3v3>;
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||||||
|
mmc-pwrseq = <&mmc2_pwrseq>;
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||||||
|
bus-width = <4>;
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||||||
|
non-removable;
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||||||
|
status = "okay";
|
||||||
|
|
||||||
|
emmc: emmc@0 {
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||||||
|
reg = <0>;
|
||||||
|
compatible = "mmc-card";
|
||||||
|
broken-hpi;
|
||||||
|
};
|
||||||
|
};
|
296
arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
Normal file
296
arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
Normal file
|
@ -0,0 +1,296 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||||
|
/*
|
||||||
|
* Device Tree Source for A20-SOM204-EVB Board
|
||||||
|
*
|
||||||
|
* Copyright (C) 2018 Olimex Ltd.
|
||||||
|
* Author: Stefan Mavrodiev <stefan@olimex.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
#include "sun7i-a20.dtsi"
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||||||
|
#include "sunxi-common-regulators.dtsi"
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||||||
|
|
||||||
|
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
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||||||
|
#include <dt-bindings/interrupt-controller/irq.h>
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||||||
|
#include <dt-bindings/pwm/pwm.h>
|
||||||
|
|
||||||
|
/ {
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||||||
|
model = "Olimex A20-SOM204-EVB";
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||||||
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compatible = "olimex,a20-olimex-som204-evb", "allwinner,sun7i-a20";
|
||||||
|
|
||||||
|
aliases {
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||||||
|
serial0 = &uart0;
|
||||||
|
serial1 = &uart4;
|
||||||
|
serial2 = &uart7;
|
||||||
|
spi0 = &spi1;
|
||||||
|
spi1 = &spi2;
|
||||||
|
ethernet1 = &rtl8723bs;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
stdout-path = "serial0:115200n8";
|
||||||
|
};
|
||||||
|
|
||||||
|
leds {
|
||||||
|
compatible = "gpio-leds";
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||||||
|
|
||||||
|
stat {
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||||||
|
label = "a20-som204-evb:green:stat";
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||||||
|
gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>;
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||||||
|
default-state = "on";
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||||||
|
};
|
||||||
|
|
||||||
|
led1 {
|
||||||
|
label = "a20-som204-evb:green:led1";
|
||||||
|
gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
|
||||||
|
led2 {
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||||||
|
label = "a20-som204-evb:yellow:led2";
|
||||||
|
gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
rtl_pwrseq: rtl_pwrseq {
|
||||||
|
compatible = "mmc-pwrseq-simple";
|
||||||
|
reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&ahci {
|
||||||
|
target-supply = <®_ahci_5v>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&codec {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu0 {
|
||||||
|
cpu-supply = <®_dcdc2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&ehci0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&ehci1 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gmac {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&gmac_pins_rgmii_a>;
|
||||||
|
phy = <&phy3>;
|
||||||
|
phy-mode = "rgmii";
|
||||||
|
phy-supply = <®_vcc3v3>;
|
||||||
|
|
||||||
|
snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>;
|
||||||
|
snps,reset-active-low;
|
||||||
|
snps,reset-delays-us = <0 10000 1000000>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
reg = <3>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&i2c0_pins_a>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
axp209: pmic@34 {
|
||||||
|
reg = <0x34>;
|
||||||
|
interrupt-parent = <&nmi_intc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Exposed to UEXT1 */
|
||||||
|
&i2c1 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&i2c1_pins_a>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
eeprom: eeprom@50 {
|
||||||
|
compatible = "atmel,24c16";
|
||||||
|
reg = <0x50>;
|
||||||
|
pagesize = <16>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Exposed to UEXT2 */
|
||||||
|
&i2c2 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&i2c2_pins_a>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&ir0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&ir0_rx_pins_a>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&mmc0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&mmc0_pins_a>;
|
||||||
|
vmmc-supply = <®_vcc3v3>;
|
||||||
|
bus-width = <4>;
|
||||||
|
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>;
|
||||||
|
cd-inverted;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&mmc3 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&mmc3_pins_a>;
|
||||||
|
vmmc-supply = <®_vcc3v3>;
|
||||||
|
mmc-pwrseq = <&rtl_pwrseq>;
|
||||||
|
bus-width = <4>;
|
||||||
|
non-removable;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
rtl8723bs: sdio_wifi@1 {
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&ohci0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&ohci1 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&otg_sram {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&pio {
|
||||||
|
bt_uart_pins: bt_uart_pins@0 {
|
||||||
|
pins = "PG6", "PG7", "PG8";
|
||||||
|
function = "uart3";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
#include "axp209.dtsi"
|
||||||
|
|
||||||
|
®_ahci_5v {
|
||||||
|
gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
®_dcdc2 {
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-min-microvolt = <1000000>;
|
||||||
|
regulator-max-microvolt = <1400000>;
|
||||||
|
regulator-name = "vdd-cpu";
|
||||||
|
};
|
||||||
|
|
||||||
|
®_dcdc3 {
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-min-microvolt = <1000000>;
|
||||||
|
regulator-max-microvolt = <1400000>;
|
||||||
|
regulator-name = "vdd-int-dll";
|
||||||
|
};
|
||||||
|
|
||||||
|
®_ldo1 {
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-min-microvolt = <1300000>;
|
||||||
|
regulator-max-microvolt = <1300000>;
|
||||||
|
regulator-name = "vdd-rtc";
|
||||||
|
};
|
||||||
|
|
||||||
|
®_ldo2 {
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-min-microvolt = <3000000>;
|
||||||
|
regulator-max-microvolt = <3000000>;
|
||||||
|
regulator-name = "avcc";
|
||||||
|
};
|
||||||
|
|
||||||
|
®_ldo4 {
|
||||||
|
regulator-min-microvolt = <3300000>;
|
||||||
|
regulator-max-microvolt = <3300000>;
|
||||||
|
regulator-name = "vcc-pg";
|
||||||
|
};
|
||||||
|
|
||||||
|
®_usb0_vbus {
|
||||||
|
gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
®_usb1_vbus {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
®_usb2_vbus {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Exposed to UEXT1 */
|
||||||
|
&spi1 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&spi1_pins_a>,
|
||||||
|
<&spi1_cs0_pins_a>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Exposed to UEXT2 */
|
||||||
|
&spi2 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&spi2_pins_a>,
|
||||||
|
<&spi2_cs0_pins_a>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&uart0_pins_a>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Used for RTL8723BS bluetooth */
|
||||||
|
&uart3 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&bt_uart_pins>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Exposed to UEXT1 */
|
||||||
|
&uart4 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&uart4_pins_a>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Exposed to UEXT2 */
|
||||||
|
&uart7 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&uart7_pins_a>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb_otg {
|
||||||
|
dr_mode = "otg";
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb_power_supply {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usbphy {
|
||||||
|
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
|
||||||
|
usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
|
||||||
|
usb0_vbus_power-supply = <&usb_power_supply>;
|
||||||
|
usb0_vbus-supply = <®_usb0_vbus>;
|
||||||
|
usb1_vbus-supply = <®_usb1_vbus>;
|
||||||
|
usb2_vbus-supply = <®_usb2_vbus>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
|
@ -227,6 +227,7 @@
|
||||||
|
|
||||||
usb_otg: usb@01c19000 {
|
usb_otg: usb@01c19000 {
|
||||||
compatible = "allwinner,sun8i-a33-musb";
|
compatible = "allwinner,sun8i-a33-musb";
|
||||||
|
reg = <0x01c19000 0x400>;
|
||||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
interrupt-names = "mc";
|
interrupt-names = "mc";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
|
@ -311,6 +311,12 @@ M: FUKAUMI Naoki <naobsd@gmail.com>
|
||||||
S: Maintained
|
S: Maintained
|
||||||
F: configs/Nintendo_NES_Classic_Edition_defconfig
|
F: configs/Nintendo_NES_Classic_Edition_defconfig
|
||||||
|
|
||||||
|
OLIMEX A20-SOM204 BOARD
|
||||||
|
M: Stefan Mavrodiev <stefan@olimex.com>
|
||||||
|
S: Maintained
|
||||||
|
F: configs/A20-Olimex-SOM204-EVB_defconfig
|
||||||
|
F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
|
||||||
|
|
||||||
ORANGEPI WIN/WIN PLUS BOARD
|
ORANGEPI WIN/WIN PLUS BOARD
|
||||||
M: Jagan Teki <jagan@amarulasolutions.com>
|
M: Jagan Teki <jagan@amarulasolutions.com>
|
||||||
S: Maintained
|
S: Maintained
|
||||||
|
|
|
@ -95,9 +95,8 @@ Transfer the SPL and the U-Boot FIT image directly to an uSD card:
|
||||||
(replace /dev/sdx with you SD card device file name, which could be
|
(replace /dev/sdx with you SD card device file name, which could be
|
||||||
/dev/mmcblk[x] as well).
|
/dev/mmcblk[x] as well).
|
||||||
|
|
||||||
Alternatively you can concatenate the SPL and the U-Boot FIT image into a
|
Alternatively you can use the SPL and the U-Boot FIT image combined into a
|
||||||
single file and transfer that instead:
|
single file and transfer that instead:
|
||||||
$ cat spl/sunxi-spl.bin u-boot.itb > u-boot-sunxi-with-spl.bin
|
|
||||||
# dd if=u-boot-sunxi-with-spl.bin of=/dev/sdx bs=8k seek=1
|
# dd if=u-boot-sunxi-with-spl.bin of=/dev/sdx bs=8k seek=1
|
||||||
|
|
||||||
You can partition the microSD card, but leave the first MB unallocated (most
|
You can partition the microSD card, but leave the first MB unallocated (most
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN4I=y
|
CONFIG_MACH_SUN4I=y
|
||||||
CONFIG_DRAM_CLK=480
|
CONFIG_DRAM_CLK=480
|
||||||
CONFIG_DRAM_EMR1=4
|
CONFIG_DRAM_EMR1=4
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN5I=y
|
CONFIG_MACH_SUN5I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_MMC0_CD_PIN="PG1"
|
CONFIG_MMC0_CD_PIN="PG1"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN5I=y
|
CONFIG_MACH_SUN5I=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_DRAM_EMR1=0
|
CONFIG_DRAM_EMR1=0
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN5I=y
|
CONFIG_MACH_SUN5I=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_DRAM_EMR1=0
|
CONFIG_DRAM_EMR1=0
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=384
|
CONFIG_DRAM_CLK=384
|
||||||
CONFIG_MMC0_CD_PIN="PH1"
|
CONFIG_MMC0_CD_PIN="PH1"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=384
|
CONFIG_DRAM_CLK=384
|
||||||
CONFIG_MMC0_CD_PIN="PH1"
|
CONFIG_MMC0_CD_PIN="PH1"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=384
|
CONFIG_DRAM_CLK=384
|
||||||
CONFIG_MMC0_CD_PIN="PH1"
|
CONFIG_MMC0_CD_PIN="PH1"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=384
|
CONFIG_DRAM_CLK=384
|
||||||
CONFIG_MMC0_CD_PIN="PH1"
|
CONFIG_MMC0_CD_PIN="PH1"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=384
|
CONFIG_DRAM_CLK=384
|
||||||
CONFIG_MMC0_CD_PIN="PH1"
|
CONFIG_MMC0_CD_PIN="PH1"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=384
|
CONFIG_DRAM_CLK=384
|
||||||
CONFIG_MMC0_CD_PIN="PH1"
|
CONFIG_MMC0_CD_PIN="PH1"
|
||||||
|
|
34
configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
Normal file
34
configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
Normal file
|
@ -0,0 +1,34 @@
|
||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_ARCH_SUNXI=y
|
||||||
|
CONFIG_MACH_SUN7I=y
|
||||||
|
CONFIG_DRAM_CLK=384
|
||||||
|
CONFIG_MMC0_CD_PIN="PH1"
|
||||||
|
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||||
|
CONFIG_USB0_VBUS_PIN="PC17"
|
||||||
|
CONFIG_USB0_VBUS_DET="PH5"
|
||||||
|
CONFIG_I2C1_ENABLE=y
|
||||||
|
CONFIG_SATAPWR="PC3"
|
||||||
|
CONFIG_GMAC_TX_DELAY=4
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb-emmc"
|
||||||
|
CONFIG_AHCI=y
|
||||||
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
CONFIG_SPL=y
|
||||||
|
CONFIG_SPL_I2C_SUPPORT=y
|
||||||
|
# CONFIG_CMD_FLASH is not set
|
||||||
|
# CONFIG_CMD_FPGA is not set
|
||||||
|
# CONFIG_SPL_DOS_PARTITION is not set
|
||||||
|
# CONFIG_SPL_ISO_PARTITION is not set
|
||||||
|
# CONFIG_SPL_PARTITION_UUIDS is not set
|
||||||
|
CONFIG_SCSI_AHCI=y
|
||||||
|
CONFIG_ETH_DESIGNWARE=y
|
||||||
|
CONFIG_PHY_ADDR=3
|
||||||
|
CONFIG_PHY_MICREL=y
|
||||||
|
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||||
|
CONFIG_RGMII=y
|
||||||
|
CONFIG_SUN7I_GMAC=y
|
||||||
|
CONFIG_AXP_ALDO3_VOLT=2800
|
||||||
|
CONFIG_AXP_ALDO4_VOLT=2800
|
||||||
|
CONFIG_SCSI=y
|
||||||
|
CONFIG_USB_EHCI_HCD=y
|
||||||
|
CONFIG_USB_MUSB_GADGET=y
|
||||||
|
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
|
33
configs/A20-Olimex-SOM204-EVB_defconfig
Normal file
33
configs/A20-Olimex-SOM204-EVB_defconfig
Normal file
|
@ -0,0 +1,33 @@
|
||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_ARCH_SUNXI=y
|
||||||
|
CONFIG_MACH_SUN7I=y
|
||||||
|
CONFIG_DRAM_CLK=384
|
||||||
|
CONFIG_MMC0_CD_PIN="PH1"
|
||||||
|
CONFIG_USB0_VBUS_PIN="PC17"
|
||||||
|
CONFIG_USB0_VBUS_DET="PH5"
|
||||||
|
CONFIG_I2C1_ENABLE=y
|
||||||
|
CONFIG_SATAPWR="PC3"
|
||||||
|
CONFIG_GMAC_TX_DELAY=4
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb"
|
||||||
|
CONFIG_AHCI=y
|
||||||
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
CONFIG_SPL=y
|
||||||
|
CONFIG_SPL_I2C_SUPPORT=y
|
||||||
|
# CONFIG_CMD_FLASH is not set
|
||||||
|
# CONFIG_CMD_FPGA is not set
|
||||||
|
# CONFIG_SPL_DOS_PARTITION is not set
|
||||||
|
# CONFIG_SPL_ISO_PARTITION is not set
|
||||||
|
# CONFIG_SPL_PARTITION_UUIDS is not set
|
||||||
|
CONFIG_SCSI_AHCI=y
|
||||||
|
CONFIG_ETH_DESIGNWARE=y
|
||||||
|
CONFIG_PHY_ADDR=3
|
||||||
|
CONFIG_PHY_MICREL=y
|
||||||
|
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||||
|
CONFIG_RGMII=y
|
||||||
|
CONFIG_SUN7I_GMAC=y
|
||||||
|
CONFIG_AXP_ALDO3_VOLT=2800
|
||||||
|
CONFIG_AXP_ALDO4_VOLT=2800
|
||||||
|
CONFIG_SCSI=y
|
||||||
|
CONFIG_USB_EHCI_HCD=y
|
||||||
|
CONFIG_USB_MUSB_GADGET=y
|
||||||
|
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_CONS_INDEX=1
|
CONFIG_CONS_INDEX=1
|
||||||
CONFIG_MACH_SUN8I_A33=y
|
CONFIG_MACH_SUN8I_A33=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_DRAM_ZQ=123
|
CONFIG_DRAM_ZQ=123
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN5I=y
|
CONFIG_MACH_SUN5I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_MMC0_CD_PIN="PG0"
|
CONFIG_MMC0_CD_PIN="PG0"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN5I=y
|
CONFIG_MACH_SUN5I=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_DRAM_EMR1=0
|
CONFIG_DRAM_EMR1=0
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN5I=y
|
CONFIG_MACH_SUN5I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_USB1_VBUS_PIN="PG13"
|
CONFIG_USB1_VBUS_PIN="PG13"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN8I_R40=y
|
CONFIG_MACH_SUN8I_R40=y
|
||||||
CONFIG_DRAM_CLK=576
|
CONFIG_DRAM_CLK=576
|
||||||
CONFIG_DRAM_ZQ=3881979
|
CONFIG_DRAM_ZQ=3881979
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_MACPWR="PH23"
|
CONFIG_MACPWR="PH23"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_CONS_INDEX=1
|
CONFIG_CONS_INDEX=1
|
||||||
CONFIG_MACH_SUN8I_A33=y
|
CONFIG_MACH_SUN8I_A33=y
|
||||||
CONFIG_DRAM_CLK=600
|
CONFIG_DRAM_CLK=600
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_MACPWR="PH23"
|
CONFIG_MACPWR="PH23"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN5I=y
|
CONFIG_MACH_SUN5I=y
|
||||||
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
|
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
|
||||||
CONFIG_USB0_VBUS_PIN="PB10"
|
CONFIG_USB0_VBUS_PIN="PB10"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_SPL_NAND_SUPPORT=y
|
CONFIG_SPL_NAND_SUPPORT=y
|
||||||
CONFIG_MACH_SUN5I=y
|
CONFIG_MACH_SUN5I=y
|
||||||
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
|
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN6I=y
|
CONFIG_MACH_SUN6I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_USB1_VBUS_PIN=""
|
CONFIG_USB1_VBUS_PIN=""
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN4I=y
|
CONFIG_MACH_SUN4I=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_DRAM_EMR1=4
|
CONFIG_DRAM_EMR1=4
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN6I=y
|
CONFIG_MACH_SUN6I=y
|
||||||
CONFIG_DRAM_CLK=240
|
CONFIG_DRAM_CLK=240
|
||||||
CONFIG_DRAM_ZQ=251
|
CONFIG_DRAM_ZQ=251
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=480
|
CONFIG_DRAM_CLK=480
|
||||||
CONFIG_MMC0_CD_PIN="PH1"
|
CONFIG_MMC0_CD_PIN="PH1"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x2a000000
|
|
||||||
CONFIG_MACH_SUN9I=y
|
CONFIG_MACH_SUN9I=y
|
||||||
CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
|
||||||
CONFIG_MMC0_CD_PIN="PH18"
|
CONFIG_MMC0_CD_PIN="PH18"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN4I=y
|
CONFIG_MACH_SUN4I=y
|
||||||
CONFIG_DRAM_CLK=480
|
CONFIG_DRAM_CLK=480
|
||||||
CONFIG_MMC0_CD_PIN="PH1"
|
CONFIG_MMC0_CD_PIN="PH1"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_MMC0_CD_PIN="PH1"
|
CONFIG_MMC0_CD_PIN="PH1"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN8I_A83T=y
|
CONFIG_MACH_SUN8I_A83T=y
|
||||||
CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
|
||||||
CONFIG_DRAM_ZQ=15355
|
CONFIG_DRAM_ZQ=15355
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN5I=y
|
CONFIG_MACH_SUN5I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_DRAM_EMR1=0
|
CONFIG_DRAM_EMR1=0
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN5I=y
|
CONFIG_MACH_SUN5I=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_MMC0_CD_PIN="PG0"
|
CONFIG_MMC0_CD_PIN="PG0"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN6I=y
|
CONFIG_MACH_SUN6I=y
|
||||||
CONFIG_DRAM_ZQ=251
|
CONFIG_DRAM_ZQ=251
|
||||||
CONFIG_USB1_VBUS_PIN="PH24"
|
CONFIG_USB1_VBUS_PIN="PH24"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN4I=y
|
CONFIG_MACH_SUN4I=y
|
||||||
CONFIG_DRAM_EMR1=4
|
CONFIG_DRAM_EMR1=4
|
||||||
CONFIG_USB0_VBUS_PIN="PB09"
|
CONFIG_USB0_VBUS_PIN="PB09"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=480
|
CONFIG_DRAM_CLK=480
|
||||||
CONFIG_MMC0_CD_PIN="PH1"
|
CONFIG_MMC0_CD_PIN="PH1"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_MACPWR="PH23"
|
CONFIG_MACPWR="PH23"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x42e00000
|
|
||||||
CONFIG_MACH_SUN8I_V3S=y
|
CONFIG_MACH_SUN8I_V3S=y
|
||||||
CONFIG_DRAM_CLK=360
|
CONFIG_DRAM_CLK=360
|
||||||
CONFIG_DRAM_ZQ=14779
|
CONFIG_DRAM_ZQ=14779
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_DRAM_ZQ=122
|
CONFIG_DRAM_ZQ=122
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=480
|
CONFIG_DRAM_CLK=480
|
||||||
CONFIG_DRAM_ZQ=122
|
CONFIG_DRAM_ZQ=122
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN4I=y
|
CONFIG_MACH_SUN4I=y
|
||||||
CONFIG_USB1_VBUS_PIN=""
|
CONFIG_USB1_VBUS_PIN=""
|
||||||
CONFIG_USB2_VBUS_PIN=""
|
CONFIG_USB2_VBUS_PIN=""
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=384
|
CONFIG_DRAM_CLK=384
|
||||||
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
|
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=384
|
CONFIG_DRAM_CLK=384
|
||||||
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:60000,le:60,ri:160,up:13,lo:12,hs:100,vs:10,sync:3,vmode:0"
|
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:60000,le:60,ri:160,up:13,lo:12,hs:100,vs:10,sync:3,vmode:0"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN6I=y
|
CONFIG_MACH_SUN6I=y
|
||||||
CONFIG_DRAM_CLK=360
|
CONFIG_DRAM_CLK=360
|
||||||
CONFIG_DRAM_ZQ=122
|
CONFIG_DRAM_ZQ=122
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN4I=y
|
CONFIG_MACH_SUN4I=y
|
||||||
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
|
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
|
||||||
CONFIG_AHCI=y
|
CONFIG_AHCI=y
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN6I=y
|
CONFIG_MACH_SUN6I=y
|
||||||
CONFIG_DRAM_ZQ=120
|
CONFIG_DRAM_ZQ=120
|
||||||
CONFIG_INITIAL_USB_SCAN_DELAY=2000
|
CONFIG_INITIAL_USB_SCAN_DELAY=2000
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN4I=y
|
CONFIG_MACH_SUN4I=y
|
||||||
CONFIG_MACPWR="PH15"
|
CONFIG_MACPWR="PH15"
|
||||||
CONFIG_VIDEO_VGA=y
|
CONFIG_VIDEO_VGA=y
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN6I=y
|
CONFIG_MACH_SUN6I=y
|
||||||
CONFIG_DRAM_ZQ=120
|
CONFIG_DRAM_ZQ=120
|
||||||
CONFIG_USB1_VBUS_PIN="PC27"
|
CONFIG_USB1_VBUS_PIN="PC27"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=384
|
CONFIG_DRAM_CLK=384
|
||||||
CONFIG_MMC0_CD_PIN="PH1"
|
CONFIG_MMC0_CD_PIN="PH1"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_DRAM_ZQ=122
|
CONFIG_DRAM_ZQ=122
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN6I=y
|
CONFIG_MACH_SUN6I=y
|
||||||
CONFIG_DRAM_ZQ=120
|
CONFIG_DRAM_ZQ=120
|
||||||
CONFIG_USB1_VBUS_PIN="PC27"
|
CONFIG_USB1_VBUS_PIN="PC27"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x2a000000
|
|
||||||
CONFIG_MACH_SUN9I=y
|
CONFIG_MACH_SUN9I=y
|
||||||
CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
|
||||||
CONFIG_MMC0_CD_PIN="PH18"
|
CONFIG_MMC0_CD_PIN="PH18"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN4I=y
|
CONFIG_MACH_SUN4I=y
|
||||||
CONFIG_USB0_VBUS_PIN="PB9"
|
CONFIG_USB0_VBUS_PIN="PB9"
|
||||||
CONFIG_VIDEO_COMPOSITE=y
|
CONFIG_VIDEO_COMPOSITE=y
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN8I_A33=y
|
CONFIG_MACH_SUN8I_A33=y
|
||||||
CONFIG_DRAM_CLK=600
|
CONFIG_DRAM_CLK=600
|
||||||
CONFIG_DRAM_ZQ=15291
|
CONFIG_DRAM_ZQ=15291
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_MACPWR="PH23"
|
CONFIG_MACPWR="PH23"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_MACPWR="PH23"
|
CONFIG_MACPWR="PH23"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN6I=y
|
CONFIG_MACH_SUN6I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_DRAM_ZQ=251
|
CONFIG_DRAM_ZQ=251
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_CONS_INDEX=1
|
CONFIG_CONS_INDEX=1
|
||||||
CONFIG_MACH_SUN8I_A33=y
|
CONFIG_MACH_SUN8I_A33=y
|
||||||
CONFIG_DRAM_CLK=552
|
CONFIG_DRAM_CLK=552
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
|
||||||
CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
|
||||||
CONFIG_DRAM_ZQ=3881979
|
CONFIG_DRAM_ZQ=3881979
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN6I=y
|
CONFIG_MACH_SUN6I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_USB1_VBUS_PIN=""
|
CONFIG_USB1_VBUS_PIN=""
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN8I_A83T=y
|
CONFIG_MACH_SUN8I_A83T=y
|
||||||
CONFIG_DRAM_TYPE=7
|
CONFIG_DRAM_TYPE=7
|
||||||
CONFIG_DRAM_CLK=480
|
CONFIG_DRAM_CLK=480
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x2a000000
|
|
||||||
CONFIG_MACH_SUN9I=y
|
CONFIG_MACH_SUN9I=y
|
||||||
CONFIG_DRAM_CLK=600
|
CONFIG_DRAM_CLK=600
|
||||||
CONFIG_DRAM_ZQ=3881915
|
CONFIG_DRAM_ZQ=3881915
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN5I=y
|
CONFIG_MACH_SUN5I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_DRAM_EMR1=0
|
CONFIG_DRAM_EMR1=0
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=384
|
CONFIG_DRAM_CLK=384
|
||||||
CONFIG_USB0_VBUS_PIN="PB9"
|
CONFIG_USB0_VBUS_PIN="PB9"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=384
|
CONFIG_DRAM_CLK=384
|
||||||
CONFIG_VIDEO_VGA=y
|
CONFIG_VIDEO_VGA=y
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN5I=y
|
CONFIG_MACH_SUN5I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_MMC0_CD_PIN="PB3"
|
CONFIG_MMC0_CD_PIN="PB3"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_MMC0_CD_PIN="PH1"
|
CONFIG_MMC0_CD_PIN="PH1"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN6I=y
|
CONFIG_MACH_SUN6I=y
|
||||||
CONFIG_DRAM_CLK=420
|
CONFIG_DRAM_CLK=420
|
||||||
CONFIG_DRAM_ZQ=251
|
CONFIG_DRAM_ZQ=251
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN50I=y
|
CONFIG_MACH_SUN50I=y
|
||||||
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
|
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
|
||||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN4I=y
|
CONFIG_MACH_SUN4I=y
|
||||||
CONFIG_DRAM_CLK=384
|
CONFIG_DRAM_CLK=384
|
||||||
CONFIG_DRAM_EMR1=4
|
CONFIG_DRAM_EMR1=4
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_MACPWR="PH23"
|
CONFIG_MACPWR="PH23"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN50I=y
|
CONFIG_MACH_SUN50I=y
|
||||||
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
|
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
|
||||||
CONFIG_MMC0_CD_PIN="PH13"
|
CONFIG_MMC0_CD_PIN="PH13"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN6I=y
|
CONFIG_MACH_SUN6I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_DRAM_ZQ=251
|
CONFIG_DRAM_ZQ=251
|
||||||
|
|
|
@ -36,6 +36,7 @@ CONFIG_MTD_NOR_FLASH=y
|
||||||
CONFIG_NAND=y
|
CONFIG_NAND=y
|
||||||
CONFIG_SPL_NAND_SIMPLE=y
|
CONFIG_SPL_NAND_SIMPLE=y
|
||||||
CONFIG_PHYLIB=y
|
CONFIG_PHYLIB=y
|
||||||
|
CONFIG_PHY_ADDR=31
|
||||||
CONFIG_DM_SERIAL=y
|
CONFIG_DM_SERIAL=y
|
||||||
CONFIG_SYS_NS16550=y
|
CONFIG_SYS_NS16550=y
|
||||||
CONFIG_LPC32XX_SSP=y
|
CONFIG_LPC32XX_SSP=y
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN5I=y
|
CONFIG_MACH_SUN5I=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_MMC0_CD_PIN="PG0"
|
CONFIG_MMC0_CD_PIN="PG0"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN4I=y
|
CONFIG_MACH_SUN4I=y
|
||||||
CONFIG_MMC0_CD_PIN="PH1"
|
CONFIG_MMC0_CD_PIN="PH1"
|
||||||
CONFIG_USB0_VBUS_PIN="PB9"
|
CONFIG_USB0_VBUS_PIN="PB9"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN8I_A33=y
|
CONFIG_MACH_SUN8I_A33=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_DRAM_ZQ=15291
|
CONFIG_DRAM_ZQ=15291
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN8I_A23=y
|
CONFIG_MACH_SUN8I_A23=y
|
||||||
CONFIG_DRAM_CLK=480
|
CONFIG_DRAM_CLK=480
|
||||||
CONFIG_DRAM_ZQ=32767
|
CONFIG_DRAM_ZQ=32767
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN8I_A83T=y
|
CONFIG_MACH_SUN8I_A83T=y
|
||||||
CONFIG_DRAM_CLK=480
|
CONFIG_DRAM_CLK=480
|
||||||
CONFIG_DRAM_ZQ=15355
|
CONFIG_DRAM_ZQ=15355
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=384
|
CONFIG_DRAM_CLK=384
|
||||||
CONFIG_MACPWR="PH21"
|
CONFIG_MACPWR="PH21"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN4I=y
|
CONFIG_MACH_SUN4I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_DRAM_EMR1=4
|
CONFIG_DRAM_EMR1=4
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN4I=y
|
CONFIG_MACH_SUN4I=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_DRAM_ZQ=127
|
CONFIG_DRAM_ZQ=127
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN5I=y
|
CONFIG_MACH_SUN5I=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_USB0_VBUS_PIN="PG12"
|
CONFIG_USB0_VBUS_PIN="PG12"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN8I_A33=y
|
CONFIG_MACH_SUN8I_A33=y
|
||||||
CONFIG_DRAM_CLK=456
|
CONFIG_DRAM_CLK=456
|
||||||
CONFIG_DRAM_ZQ=15291
|
CONFIG_DRAM_ZQ=15291
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN7I=y
|
CONFIG_MACH_SUN7I=y
|
||||||
CONFIG_DRAM_CLK=384
|
CONFIG_DRAM_CLK=384
|
||||||
CONFIG_OLD_SUNXI_KERNEL_COMPAT=y
|
CONFIG_OLD_SUNXI_KERNEL_COMPAT=y
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN4I=y
|
CONFIG_MACH_SUN4I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_DRAM_EMR1=4
|
CONFIG_DRAM_EMR1=4
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN8I_A23=y
|
CONFIG_MACH_SUN8I_A23=y
|
||||||
CONFIG_DRAM_CLK=552
|
CONFIG_DRAM_CLK=552
|
||||||
CONFIG_DRAM_ZQ=63351
|
CONFIG_DRAM_ZQ=63351
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN4I=y
|
CONFIG_MACH_SUN4I=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_DRAM_EMR1=4
|
CONFIG_DRAM_EMR1=4
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN5I=y
|
CONFIG_MACH_SUN5I=y
|
||||||
CONFIG_DRAM_CLK=432
|
CONFIG_DRAM_CLK=432
|
||||||
CONFIG_MMC0_CD_PIN="PG0"
|
CONFIG_MMC0_CD_PIN="PG0"
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_ARCH_SUNXI=y
|
CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x4a000000
|
|
||||||
CONFIG_MACH_SUN4I=y
|
CONFIG_MACH_SUN4I=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_DRAM_EMR1=4
|
CONFIG_DRAM_EMR1=4
|
||||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue