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https://github.com/AsahiLinux/u-boot
synced 2024-09-22 07:32:03 +00:00
arm64: zynqmp: Use overlay sugar syntax for Kria SOM
dtc supports new sugar syntax which is easier compare to previous one that's why also covert overlays for SOM to it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek
parent
3dbd53144c
commit
b6d8d4b100
2 changed files with 571 additions and 644 deletions
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@ -20,16 +20,14 @@
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/dts-v1/;
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/plugin/;
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/{
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&{/} {
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compatible = "xlnx,zynqmp-sk-kv260-revA",
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"xlnx,zynqmp-sk-kv260-revY",
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"xlnx,zynqmp-sk-kv260-revZ",
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"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
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};
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fragment1 {
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target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */
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__overlay__ {
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&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default", "gpio";
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@ -45,12 +43,9 @@
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reg = <0x40>;
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};
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/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
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};
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};
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};
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fragment1a {
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target = <&amba>;
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__overlay__ {
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&amba {
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ina260-u14 {
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compatible = "iio-hwmon";
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io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
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@ -91,23 +86,17 @@
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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};
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};
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};
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/* DP/USB 3.0 and SATA */
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fragment2 {
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target = <&psgtr>;
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__overlay__ {
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&psgtr {
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status = "okay";
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/* pcie, usb3, sata */
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clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
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clock-names = "ref0", "ref1", "ref2";
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};
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};
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};
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fragment3 {
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target = <&sata>;
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__overlay__ {
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&sata {
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status = "okay";
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/* SATA OOB timing settings */
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ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
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@ -120,28 +109,19 @@
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ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
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phy-names = "sata-phy";
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phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
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};
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};
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};
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fragment4 {
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target = <&zynqmp_dpsub>;
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__overlay__ {
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&zynqmp_dpsub {
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status = "disabled";
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phy-names = "dp-phy0", "dp-phy1";
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phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
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};
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};
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};
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fragment9 {
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target = <&zynqmp_dpdma>;
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__overlay__ {
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&zynqmp_dpdma {
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status = "okay";
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};
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};
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};
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fragment10 {
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target = <&usb0>;
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__overlay__ {
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&usb0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_default>;
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@ -149,24 +129,18 @@
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compatible = "microchip,usb5744";
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reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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};
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fragment11 {
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target = <&dwc3_0>;
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__overlay__ {
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&dwc3_0 {
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status = "okay";
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dr_mode = "host";
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snps,usb3_lpm_capable;
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phy-names = "usb3-phy";
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phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
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maximum-speed = "super-speed";
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};
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};
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};
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fragment12 {
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target = <&sdhci1>; /* on CC with tuned parameters */
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__overlay__ {
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&sdhci1 { /* on CC with tuned parameters */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdhci1_default>;
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@ -178,14 +152,9 @@
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no-1-8-v;
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disable-wp;
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xlnx,mio-bank = <1>;
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};
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};
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};
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fragment13 {
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target = <&gem3>; /* required by spec */
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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&gem3 { /* required by spec */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem3_default>;
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@ -207,12 +176,9 @@
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ti,dp83867-rxctrl-strap-quirk;
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};
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};
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};
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};
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};
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fragment14 {
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target = <&pinctrl0>; /* required by spec */
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__overlay__ {
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&pinctrl0 { /* required by spec */
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status = "okay";
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pinctrl_uart1_default: uart1-default {
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@ -360,14 +326,10 @@
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function = "sdio1";
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};
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};
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};
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};
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fragment15 {
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target = <&uart1>;
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__overlay__ {
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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};
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};
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};
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@ -15,15 +15,13 @@
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/dts-v1/;
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/plugin/;
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/{
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&{/} {
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compatible = "xlnx,zynqmp-sk-kv260-rev1",
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"xlnx,zynqmp-sk-kv260-revB",
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"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
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};
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fragment1 {
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target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */
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__overlay__ {
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&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default", "gpio";
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@ -44,12 +42,9 @@
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reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
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};
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/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
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};
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};
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};
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fragment1a {
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target = <&amba>;
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__overlay__ {
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&amba {
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ina260-u14 {
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compatible = "iio-hwmon";
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io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
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@ -90,60 +85,42 @@
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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};
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};
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};
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/* DP/USB 3.0 */
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fragment2 {
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target = <&psgtr>;
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__overlay__ {
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&psgtr {
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status = "okay";
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/* pcie, usb3, sata */
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clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
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clock-names = "ref0", "ref1", "ref2";
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};
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};
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};
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fragment4 {
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target = <&zynqmp_dpsub>;
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__overlay__ {
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&zynqmp_dpsub {
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status = "disabled";
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phy-names = "dp-phy0", "dp-phy1";
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phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
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};
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};
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};
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fragment9 {
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target = <&zynqmp_dpdma>;
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__overlay__ {
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&zynqmp_dpdma {
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status = "okay";
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};
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};
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};
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fragment10 {
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target = <&usb0>;
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__overlay__ {
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&usb0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_default>;
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};
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};
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};
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fragment11 {
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target = <&dwc3_0>;
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__overlay__ {
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&dwc3_0 {
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status = "okay";
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dr_mode = "host";
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snps,usb3_lpm_capable;
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phy-names = "usb3-phy";
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phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
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maximum-speed = "super-speed";
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};
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};
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};
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fragment12 {
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target = <&sdhci1>; /* on CC with tuned parameters */
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__overlay__ {
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&sdhci1 { /* on CC with tuned parameters */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdhci1_default>;
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@ -158,14 +135,9 @@
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clk-phase-sd-hs = <126>, <60>;
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clk-phase-uhs-sdr25 = <120>, <60>;
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clk-phase-uhs-ddr50 = <126>, <48>;
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};
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};
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};
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fragment13 {
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target = <&gem3>; /* required by spec */
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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&gem3 { /* required by spec */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem3_default>;
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@ -187,12 +159,9 @@
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ti,dp83867-rxctrl-strap-quirk;
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};
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};
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};
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};
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};
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fragment14 {
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target = <&pinctrl0>; /* required by spec */
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__overlay__ {
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&pinctrl0 { /* required by spec */
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status = "okay";
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pinctrl_uart1_default: uart1-default {
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@ -340,14 +309,10 @@
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function = "sdio1";
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};
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};
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};
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};
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fragment15 {
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target = <&uart1>;
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__overlay__ {
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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};
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};
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};
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