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Merge branch 'master' of git://git.denx.de/u-boot-arm

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This commit is contained in:
Minkyu Kang 2009-11-10 08:44:30 +09:00
commit b6d8992cbb
106 changed files with 7936 additions and 754 deletions
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6162
CHANGELOG
View file

File diff suppressed because it is too large Load diff

12
MAKEALL
View file

@ -404,9 +404,21 @@ LIST_85xx=" \
P2020DS \
P2020DS_36BIT \
P1011RDB \
P1011RDB_NAND \
P1011RDB_SDCARD \
P1011RDB_SPIFLASH \
P1020RDB \
P1020RDB_NAND \
P1020RDB_SDCARD \
P1020RDB_SPIFLASH \
P2010RDB \
P2010RDB_NAND \
P2010RDB_SDCARD \
P2010RDB_SPIFLASH \
P2020RDB \
P2020RDB_NAND \
P2020RDB_SDCARD \
P2020RDB_SPIFLASH \
PM854 \
PM856 \
sbc8540 \

25
Makefile
View file

@ -22,9 +22,9 @@
#
VERSION = 2009
PATCHLEVEL = 08
PATCHLEVEL = 11
SUBLEVEL =
EXTRAVERSION =
EXTRAVERSION = -rc1
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
@ -501,6 +501,9 @@ unconfig:
$(obj)board/*/config.tmp $(obj)board/*/*/config.tmp \
$(obj)include/autoconf.mk $(obj)include/autoconf.mk.dep
%: %_config
$(MAKE)
#========================================================================
# PowerPC
#========================================================================
@ -2511,9 +2514,21 @@ P2020DS_config: unconfig
@$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale
P1011RDB_config \
P1011RDB_NAND_config \
P1011RDB_SDCARD_config \
P1011RDB_SPIFLASH_config \
P1020RDB_config \
P1020RDB_NAND_config \
P1020RDB_SDCARD_config \
P1020RDB_SPIFLASH_config \
P2010RDB_config \
P2020RDB_config: unconfig
P2010RDB_NAND_config \
P2010RDB_SDCARD_config \
P2010RDB_SPIFLASH_config \
P2020RDB_config \
P2020RDB_NAND_config \
P2020RDB_SDCARD_config \
P2020RDB_SPIFLASH_config: unconfig
@$(MKCONFIG) -t $(@:_config=) P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale
PM854_config: unconfig
@ -3542,10 +3557,6 @@ BFIN_BOARDS += ibf-dsp561
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
$(BFIN_BOARDS):
$(MAKE) $@_config
$(MAKE)
#========================================================================
# AVR32
#========================================================================

1
README
View file

@ -620,6 +620,7 @@ The following options need to be configured:
CONFIG_CMD_DS4510_RST * ds4510 I2C rst command
CONFIG_CMD_DTT * Digital Therm and Thermostat
CONFIG_CMD_ECHO echo arguments
CONFIG_CMD_EDITENV edit env variable
CONFIG_CMD_EEPROM * EEPROM read/write support
CONFIG_CMD_ELF * bootelf, bootvx
CONFIG_CMD_SAVEENV saveenv

4
board/amcc/sequoia/Makefile
View file

@ -25,9 +25,11 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o cmd_sequoia.o sdram.o
COBJS-y = $(BOARD).o sdram.o
COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
SOBJS = init.o
COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))

122
board/amcc/sequoia/chip_config.c Normal file
View file

@ -0,0 +1,122 @@
/*
* (C) Copyright 2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <asm/ppc4xx_config.h>
struct ppc4xx_config ppc4xx_config_val[] = {
{
"333-133-nor", "NOR CPU: 333 PLB: 133 OPB: 66 EBC: 66",
{
0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"333-166-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 55",
{
0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"333-166-nand", "NAND CPU: 333 PLB: 166 OPB: 83 EBC: 55",
{
0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xd0, 0x30,
0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
}
},
{
"400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
{
0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"400-160-nor", "NOR CPU: 400 PLB: 160 OPB: 80 EBC: 53",
{
0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"416-166-nor", "NOR CPU: 416 PLB: 166 OPB: 83 EBC: 55",
{
0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"416-166-nand", "NAND CPU: 416 PLB: 166 OPB: 83 EBC: 55",
{
0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xd0, 0x10,
0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
}
},
{
"500-166-nor", "NOR CPU: 500 PLB: 166 OPB: 83 EBC: 55",
{
0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"500-166-nand", "NAND CPU: 500 PLB: 166 OPB: 83 EBC: 55",
{
0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xd0, 0x30,
0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
}
},
{
"533-133-nor", "NOR CPU: 533 PLB: 133 OPB: 66 EBC: 66",
{
0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"667-133-nor", "NOR CPU: 667 PLB: 133 OPB: 66 EBC: 66",
{
0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"667-166-nor", "NOR CPU: 667 PLB: 166 OPB: 83 EBC: 55",
{
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"667-166-nand", "NAND CPU: 667 PLB: 166 OPB: 83 EBC: 55",
{
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x30,
0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
}
},
};
int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);

231
board/amcc/sequoia/cmd_sequoia.c
View file

@ -1,231 +0,0 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <asm/io.h>
/*
* There are 2 versions of production Sequoia & Rainier platforms.
* The primary difference is the reference clock. Those with
* 33333333 reference clocks will also have 667MHz rated
* processors. Not enough differences to have unique clock
* settings.
*
* NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The
* values are independent of the rest of the clock settings.
*
* All Sequoias & Rainiers select from two possible EEPROMs in Boot
* Config F. One for 33MHz PCI, one for 66MHz PCI. The following
* values are for the 33MHz PCI configuration. Byte 5 (0 base) is
* the only value affected for a 33MHz PCI and simply needs a | 0x08.
*/
#define NAND_COMPATIBLE 0x01
#define NOR_COMPATIBLE 0x02
/* check with Stefan on CONFIG_SYS_I2C_EEPROM_ADDR */
#define I2C_EEPROM_ADDR 0x52
static char *config_labels[] = {
"CPU: 333 PLB: 133 OPB: 66 EBC: 66",
"CPU: 333 PLB: 166 OPB: 83 EBC: 55",
"CPU: 400 PLB: 133 OPB: 66 EBC: 66",
"CPU: 400 PLB: 160 OPB: 80 EBC: 53",
"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
"CPU: 667 PLB: 133 OPB: 66 EBC: 66",
"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
NULL
};
static u8 boot_configs[][17] = {
{
(NOR_COMPATIBLE),
0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
}
};
/*
* Bytes 6,8,9,11 change for NAND boot
*/
static u8 nand_boot[] = {
0xd0, 0xa0, 0x68, 0x58
};
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
u8 *buf, bNAND;
int x, y, nbytes, selcfg;
extern char console_buffer[];
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if ((strcmp(argv[1], "nor") != 0) &&
(strcmp(argv[1], "nand") != 0)) {
printf("Unsupported boot-device - only nor|nand support\n");
return 1;
}
/* set the nand flag based on provided input */
if ((strcmp(argv[1], "nand") == 0))
bNAND = 1;
else
bNAND = 0;
printf("Available configurations: \n\n");
if (bNAND) {
for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
/* filter on nand compatible */
if (boot_configs[x][0] & NAND_COMPATIBLE) {
printf(" %d - %s\n", (y+1), config_labels[x]);
y++;
}
}
} else {
for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
/* filter on nor compatible */
if (boot_configs[x][0] & NOR_COMPATIBLE) {
printf(" %d - %s\n", (y+1), config_labels[x]);
y++;
}
}
}
do {
nbytes = readline(" Selection [1-x / quit]: ");
if (nbytes) {
if (strcmp(console_buffer, "quit") == 0)
return 0;
selcfg = simple_strtol(console_buffer, NULL, 10);
if ((selcfg < 1) || (selcfg > y))
nbytes = 0;
}
} while (nbytes == 0);
y = (selcfg - 1);
for (x = 0; boot_configs[x][0] != 0; x++) {
if (bNAND) {
if (boot_configs[x][0] & NAND_COMPATIBLE) {
if (y > 0)
y--;
else if (y < 1)
break;
}
} else {
if (boot_configs[x][0] & NOR_COMPATIBLE) {
if (y > 0)
y--;
else if (y < 1)
break;
}
}
}
buf = &boot_configs[x][1];
if (bNAND) {
buf[6] = nand_boot[0];
buf[8] = nand_boot[1];
buf[9] = nand_boot[2];
buf[11] = nand_boot[3];
}
/* check CPLD register +5 for PCI 66MHz flag */
if ((in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN) == 0)
/*
* PLB-to-PCI divisor = 3 for 33MHz sync PCI
* instead of 2 for 66MHz systems
*/
buf[5] |= 0x08;
if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
printf("Done\n");
printf("Please power-cycle the board for the changes to take effect\n");
return 0;
}
U_BOOT_CMD(
bootstrap, 2, 0, do_bootstrap,
"program the I2C bootstrap EEPROM",
"<nand|nor> - strap to boot from NAND or NOR flash"
);

26
board/amcc/sequoia/sequoia.c
View file

@ -40,6 +40,15 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch
extern void __ft_board_setup(void *blob, bd_t *bd);
ulong flash_get_size(ulong base, int banknum);
static inline u32 get_async_pci_freq(void)
{
if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
CONFIG_SYS_BCSR5_PCI66EN)
return 66666666;
else
return 33333333;
}
int board_early_init_f(void)
{
u32 sdr0_cust0;
@ -76,6 +85,9 @@ int board_early_init_f(void)
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
/* Check and reconfigure the PCI sync clock if necessary */
ppc4xx_pci_sync_clock_config(get_async_pci_freq());
/* 50MHz tmrclk */
out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
@ -319,7 +331,7 @@ int checkboard(void)
{
char *s = getenv("serial#");
u8 rev;
u8 val;
u32 clock = get_async_pci_freq();
#ifdef CONFIG_440EPX
printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
@ -328,8 +340,7 @@ int checkboard(void)
#endif
rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
if (s != NULL) {
puts(", serial# ");
@ -337,6 +348,15 @@ int checkboard(void)
}
putc('\n');
/*
* Reconfiguration of the PCI sync clock is already done,
* now check again if everything is in range:
*/
if (ppc4xx_pci_sync_clock_config(clock)) {
printf("ERROR: PCI clocking incorrect (async=%d "
"sync=%ld)!\n", clock, get_PCI_freq());
}
return (0);
}

26
board/amcc/yosemite/yosemite.c
View file

@ -33,6 +33,15 @@ DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
static inline u32 get_async_pci_freq(void)
{
if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
CONFIG_SYS_BCSR5_PCI66EN)
return 66666666;
else
return 33333333;
}
int board_early_init_f(void)
{
register uint reg;
@ -106,6 +115,9 @@ int board_early_init_f(void)
mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */
mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */
/* Check and reconfigure the PCI sync clock if necessary */
ppc4xx_pci_sync_clock_config(get_async_pci_freq());
/*clear tmrclk divisor */
*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;
@ -178,7 +190,7 @@ int checkboard(void)
{
char *s = getenv("serial#");
u8 rev;
u8 val;
u32 clock = get_async_pci_freq();
#ifdef CONFIG_440EP
printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
@ -187,8 +199,7 @@ int checkboard(void)
#endif
rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
if (s != NULL) {
puts(", serial# ");
@ -196,6 +207,15 @@ int checkboard(void)
}
putc('\n');
/*
* Reconfiguration of the PCI sync clock is already done,
* now check again if everything is in range:
*/
if (ppc4xx_pci_sync_clock_config(clock)) {
printf("ERROR: PCI clocking incorrect (async=%d "
"sync=%ld)!\n", clock, get_PCI_freq());
}
return (0);
}

1
board/davinci/dm6467evm/dm6467evm.c
View file

@ -28,4 +28,3 @@ int board_init(void)
return 0;
}

1
board/ep8248/ep8248.c
View file

@ -268,4 +268,3 @@ void ft_board_setup(void *blob, bd_t *bd)
ft_cpu_setup( blob, bd);
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */

27
board/esd/common/s1d13704_320_240_4bpp.h
View file

@ -1,19 +1,26 @@
/*
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
*
* Generic Header information generated by 13704CFG.EXE (Build 10)
* See file CREDITS for list of people who contributed to this
* project.
*
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
* All rights reserved.
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz)
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* This file defines the configuration environment and registers,
* which can be used by any software, such as display drivers.
*
* PLEASE NOTE: If you FTP this file to a non-Windows platform, make
* sure you transfer this file using ASCII, not BINARY
* mode.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Generic Header information generated by 13704CFG.EXE (Build 10)
* Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz)
*/
static S1D_REGS regs_13704_320_240_4bpp[] =

27
board/esd/common/s1d13705_320_240_8bpp.h
View file

@ -1,19 +1,26 @@
/*
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
*
* Generic Header information generated by 13704CFG.EXE (Build 10)
* See file CREDITS for list of people who contributed to this
* project.
*
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
* All rights reserved.
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz)
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* This file defines the configuration environment and registers,
* which can be used by any software, such as display drivers.
*
* PLEASE NOTE: If you FTP this file to a non-Windows platform, make
* sure you transfer this file using ASCII, not BINARY
* mode.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Generic Header information generated by 13704CFG.EXE (Build 10)
* Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz)
*/
static S1D_REGS regs_13705_320_240_8bpp[] =

23
board/esd/common/s1d13806_1024_768_8bpp.h
View file

@ -1,16 +1,27 @@
/*
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
*
* File generated by S1D13806CFG.EXE
* See file CREDITS for list of people who contributed to this
* project.
*
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
* All rights reserved.
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* PLEASE NOTE: If you FTP this file to a non-Windows platform, make
* sure you transfer this file using ASCII, not BINARY mode.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* File generated by S1D13806CFG.EXE
* Panel: (active) 1024x768 34Hz TFT Single 12-bit (PCLK=BUSCLK=33.333MHz)
* Memory: Embedded SDRAM (MCLK=CLKI=49.100MHz) (BUSCLK=33.333MHz)
*
*/
static S1D_REGS regs_13806_1024_768_8bpp[] =

23
board/esd/common/s1d13806_320_240_4bpp.h
View file

@ -1,16 +1,27 @@
/*
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
*
* File generated by S1D13806CFG.EXE
* See file CREDITS for list of people who contributed to this
* project.
*
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
* All rights reserved.
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* PLEASE NOTE: If you FTP this file to a non-Windows platform, make
* sure you transfer this file using ASCII, not BINARY mode.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* File generated by S1D13806CFG.EXE
* Panel: (active) 320x240 62Hz STN Single 4-bit (PCLK=CLKI2/4=6.250MHz)
* Memory: Embedded SDRAM (MCLK=CLKI=49.500MHz) (BUSCLK=33.333MHz)
*
*/
static S1D_REGS regs_13806_320_240_4bpp[] =

23
board/esd/common/s1d13806_640_480_16bpp.h
View file

@ -1,16 +1,27 @@
/*
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
*
* File generated by S1D13806CFG.EXE
* See file CREDITS for list of people who contributed to this
* project.
*
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
* All rights reserved.
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* PLEASE NOTE: If you FTP this file to a non-Windows platform, make
* sure you transfer this file using ASCII, not BINARY mode.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* File generated by S1D13806CFG.EXE
* Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
* Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
*
*/
static S1D_REGS regs_13806_640_480_16bpp[] =

23
board/esd/common/s1d13806_640_480_8bpp.h
View file

@ -1,16 +1,27 @@
/*
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
*
* File generated by S1D13806CFG.EXE
* See file CREDITS for list of people who contributed to this
* project.
*
* Copyright (c) 2000,2001 Epson Research and Development, Inc.
* All rights reserved.
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* PLEASE NOTE: If you FTP this file to a non-Windows platform, make
* sure you transfer this file using ASCII, not BINARY mode.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* File generated by S1D13806CFG.EXE
* Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
* Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
*
*/
static S1D_REGS regs_13806_640_320_16bpp[] =

10
board/espt/lowlevel_init.S
View file

@ -72,15 +72,7 @@ lowlevel_init:
/* set DDR-SDRAM dummy read */
write32 MMSEL_A, MMSEL_D
mov.l MMSEL_A, r0
synco
mov.l @r0, r1
synco
mov.l CS0_A, r0
synco
mov.l @r0, r1
synco
write32 MMSEL_A, CS0_A
/* set DDR-SDRAM bus/endian etc */
write32 MIM_U_A, MIM_U_D

8
board/freescale/mpc8569mds/bcsr.h
View file

@ -33,7 +33,8 @@
#define BCSR6_UPC1_POS_EN 0x40
#define BCSR6_UPC1_ADDR_EN 0x20
#define BCSR6_UPC1_DEV2 0x10
#define BCSR6_SD_ENABLE 0x04
#define BCSR6_SD_CARD_1BIT 0x08
#define BCSR6_SD_CARD_4BITS 0x04
#define BCSR6_TDM2G_EN 0x02
#define BCSR6_UCC7_RMII_EN 0x01
@ -67,9 +68,14 @@
#define BCSR15_SMII6_DIS 0x08
#define BCSR15_SMII8_DIS 0x04
#define BCSR15_QEUART_EN 0x01
#define BCSR16_UPC1_DEV2 0x02
#define BCSR17_nUSBEN 0x80
#define BCSR17_nUSBLOWSPD 0x40
#define BCSR17_USBVCC 0x20
#define BCSR17_USBMODE 0x10
#define BCSR17_FLASH_nWP 0x01
/*BCSR Utils functions*/

1
board/freescale/mpc8569mds/law.c
View file

@ -54,6 +54,7 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);

210
board/freescale/mpc8569mds/mpc8569mds.c
View file

@ -23,6 +23,7 @@
*/
#include <common.h>
#include <hwconfig.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
@ -35,6 +36,7 @@
#include <ioports.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
#include "bcsr.h"
@ -152,6 +154,27 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{5, 10, 2, 0, 3}, /* UART1_CTS_B */
{5, 11, 1, 0, 2}, /* UART1_RTS_B */
/* QE UART */
{0, 19, 1, 0, 2}, /* QEUART_TX */
{1, 17, 2, 0, 3}, /* QEUART_RX */
{0, 25, 1, 0, 1}, /* QEUART_RTS */
{1, 23, 2, 0, 1}, /* QEUART_CTS */
/* QE USB */
{5, 3, 1, 0, 1}, /* USB_OE */
{5, 4, 1, 0, 2}, /* USB_TP */
{5, 5, 1, 0, 2}, /* USB_TN */
{5, 6, 2, 0, 2}, /* USB_RP */
{5, 7, 2, 0, 1}, /* USB_RX */
{5, 8, 2, 0, 1}, /* USB_RN */
{2, 4, 2, 0, 2}, /* CLK5 */
/* SPI Flash, M25P40 */
{4, 27, 3, 0, 1}, /* SPI_MOSI */
{4, 28, 3, 0, 1}, /* SPI_MISO */
{4, 29, 3, 0, 1}, /* SPI_CLK */
{4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
};
@ -303,6 +326,190 @@ local_bus_init(void)
out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
}
static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
{
const char *status = "disabled";
int off;
int err;
off = fdt_path_offset(blob, alias);
if (off < 0) {
printf("WARNING: could not find %s alias: %s.\n", alias,
fdt_strerror(off));
return;
}
err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
if (err) {
printf("WARNING: could not set status for serial0: %s.\n",
fdt_strerror(err));
return;
}
}
/*
* Because of an erratum in prototype boards it is impossible to use eSDHC
* without disabling UART0 (which makes it quite easy to 'brick' the board
* by simply issung 'setenv hwconfig esdhc', and not able to interact with
* U-Boot anylonger).
*
* So, but default we assume that the board is a prototype, which is a most
* safe assumption. There is no way to determine board revision from a
* register, so we use hwconfig.
*/
static int prototype_board(void)
{
if (hwconfig_subarg("board", "rev", NULL))
return hwconfig_subarg_cmp("board", "rev", "prototype");
return 1;
}
static int esdhc_disables_uart0(void)
{
return prototype_board() ||
hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
}
static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
{
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
const char *devtype = "serial";
const char *compat = "ucc_uart";
const char *clk = "brg9";
u32 portnum = 0;
int off = -1;
if (!hwconfig("qe_uart"))
return;
if (hwconfig("esdhc") && esdhc_disables_uart0()) {
printf("QE UART: won't enable with esdhc.\n");
return;
}
fdt_board_disable_serial(blob, bd, "serial1");
while (1) {
const u32 *idx;
int len;
off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
if (off < 0) {
printf("WARNING: unable to fixup device tree for "
"QE UART\n");
return;
}
idx = fdt_getprop(blob, off, "cell-index", &len);
if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
continue;
break;
}
fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
setbits_8(&bcsr[15], BCSR15_QEUART_EN);
}
#ifdef CONFIG_FSL_ESDHC
int board_mmc_init(bd_t *bd)
{
struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
u8 bcsr6 = BCSR6_SD_CARD_1BIT;
if (!hwconfig("esdhc"))
return 0;
printf("Enabling eSDHC...\n"
" For eSDHC to function, I2C2 ");
if (esdhc_disables_uart0()) {
printf("and UART0 should be disabled.\n");
printf(" Redirecting stderr, stdout and stdin to UART1...\n");
console_assign(stderr, "eserial1");
console_assign(stdout, "eserial1");
console_assign(stdin, "eserial1");
printf("Switched to UART1 (initial log has been printed to "
"UART0).\n");
bcsr6 |= BCSR6_SD_CARD_4BITS;
} else {
printf("should be disabled.\n");
}
/* Assign I2C2 signals to eSDHC. */
clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
PLPPAR1_ESDHC_VAL);
clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
PLPDIR1_ESDHC_VAL);
/* Mux I2C2 (and optionally UART0) signals to eSDHC. */
setbits_8(&bcsr[6], bcsr6);
return fsl_esdhc_mmc_init(bd);
}
static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
{
const char *status = "disabled";
int off = -1;
if (!hwconfig("esdhc"))
return;
if (esdhc_disables_uart0())
fdt_board_disable_serial(blob, bd, "serial0");
while (1) {
const u32 *idx;
int len;
off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
if (off < 0)
break;
idx = fdt_getprop(blob, off, "cell-index", &len);
if (!idx || len != sizeof(*idx))
continue;
if (*idx == 1) {
fdt_setprop(blob, off, "status", status,
strlen(status) + 1);
break;
}
}
}
#else
static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
#endif
static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
{
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
else
setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
clrbits_8(&bcsr[17], BCSR17_USBVCC);
clrbits_8(&bcsr[17], BCSR17_USBMODE);
do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
"peripheral", sizeof("peripheral"), 1);
} else {
setbits_8(&bcsr[17], BCSR17_USBVCC);
setbits_8(&bcsr[17], BCSR17_USBMODE);
}
clrbits_8(&bcsr[17], BCSR17_nUSBEN);
}
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
@ -444,5 +651,8 @@ void ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
fdt_board_fixup_esdhc(blob, bd);
fdt_board_fixup_qe_uart(blob, bd);
fdt_board_fixup_qe_usb(blob, bd);
}
#endif

30
board/freescale/mpc8569mds/tlb.c
View file

@ -46,22 +46,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 Initializations */
/*
* TLBe 0: 16M Non-cacheable, guarded
* 0xff000000 16M FLASH (upper half)
* TLBe 0: 64M Non-cacheable, guarded
* Out of reset this entry is only 4K.
* 0xfc000000 256K NAND FLASH (CS3)
* 0xfe000000 32M NOR FLASH (CS0)
*/
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
0, 0, BOOKE_PAGESZ_64M, 1),
/*
* TLBe 1: 16M Non-cacheable, guarded
* 0xfe000000 16M FLASH (lower half)
* TLBe 1: 256KB Non-cacheable, guarded
* 0xf8000000 32K BCSR
* 0xf8008000 32K PIB (CS4)
* 0xf8010000 32K PIB (CS5)
*/
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
0, 1, BOOKE_PAGESZ_256K, 1),
/*
* TLBe 2: 256M Non-cacheable, guarded
@ -88,16 +90,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64M, 1),
/*
* TLBe 5: 256K Non-cacheable, guarded
* 0xf8000000 32K BCSR
* 0xf8008000 32K PIB (CS4)
* 0xf8010000 32K PIB (CS5)
*/
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256K, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

6
board/freescale/mpc8572ds/mpc8572ds.c
View file

@ -199,7 +199,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
&pcie3_hose, first_free_busno, pcie_ep);
/*
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
@ -231,7 +231,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
&pcie2_hose, first_free_busno, pcie_ep);
} else {
printf (" PCIE2: disabled\n");
}
@ -251,7 +251,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
&pcie1_hose, first_free_busno, pcie_ep);
} else {
printf (" PCIE1: disabled\n");
}

19
board/freescale/p1_p2_rdb/config.mk
View file

@ -24,8 +24,27 @@
# p1_p2rdb board
#
ifndef NAND_SPL
ifeq ($(CONFIG_MK_NAND), y)
TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
endif
endif
ifeq ($(CONFIG_MK_SDCARD), y)
TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
RESET_VECTOR_ADDRESS = 0xf8fffffc
endif
ifeq ($(CONFIG_MK_SPIFLASH), y)
TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
RESET_VECTOR_ADDRESS = 0xf8fffffc
endif
ifndef TEXT_BASE
TEXT_BASE = 0xeff80000
endif
ifndef RESET_VECTOR_ADDRESS
RESET_VECTOR_ADDRESS = 0xeffffffc
endif

20
board/freescale/p1_p2_rdb/ddr.c
View file

@ -85,8 +85,8 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
#define CONFIG_SYS_DDR_TIMING_0_800 0x55770802
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02000000
#define CONFIG_SYS_DDR_MODE_1_800 0x00440862
#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
#define CONFIG_SYS_DDR_MODE_1_800 0x00040852
#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
#define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100
@ -206,7 +206,7 @@ phys_size_t fixed_sdram (void)
{
sys_info_t sysinfo;
char buf[32];
fsl_ddr_cfg_regs_t *ddr_cfg_regs = NULL;
fsl_ddr_cfg_regs_t ddr_cfg_regs;
size_t ddr_size;
struct cpu_type *cpu;
@ -215,13 +215,13 @@ phys_size_t fixed_sdram (void)
strmhz(buf, sysinfo.freqDDRBus));
if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
ddr_cfg_regs = &ddr_cfg_regs_400;
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
ddr_cfg_regs = &ddr_cfg_regs_533;
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
ddr_cfg_regs = &ddr_cfg_regs_667;
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
ddr_cfg_regs = &ddr_cfg_regs_800;
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
else
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, sysinfo.freqDDRBus));
@ -230,14 +230,14 @@ phys_size_t fixed_sdram (void)
/* P1020 and it's derivatives support max 32bit DDR width */
if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
ddr_cfg_regs->ddr_sdram_cfg |= SDRAM_CFG_32_BE;
ddr_cfg_regs->cs[0].bnds = 0x0000001F;
ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
ddr_cfg_regs.cs[0].bnds = 0x0000001F;
ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
}
else
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(ddr_cfg_regs, 0);
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
return ddr_size;
}

4
board/freescale/p1_p2_rdb/pci.c
View file

@ -71,7 +71,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
&pcie2_hose, first_free_busno, pcie_ep);
} else {
printf (" PCIE2: disabled\n");
}
@ -90,7 +90,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
&pcie1_hose, first_free_busno, pcie_ep);
} else {
printf (" PCIE1: disabled\n");
}

10
board/freescale/p1_p2_rdb/tlb.c
View file

@ -78,6 +78,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
/* *I*G - L2SRAM */
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_256K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_256K, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

6
board/freescale/p2020ds/p2020ds.c
View file

@ -227,7 +227,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
&pcie2_hose, first_free_busno, pcie_ep);
/*
* The workaround doesn't work on p2020 because the location
@ -267,7 +267,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
&pcie3_hose, first_free_busno, pcie_ep);
} else {
printf(" PCIE3: disabled\n");
}
@ -286,7 +286,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
&pcie1_hose, first_free_busno, pcie_ep);
} else {
printf(" PCIE1: disabled\n");
}

1
board/logicpd/imx27lite/Makefile
View file

@ -48,4 +48,3 @@ include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

107
board/renesas/sh7785lcr/lowlevel_init.S
View file

@ -178,60 +178,6 @@ lbsc_end:
.align 4
/*------- LBSC -------*/
MMSELR_A: .long 0xfc400020
#if defined(CONFIG_SH_32BIT)
MMSELR_D: .long 0xa5a50005
#else
MMSELR_D: .long 0xa5a50002
#endif
/*------- DBSC2 -------*/
#define DBSC2_BASE 0xfe800000
DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
DBSC2_DBDICODTOCD_A: .long DBSC2_BASE + 0x54
DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
DDR_DUMMY_ACCESS_A: .long 0x40000000
DBSC2_DBCONF_D: .long 0x00630002
DBSC2_DBTR0_D: .long 0x050b1f04
DBSC2_DBTR1_D: .long 0x00040204
DBSC2_DBTR2_D: .long 0x02100308
DBSC2_DBFREQ_D1: .long 0x00000000
DBSC2_DBFREQ_D2: .long 0x00000100
DBSC2_DBDICODTOCD_D: .long 0x000f0907
DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
DBSC2_DBCMDCNT_D_REF: .long 0x00000004
DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
DBSC2_DBEN_D: .long 0x00000001
DBSC2_DBPDCNT0_D3: .long 0x00000080
DBSC2_DBRFCNT1_D: .long 0x00000926
DBSC2_DBRFCNT2_D: .long 0x00fe00fe
DBSC2_DBRFCNT0_D: .long 0x00010000
WAIT_200US: .long 33333
/*------- GPIO -------*/
PACR_D: .long 0x0000
PBCR_D: .long 0x0000
@ -291,6 +237,59 @@ PPUPR2_A: .long GPIO_BASE + 0x62
P1MSELR_A: .long GPIO_BASE + 0x80
P2MSELR_A: .long GPIO_BASE + 0x82
MMSELR_A: .long 0xfc400020
#if defined(CONFIG_SH_32BIT)
MMSELR_D: .long 0xa5a50005
#else
MMSELR_D: .long 0xa5a50002
#endif
/*------- DBSC2 -------*/
#define DBSC2_BASE 0xfe800000
DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54
DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
DDR_DUMMY_ACCESS_A: .long 0x40000000
DBSC2_DBCONF_D: .long 0x00630002
DBSC2_DBTR0_D: .long 0x050b1f04
DBSC2_DBTR1_D: .long 0x00040204
DBSC2_DBTR2_D: .long 0x02100308
DBSC2_DBFREQ_D1: .long 0x00000000
DBSC2_DBFREQ_D2: .long 0x00000100
DBSC2_DBDICODTOCD_D:.long 0x000f0907
DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
DBSC2_DBCMDCNT_D_REF: .long 0x00000004
DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
DBSC2_DBEN_D: .long 0x00000001
DBSC2_DBPDCNT0_D3: .long 0x00000080
DBSC2_DBRFCNT1_D: .long 0x00000926
DBSC2_DBRFCNT2_D: .long 0x00fe00fe
DBSC2_DBRFCNT0_D: .long 0x00010000
WAIT_200US: .long 33333
/*------- LBSC -------*/
PASCR_A: .long 0xff000070
PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */

4
board/sbc8548/sbc8548.c
View file

@ -359,7 +359,7 @@ pci_init_board(void)
SET_STD_PCI_INFO(pci_info[num], 1);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pci1_hose, first_free_busno);
&pci1_hose, first_free_busno, 0);
} else {
printf (" PCI: disabled\n");
}
@ -378,7 +378,7 @@ pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 1);
printf (" PCIE at base address %lx\n", pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
&pcie1_hose, first_free_busno, 0);
} else {
printf (" PCIE: disabled\n");
}

5
board/sbc8641d/law.c
View file

@ -44,14 +44,17 @@
struct law_entry law_table[] = {
#if !defined(CONFIG_SPD_EEPROM)
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
#endif
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
};

13
board/xes/xpedite5370/tlb.c
View file

@ -61,32 +61,37 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1M, 1),
/* **M** - Boot page for secondary processors */
SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 3, BOOKE_PAGESZ_4K, 1),
#ifdef CONFIG_PCIE1
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
0, 4, BOOKE_PAGESZ_1G, 1),
#endif
#ifdef CONFIG_PCIE2
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
0, 5, BOOKE_PAGESZ_256M, 1),
#endif
#ifdef CONFIG_PCIE3
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
0, 6, BOOKE_PAGESZ_256M, 1),
#endif
#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
0, 7, BOOKE_PAGESZ_64M, 1),
#endif
};

58
common/cmd_mem.c
View file

@ -631,7 +631,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
vu_long *addr, *start, *end;
ulong val;
ulong readback;
int rcode = 0;
ulong errs = 0;
int iterations = 1;
int iteration_limit;
@ -698,9 +698,9 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (iteration_limit && iterations > iteration_limit) {
printf("Tested %d iteration(s) without errors.\n",
iterations-1);
return 0;
printf("Tested %d iteration(s) with %lu errors.\n",
iterations-1, errs);
return errs != 0;
}
printf("Iteration: %6d\r", iterations);
@ -732,9 +732,14 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
*dummy = ~val; /* clear the test data off of the bus */
readback = *addr;
if(readback != val) {
printf ("FAILURE (data line): "
printf ("FAILURE (data line): "
"expected %08lx, actual %08lx\n",
val, readback);
errs++;
if (ctrlc()) {
putc ('\n');
return 1;
}
}
*addr = ~val;
*dummy = val;
@ -743,6 +748,11 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf ("FAILURE (data line): "
"Is %08lx, should be %08lx\n",
readback, ~val);
errs++;
if (ctrlc()) {
putc ('\n');
return 1;
}
}
}
}
@ -808,7 +818,11 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf ("\nFAILURE: Address bit stuck high @ 0x%.8lx:"
" expected 0x%.8lx, actual 0x%.8lx\n",
(ulong)&start[offset], pattern, temp);
return 1;
errs++;
if (ctrlc()) {
putc ('\n');
return 1;
}
}
}
start[test_offset] = pattern;
@ -826,7 +840,11 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf ("\nFAILURE: Address bit stuck low or shorted @"
" 0x%.8lx: expected 0x%.8lx, actual 0x%.8lx\n",
(ulong)&start[offset], pattern, temp);
return 1;
errs++;
if (ctrlc()) {
putc ('\n');
return 1;
}
}
}
start[test_offset] = pattern;
@ -864,7 +882,11 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf ("\nFAILURE (read/write) @ 0x%.8lx:"
" expected 0x%.8lx, actual 0x%.8lx)\n",
(ulong)&start[offset], pattern, temp);
return 1;
errs++;
if (ctrlc()) {
putc ('\n');
return 1;
}
}
anti_pattern = ~pattern;
@ -882,7 +904,11 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf ("\nFAILURE (read/write): @ 0x%.8lx:"
" expected 0x%.8lx, actual 0x%.8lx)\n",
(ulong)&start[offset], anti_pattern, temp);
return 1;
errs++;
if (ctrlc()) {
putc ('\n');
return 1;
}
}
start[offset] = 0;
}
@ -897,9 +923,9 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
if (iteration_limit && iterations > iteration_limit) {
printf("Tested %d iteration(s) without errors.\n",
iterations-1);
return 0;
printf("Tested %d iteration(s) with %lu errors.\n",
iterations-1, errs);
return errs != 0;
}
++iterations;
@ -923,7 +949,11 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf ("\nMem error @ 0x%08X: "
"found %08lX, expected %08lX\n",
(uint)addr, readback, val);
rcode = 1;
errs++;
if (ctrlc()) {
putc ('\n');
return 1;
}
}
val += incr;
}
@ -943,7 +973,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
incr = -incr;
}
#endif
return rcode;
return 0; /* not reached */
}

104
common/cmd_nvedit.c
View file

@ -42,6 +42,9 @@
#include <common.h>
#include <command.h>
#include <environment.h>
#if defined(CONFIG_CMD_EDITENV)
#include <malloc.h>
#endif
#include <watchdog.h>
#include <serial.h>
#include <linux/stddef.h>
@ -202,6 +205,37 @@ int _do_setenv (int flag, int argc, char *argv[])
break;
}
/* Check for console redirection */
if (strcmp(name,"stdin") == 0) {
console = stdin;
} else if (strcmp(name,"stdout") == 0) {
console = stdout;
} else if (strcmp(name,"stderr") == 0) {
console = stderr;
}
if (console != -1) {
if (argc < 3) { /* Cannot delete it! */
printf("Can't delete \"%s\"\n", name);
return 1;
}
#ifdef CONFIG_CONSOLE_MUX
i = iomux_doenv(console, argv[2]);
if (i)
return i;
#else
/* Try assigning specified device */
if (console_assign (console, argv[2]) < 0)
return 1;
#ifdef CONFIG_SERIAL_MULTI
if (serial_assign (argv[2]) < 0)
return 1;
#endif
#endif /* CONFIG_CONSOLE_MUX */
}
/*
* Delete any existing definition
*/
@ -229,37 +263,6 @@ int _do_setenv (int flag, int argc, char *argv[])
}
#endif
/* Check for console redirection */
if (strcmp(name,"stdin") == 0) {
console = stdin;
} else if (strcmp(name,"stdout") == 0) {
console = stdout;
} else if (strcmp(name,"stderr") == 0) {
console = stderr;
}
if (console != -1) {
if (argc < 3) { /* Cannot delete it! */
printf("Can't delete \"%s\"\n", name);
return 1;
}
#ifdef CONFIG_CONSOLE_MUX
i = iomux_doenv(console, argv[2]);
if (i)
return i;
#else
/* Try assigning specified device */
if (console_assign (console, argv[2]) < 0)
return 1;
#ifdef CONFIG_SERIAL_MULTI
if (serial_assign (argv[2]) < 0)
return 1;
#endif
#endif /* CONFIG_CONSOLE_MUX */
}
/*
* Switch to new baudrate if new baudrate is supported
*/
@ -400,7 +403,7 @@ int _do_setenv (int flag, int argc, char *argv[])
int setenv (char *varname, char *varvalue)
{
char *argv[4] = { "setenv", varname, varvalue, NULL };
if (varvalue == NULL)
if ((varvalue == NULL) || (varvalue[0] == '\0'))
return _do_setenv (0, 2, argv);
else
return _do_setenv (0, 3, argv);
@ -502,6 +505,34 @@ int do_askenv ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
#endif
/************************************************************************
* Interactively edit an environment variable
*/
#if defined(CONFIG_CMD_EDITENV)
int do_editenv(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char buffer[CONFIG_SYS_CBSIZE];
char *init_val;
int len;
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
/* Set read buffer to initial value or empty sting */
init_val = getenv(argv[1]);
if (init_val)
len = sprintf(buffer, "%s", init_val);
else
buffer[0] = '\0';
readline_into_buffer("edit: ", buffer);
return setenv(argv[1], buffer);
}
#endif /* CONFIG_CMD_EDITENV */
/************************************************************************
* Look up variable from environment,
* return address of storage for that variable,
@ -597,6 +628,15 @@ int envmatch (uchar *s1, int i2)
/**************************************************/
#if defined(CONFIG_CMD_EDITENV)
U_BOOT_CMD(
editenv, 2, 0, do_editenv,
"edit environment variable",
"name\n"
" - edit environment variable 'name'"
);
#endif
U_BOOT_CMD(
printenv, CONFIG_SYS_MAXARGS, 1, do_printenv,
"print environment variables",

2
common/cmd_sf.c
View file

@ -2,7 +2,9 @@
* Command for accessing SPI flash.
*
* Copyright (C) 2008 Atmel Corporation
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <spi_flash.h>

71
common/fdt_support.c
View file

@ -22,6 +22,7 @@
*/
#include <common.h>
#include <stdio_dev.h>
#include <linux/ctype.h>
#include <linux/types.h>
#include <asm/global_data.h>
@ -90,6 +91,23 @@ int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
}
#ifdef CONFIG_OF_STDOUT_VIA_ALIAS
#ifdef CONFIG_SERIAL_MULTI
static void fdt_fill_multisername(char *sername, size_t maxlen)
{
const char *outname = stdio_devices[stdout]->name;
if (strcmp(outname, "serial") > 0)
strncpy(sername, outname, maxlen);
/* eserial? */
if (strcmp(outname + 1, "serial") > 0)
strncpy(sername, outname + 1, maxlen);
}
#else
static inline void fdt_fill_multisername(char *sername, size_t maxlen) {}
#endif /* CONFIG_SERIAL_MULTI */
static int fdt_fixup_stdout(void *fdt, int chosenoff)
{
int err = 0;
@ -98,7 +116,9 @@ static int fdt_fixup_stdout(void *fdt, int chosenoff)
char sername[9] = { 0 };
const char *path;
sprintf(sername, "serial%d", CONFIG_CONS_INDEX - 1);
fdt_fill_multisername(sername, sizeof(sername) - 1);
if (!sername[0])
sprintf(sername, "serial%d", CONFIG_CONS_INDEX - 1);
err = node = fdt_path_offset(fdt, "/aliases");
if (node >= 0) {
@ -604,10 +624,11 @@ int fdt_resize(void *blob)
/*
* Calculate the actual size of the fdt
* plus the size needed for fdt_add_mem_rsv
* plus the size needed for two fdt_add_mem_rsv, one
* for the fdt itself and one for a possible initrd
*/
actualsize = fdt_off_dt_strings(blob) +
fdt_size_dt_strings(blob) + sizeof(struct fdt_reserve_entry);
fdt_size_dt_strings(blob) + 2*sizeof(struct fdt_reserve_entry);
/* Make it so the fdt ends on a page boundary */
actualsize = ALIGN(actualsize + ((uint)blob & 0xfff), 0x1000);
@ -692,3 +713,47 @@ int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose) {
return 0;
}
#endif
#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
/*
* This function can be used to update the size in the "reg" property
* of the NOR FLASH device nodes. This is necessary for boards with
* non-fixed NOR FLASH sizes.
*/
int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size)
{
char compat[][16] = { "cfi-flash", "jedec-flash" };
int off;
int len;
struct fdt_property *prop;
u32 *reg;
int i;
for (i = 0; i < 2; i++) {
off = fdt_node_offset_by_compatible(blob, -1, compat[i]);
while (off != -FDT_ERR_NOTFOUND) {
/*
* Found one compatible node, now check if this one
* has the correct CS
*/
prop = fdt_get_property_w(blob, off, "reg", &len);
if (prop) {
reg = (u32 *)&prop->data[0];
if (reg[0] == cs) {
reg[2] = size;
fdt_setprop(blob, off, "reg", reg,
3 * sizeof(u32));
return 0;
}
}
/* Move to next compatible node */
off = fdt_node_offset_by_compatible(blob, off,
compat[i]);
}
}
return -1;
}
#endif

21
common/lcd.c
View file

@ -99,32 +99,11 @@ static int lcd_getfgcolor (void);
static void console_scrollup (void)
{
#if 1
/* Copy up rows ignoring the first one */
memcpy (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE);
/* Clear the last one */
memset (CONSOLE_ROW_LAST, COLOR_MASK(lcd_color_bg), CONSOLE_ROW_SIZE);
#else
/*
* Poor attempt to optimize speed by moving "long"s.
* But the code is ugly, and not a bit faster :-(
*/
ulong *t = (ulong *)CONSOLE_ROW_FIRST;
ulong *s = (ulong *)CONSOLE_ROW_SECOND;
ulong l = CONSOLE_SCROLL_SIZE / sizeof(ulong);
uchar c = lcd_color_bg & 0xFF;
ulong val= (c<<24) | (c<<16) | (c<<8) | c;
while (l--)
*t++ = *s++;
t = (ulong *)CONSOLE_ROW_LAST;
l = CONSOLE_ROW_SIZE / sizeof(ulong);
while (l-- > 0)
*t++ = val;
#endif
}
/*----------------------------------------------------------------------*/

18
common/main.c
View file

@ -715,16 +715,17 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len)
{
unsigned long num = 0;
unsigned long eol_num = 0;
unsigned long rlen;
unsigned long wlen;
char ichar;
int insert = 1;
int esc_len = 0;
int rc = 0;
char esc_save[8];
int init_len = strlen(buf);
if (init_len)
cread_add_str(buf, init_len, 1, &num, &eol_num, buf, *len);
while (1) {
rlen = 1;
#ifdef CONFIG_BOOT_RETRY_TIME
while (!tstc()) { /* while no incoming data */
if (retry_time >= 0 && get_ticks() > endtime)
@ -923,7 +924,7 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len)
cread_add_to_hist(buf);
hist_cur = hist_add_idx;
return (rc);
return 0;
}
#endif /* CONFIG_CMDLINE_EDITING */
@ -940,6 +941,12 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len)
*/
int readline (const char *const prompt)
{
/*
* If console_buffer isn't 0-length the user will be prompted to modify
* it instead of entering it from scratch as desired.
*/
console_buffer[0] = '\0';
return readline_into_buffer(prompt, console_buffer);
}
@ -964,7 +971,8 @@ int readline_into_buffer (const char *const prompt, char * buffer)
initted = 1;
}
puts (prompt);
if (prompt)
puts (prompt);
rc = cread_line(prompt, p, &len);
return rc < 0 ? rc : len;

2
common/miiphyutil.c
View file

@ -299,7 +299,7 @@ int miiphy_reset (char *devname, unsigned char addr)
debug ("PHY status read failed\n");
return (-1);
}
if (miiphy_write (devname, addr, PHY_BMCR, reg | 0x8000) != 0) {
if (miiphy_write (devname, addr, PHY_BMCR, reg | PHY_BMCR_RESET) != 0) {
debug ("PHY reset failed\n");
return (-1);
}

1
cpu/arm926ejs/mx27/generic.c
View file

@ -328,4 +328,3 @@ void mx27_sd2_init_pins(void)
}
#endif /* CONFIG_MXC_MMC */

1
cpu/arm_cortexa8/start.S
View file

@ -414,4 +414,3 @@ fiq:
bl do_fiq
#endif

3
cpu/blackfin/interrupts.c
View file

@ -20,6 +20,7 @@
#include <common.h>
#include <config.h>
#include <watchdog.h>
#include <asm/blackfin.h>
#include "cpu.h"
@ -70,6 +71,8 @@ void udelay(unsigned long usec)
cclk = (CONFIG_CCLK_HZ);
while (usec > 1) {
WATCHDOG_RESET();
/*
* how many clock ticks to delay?
* - request(in useconds) * clock_ticks(Hz) / useconds/second

39
cpu/mpc83xx/fdt.c
View file

@ -69,6 +69,45 @@ void ft_cpu_setup(void *blob, bd_t *bd)
defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\
defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5)
fdt_fixup_ethernet(blob);
#ifdef CONFIG_MPC8313
/*
* mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1
* h/w (see AN3545). The base device tree in use has rev. 1 ID numbers,
* so if on Rev. 2 (and higher) h/w, we fix them up here
*/
if (REVID_MAJOR(immr->sysconf.spridr) >= 2) {
int nodeoffset, path;
const char *prop;
nodeoffset = fdt_path_offset(blob, "/aliases");
if (nodeoffset >= 0) {
#if defined(CONFIG_HAS_ETH0)
prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
if (prop) {
u32 tmp[] = { 32, 0x8, 33, 0x8, 34, 0x8 };
path = fdt_path_offset(blob, prop);
prop = fdt_getprop(blob, path, "interrupts", 0);
if (prop)
fdt_setprop(blob, path, "interrupts",
&tmp, sizeof(tmp));
}
#endif
#if defined(CONFIG_HAS_ETH1)
prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
if (prop) {
u32 tmp[] = { 35, 0x8, 36, 0x8, 37, 0x8 };
path = fdt_path_offset(blob, prop);
prop = fdt_getprop(blob, path, "interrupts", 0);
if (prop)
fdt_setprop(blob, path, "interrupts",
&tmp, sizeof(tmp));
}
#endif
}
}
#endif
#endif
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,

5
cpu/mpc85xx/config.mk
View file

@ -24,6 +24,11 @@
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string
# -mspe=yes is needed to have -mno-spe accepted by a buggy GCC;
# see "[PATCH,rs6000] make -mno-spe work as expected" on
# http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html
PLATFORM_CPPFLAGS +=$(call cc-option,-mspe=yes)
PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe)
# Use default linker script. Board port can override in board/*/config.mk

5
cpu/mpc85xx/cpu_init.c
View file

@ -360,8 +360,11 @@ int cpu_init_r(void)
/* enable the cache */
mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E)
if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
;
printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
}
#else
puts("disabled\n");
#endif

2
cpu/mpc85xx/fdt.c
View file

@ -43,7 +43,7 @@ extern void ft_fixup_num_cores(void *blob);
void ft_fixup_cpu(void *blob, u64 memory_limit)
{
int off;
ulong spin_tbl_addr = get_spin_addr();
ulong spin_tbl_addr = get_spin_phys_addr();
u32 bootpg = determine_mp_bootpg();
u32 id = get_my_id();

58
cpu/mpc85xx/fixed_ivor.S
View file

@ -35,22 +35,22 @@
li r3,vector_offset@l; \
mtspr SPRN_GIVOR##vector_number,r3;
SET_IVOR(0, 0x020) /* Critical Input */
SET_IVOR(1, 0x000) /* Machine Check */
SET_IVOR(2, 0x060) /* Data Storage */
SET_IVOR(3, 0x080) /* Instruction Storage */
SET_IVOR(4, 0x0a0) /* External Input */
SET_IVOR(5, 0x0c0) /* Alignment */
SET_IVOR(6, 0x0e0) /* Program */
SET_IVOR(7, 0x100) /* FP Unavailable */
SET_IVOR(8, 0x120) /* System Call */
SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
SET_IVOR(10, 0x160) /* Decrementer */
SET_IVOR(11, 0x180) /* Fixed Interval Timer */
SET_IVOR(12, 0x1a0) /* Watchdog Timer */
SET_IVOR(13, 0x1c0) /* Data TLB Error */
SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
SET_IVOR(15, 0x040) /* Debug */
SET_IVOR(0, 0x020) /* Critical Input */
SET_IVOR(1, 0x000) /* Machine Check */
SET_IVOR(2, 0x060) /* Data Storage */
SET_IVOR(3, 0x080) /* Instruction Storage */
SET_IVOR(4, 0x0a0) /* External Input */
SET_IVOR(5, 0x0c0) /* Alignment */
SET_IVOR(6, 0x0e0) /* Program */
SET_IVOR(7, 0x100) /* FP Unavailable */
SET_IVOR(8, 0x120) /* System Call */
SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
SET_IVOR(10, 0x160) /* Decrementer */
SET_IVOR(11, 0x180) /* Fixed Interval Timer */
SET_IVOR(12, 0x1a0) /* Watchdog Timer */
SET_IVOR(13, 0x1c0) /* Data TLB Error */
SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
SET_IVOR(15, 0x040) /* Debug */
/* e500v1 & e500v2 only */
#ifndef CONFIG_E500MC
@ -59,21 +59,21 @@
SET_IVOR(34, 0x240) /* Embedded FP Round */
#endif
SET_IVOR(35, 0x260) /* Performance monitor */
SET_IVOR(35, 0x260) /* Performance monitor */
/* e500mc only */
#ifdef CONFIG_E500MC
SET_IVOR(36, 0x280) /* Processor doorbell */
SET_IVOR(37, 0x2a0) /* Processor doorbell critical */
SET_IVOR(38, 0x2c0) /* Guest Processor doorbell */
SET_IVOR(39, 0x2e0) /* Guest Processor critical & machine check */
SET_IVOR(40, 0x300) /* Hypervisor system call */
SET_IVOR(41, 0x320) /* Hypervisor Priviledge */
SET_IVOR(36, 0x280) /* Processor doorbell */
SET_IVOR(37, 0x2a0) /* Processor doorbell critical */
SET_IVOR(38, 0x2c0) /* Guest Processor doorbell */
SET_IVOR(39, 0x2e0) /* Guest Processor critical & machine check */
SET_IVOR(40, 0x300) /* Hypervisor system call */
SET_IVOR(41, 0x320) /* Hypervisor Priviledge */
SET_GIVOR(2, 0x060) /* Guest Data Storage */
SET_GIVOR(3, 0x080) /* Guest Instruction Storage */
SET_GIVOR(4, 0x0a0) /* Guest External Input */
SET_GIVOR(8, 0x120) /* Guest System Call */
SET_GIVOR(13, 0x1c0) /* Guest Data TLB Error */
SET_GIVOR(14, 0x1e0) /* Guest Instruction TLB Error */
SET_GIVOR(2, 0x060) /* Guest Data Storage */
SET_GIVOR(3, 0x080) /* Guest Instruction Storage */
SET_GIVOR(4, 0x0a0) /* Guest External Input */
SET_GIVOR(8, 0x120) /* Guest System Call */
SET_GIVOR(13, 0x1c0) /* Guest Data TLB Error */
SET_GIVOR(14, 0x1e0) /* Guest Instruction TLB Error */
#endif

70
cpu/mpc85xx/mp.c
View file

@ -52,10 +52,10 @@ int cpu_status(int nr)
u32 *table, id = get_my_id();
if (nr == id) {
table = (u32 *)get_spin_addr();
table = (u32 *)get_spin_virt_addr();
printf("table base @ 0x%p\n", table);
} else {
table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
printf("Running on cpu %d\n", id);
printf("\n");
printf("table @ 0x%p\n", table);
@ -77,7 +77,7 @@ static u8 boot_entry_map[4] = {
int cpu_release(int nr, int argc, char *argv[])
{
u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
u64 boot_addr;
if (nr == get_my_id()) {
@ -124,23 +124,29 @@ u32 determine_mp_bootpg(void)
return (gd->ram_size - 4096);
}
ulong get_spin_addr(void)
ulong get_spin_phys_addr(void)
{
extern ulong __secondary_start_page;
extern ulong __spin_table;
ulong addr =
(ulong)&__spin_table - (ulong)&__secondary_start_page;
addr += 0xfffff000;
return (determine_mp_bootpg() +
(ulong)&__spin_table - (ulong)&__secondary_start_page);
}
return addr;
ulong get_spin_virt_addr(void)
{
extern ulong __secondary_start_page;
extern ulong __spin_table;
return (CONFIG_BPTR_VIRT_ADDR +
(ulong)&__spin_table - (ulong)&__secondary_start_page);
}
#ifdef CONFIG_FSL_CORENET
static void plat_mp_up(unsigned long bootpg)
{
u32 up, cpu_up_mask, whoami;
u32 *table = (u32 *)get_spin_addr();
u32 *table = (u32 *)get_spin_virt_addr();
volatile ccsr_gur_t *gur;
volatile ccsr_local_t *ccm;
volatile ccsr_rcpm_t *rcpm;
@ -194,12 +200,23 @@ static void plat_mp_up(unsigned long bootpg)
mtspr(SPRN_TBWU, 0);
mtspr(SPRN_TBWL, 0);
out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
/*
* Disabling Boot Page Translation allows the memory region 0xfffff000
* to 0xffffffff to be used normally. Leaving Boot Page Translation
* enabled remaps 0xfffff000 to SDRAM which makes that memory region
* unusable for normal operation but it does allow OSes to easily
* reset a processor core to put it back into U-Boot's spinloop.
*/
clrbits_be32(&ecm->bptr, 0x80000000);
#endif
}
#else
static void plat_mp_up(unsigned long bootpg)
{
u32 up, cpu_up_mask, whoami;
u32 *table = (u32 *)get_spin_addr();
u32 *table = (u32 *)get_spin_virt_addr();
volatile u32 bpcr;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@ -256,6 +273,17 @@ static void plat_mp_up(unsigned long bootpg)
devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
out_be32(&gur->devdisr, devdisr);
#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
/*
* Disabling Boot Page Translation allows the memory region 0xfffff000
* to 0xffffffff to be used normally. Leaving Boot Page Translation
* enabled remaps 0xfffff000 to SDRAM which makes that memory region
* unusable for normal operation but it does allow OSes to easily
* reset a processor core to put it back into U-Boot's spinloop.
*/
clrbits_be32(&ecm->bptr, 0x80000000);
#endif
}
#endif
@ -269,33 +297,27 @@ void cpu_mp_lmb_reserve(struct lmb *lmb)
void setup_mp(void)
{
extern ulong __secondary_start_page;
extern ulong __bootpg_addr;
ulong fixup = (ulong)&__secondary_start_page;
u32 bootpg = determine_mp_bootpg();
/* Store the bootpg's SDRAM address for use by secondary CPU cores */
__bootpg_addr = bootpg;
/* look for the tlb covering the reset page, there better be one */
int i = find_tlb_idx((void *)0xfffff000, 1);
int i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
/* we found a match */
if (i != -1) {
/* map reset page to bootpg so we can copy code there */
disable_tlb(i);
set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */
0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
memcpy((void *)0xfffff000, (void *)fixup, 4096);
flush_cache(0xfffff000, 4096);
disable_tlb(i);
/* setup reset page back to 1:1, we'll use HW boot translation
* to map this where we want
*/
set_tlb(1, 0xfffff000, 0xfffff000, /* tlb, epn, rpn */
set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */
0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
plat_mp_up(bootpg);
} else {
puts("WARNING: No reset page TLB. "

3
cpu/mpc85xx/mp.h
View file

@ -3,7 +3,8 @@
#include <asm/mp.h>
ulong get_spin_addr(void);
ulong get_spin_phys_addr(void);
ulong get_spin_virt_addr(void);
u32 get_my_id(void);
#define BOOT_ENTRY_ADDR_UPPER 0

34
cpu/mpc85xx/release.S
View file

@ -138,23 +138,38 @@ __secondary_start_page:
stw r3,ENTRY_R6_UPPER(r10)
stw r3,ENTRY_R6_LOWER(r10)
/* load r13 with the address of the 'bootpg' in SDRAM */
lis r13,toreset(__bootpg_addr)@h
ori r13,r13,toreset(__bootpg_addr)@l
lwz r13,0(r13)
/* setup mapping for AS = 1, and jump there */
lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
mtspr SPRN_MAS0,r11
lis r11,(MAS1_VALID|MAS1_IPROT)@h
ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
mtspr SPRN_MAS1,r11
lis r11,(0xfffff000|MAS2_I)@h
ori r11,r11,(0xfffff000|MAS2_I)@l
oris r11,r13,(MAS2_I)@h
ori r11,r13,(MAS2_I)@l
mtspr SPRN_MAS2,r11
lis r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@h
ori r11,r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@l
oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
mtspr SPRN_MAS3,r11
tlbwe
bl 1f
1: mflr r11
addi r11,r11,28
/*
* OR in 0xfff to create a mask of the bootpg SDRAM address. We use
* this mask to fixup the cpu spin table and the address that we want
* to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
* bootpg is at 0x7ffff000 in SDRAM.
*/
ori r13,r13,0xfff
and r11, r11, r13
and r10, r10, r13
addi r11,r11,(2f-1b)
mfmsr r13
ori r12,r13,MSR_IS|MSR_DS@l
@ -227,6 +242,15 @@ __secondary_start_page:
mtspr SPRN_SRR1,r13
rfi
/*
* Allocate some space for the SDRAM address of the bootpg.
* This variable has to be in the boot page so that it can
* be accessed by secondary cores when they come out of reset.
*/
.globl __bootpg_addr
__bootpg_addr:
.long 0
.align L1_CACHE_SHIFT
.globl __spin_table
__spin_table:

4
cpu/mpc85xx/speed.c
View file

@ -240,8 +240,12 @@ int get_clocks (void)
gd->i2c2_clk = gd->i2c1_clk;
#if defined(CONFIG_FSL_ESDHC)
#ifdef CONFIG_MPC8569
gd->sdhc_clk = gd->bus_clk;
#else
gd->sdhc_clk = gd->bus_clk / 2;
#endif
#endif /* defined(CONFIG_FSL_ESDHC) */
#if defined(CONFIG_CPM2)
gd->vco_out = 2*sys_info.freqSystemBus;

9
cpu/mpc8xxx/ddr/util.c
View file

@ -89,17 +89,18 @@ __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1;
if (set_ddr_laws(base, size, lawbar1_target_id) < 0) {
printf("ERROR\n");
printf("%s: ERROR (ctrl #0, intrlv=%d)\n", __func__,
memctl_interleaved);
return ;
}
} else if (ctrl_num == 1) {
if (set_ddr_laws(base, size, LAW_TRGT_IF_DDR_2) < 0) {
printf("ERROR\n");
printf("%s: ERROR (ctrl #1)\n", __func__);
return ;
}
} else {
printf("unexpected controller number %u in %s\n",
ctrl_num, __FUNCTION__);
printf("%s: unexpected DDR controller number (%u)\n", __func__,
ctrl_num);
}
}

9
cpu/ppc4xx/cpu.c
View file

@ -608,10 +608,17 @@ int checkcpu (void)
break;
}
printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu",
strmhz(buf, clock),
sys_info.freqPLB / 1000000,
get_OPB_freq() / 1000000,
sys_info.freqEBC / 1000000);
#if defined(CONFIG_PCI) && \
(defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRX))
printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000);
#endif
printf(")\n");
if (addstr[0] != 0)
printf(" %s\n", addstr);

69
cpu/ppc4xx/cpu_init.c
View file

@ -330,3 +330,72 @@ int cpu_init_r (void)
return 0;
}
#if defined(CONFIG_PCI) && \
(defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRX))
/*
* 440EP(x)/GR(x) PCI async/sync clocking restriction:
*
* In asynchronous PCI mode, the synchronous PCI clock must meet
* certain requirements. The following equation describes the
* relationship that must be maintained between the asynchronous PCI
* clock and synchronous PCI clock. Select an appropriate PCI:PLB
* ratio to maintain the relationship:
*
* AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
*/
static int ppc4xx_pci_sync_clock_ok(u32 sync, u32 async)
{
if (((async - 1000000) > sync) || (sync > ((2 * async) - 1000000)))
return 0;
else
return 1;
}
int ppc4xx_pci_sync_clock_config(u32 async)
{
sys_info_t sys_info;
u32 sync;
int div;
u32 reg;
u32 spcid_val[] = {
CPR0_SPCID_SPCIDV0_DIV1, CPR0_SPCID_SPCIDV0_DIV2,
CPR0_SPCID_SPCIDV0_DIV3, CPR0_SPCID_SPCIDV0_DIV4 };
get_sys_info(&sys_info);
sync = sys_info.freqPCI;
/*
* First check if the equation above is met
*/
if (!ppc4xx_pci_sync_clock_ok(sync, async)) {
/*
* Reconfigure PCI sync clock to meet the equation.
* Start with highest possible PCI sync frequency
* (divider 1).
*/
for (div = 1; div <= 4; div++) {
sync = sys_info.freqPLB / div;
if (ppc4xx_pci_sync_clock_ok(sync, async))
break;
}
if (div <= 4) {
mtcpr(CPR0_SPCID, spcid_val[div]);
mfcpr(CPR0_ICFG, reg);
reg |= CPR0_ICFG_RLI_MASK;
mtcpr(CPR0_ICFG, reg);
/* do chip reset */
mtspr(SPRN_DBCR0, 0x20000000);
} else {
/* Impossible to configure the PCI sync clock */
return -1;
}
}
return 0;
}
#endif

10
cpu/ppc4xx/fdt.c
View file

@ -42,7 +42,7 @@ void __ft_board_setup(void *blob, bd_t *bd)
u32 bxcr;
u32 ranges[EBC_NUM_BANKS * 4];
u32 *p = ranges;
char *ebc_path = "/plb/opb/ebc";
char ebc_path[] = "/plb/opb/ebc";
ft_cpu_setup(blob, bd);
@ -59,11 +59,17 @@ void __ft_board_setup(void *blob, bd_t *bd)
*p++ = 0;
*p++ = bxcr & EBC_BXCR_BAS_MASK;
*p++ = EBC_BXCR_BANK_SIZE(bxcr);
#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
/* Try to update reg property in nor flash node too */
fdt_fixup_nor_flash_size(blob, i,
EBC_BXCR_BANK_SIZE(bxcr));
#endif
}
}
/* Some 405 PPC's have EBC as direct PLB child in the dts */
if (fdt_path_offset(blob, "/plb/opb/ebc") < 0)
if (fdt_path_offset(blob, ebc_path) < 0)
strcpy(ebc_path, "/plb/ebc");
rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
(p - ranges) * sizeof(u32), 1);

3
disk/part_dos.c
View file

@ -188,7 +188,8 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part
* fdisk does not show the extended partitions that
* are not in the MBR
*/
if ((pt->sys_ind != 0) &&
if (((pt->boot_ind & ~0x80) == 0) &&
(pt->sys_ind != 0) &&
(part_num == which_part) &&
(is_extended(pt->sys_ind) == 0)) {
info->blksz = 512;

18
doc/README.bitbangMII
View file

@ -6,7 +6,7 @@ buses are implemented via bit-banging mode.
The driver requires that the following macros should be defined into the board
configuration file:
CONFIG_BITBANGMII - Enable the miiphybb driver
CONFIG_BITBANGMII - Enable the miiphybb driver
CONFIG_BITBANGMII_MULTI - Enable the multi bus support
If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs
@ -19,7 +19,7 @@ MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin
MDIO_READ - Read the MDIO pin
MDIO(v) - Write v on the MDIO pin
MDC_DECLARE - Declaration needed to access to the MDC pin (optional)
MDC(v) - Write v on the MDC pin
MDC(v) - Write v on the MDC pin
The previous macros make the driver compatible with the previous version
(that didn't support the multi-bus).
@ -30,17 +30,17 @@ the bb_miiphy_buses_num variable with the number of mii buses.
The record (struct bb_miiphy_bus) has the following fields/callbacks (see
miiphy.h for details):
char name[] - The symbolic name that must be equal to the MII bus
registered name
int (*init)() - Initialization function called at startup time (just
before the Ethernet initialization)
char name[] - The symbolic name that must be equal to the MII bus
registered name
int (*init)() - Initialization function called at startup time (just
before the Ethernet initialization)
int (*mdio_active)() - Activate the MDIO pin as output
int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin
int (*set_mdio)() - Write the MDIO pin
int (*get_mdio)() - Read the MDIO pin
int (*set_mdc)() - Write the MDC pin
int (*delay)() - Delay function
void *priv - Private data used by board specific code
int (*delay)() - Delay function
void *priv - Private data used by board specific code
The board code will look like:
@ -50,7 +50,7 @@ struct bb_miiphy_bus bb_miiphy_buses[] = {
...
};
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
sizeof(bb_miiphy_buses[0]);
sizeof(bb_miiphy_buses[0]);
2009 Industrie Dial Face S.p.A.
Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>

2
doc/README.drivers.eth
View file

@ -88,7 +88,7 @@ The return value for this function should be as follows:
< 0 - failure (hardware failure, not probe failure)
>=0 - number of interfaces detected
You might notice that many drivers seem to use xxx_initialize() rather than
You might notice that many drivers seem to use xxx_initialize() rather than
xxx_register(). This is the old naming convention and should be avoided as it
causes confusion with the driver-specific init function.

4
doc/README.kwbimage
View file

@ -17,12 +17,12 @@ Command syntax:
to list the kwb image file details
./tools/mkimage -n <board specific configuration file> \
-T kwbimage -a <start address> -e <execution address> \
-T kwbimage -a <start address> -e <execution address> \
-d <input_raw_binary> <output_kwboot_file>
for ex.
./tools/mkimage -n ./board/Marvell/openrd_base/kwbimage.cfg \
-T kwbimage -a 0x00600000 -e 0x00600000 \
-T kwbimage -a 0x00600000 -e 0x00600000 \
-d u-boot.bin u-boot.kwb
kwimage support available with mkimage utility will generate kirkwood boot

151
drivers/mtd/cfi_flash.c
View file

@ -39,6 +39,7 @@
#include <asm/io.h>
#include <asm/byteorder.h>
#include <environment.h>
#include <mtd/cfi_flash.h>
/*
* This file implements a Common Flash Interface (CFI) driver for
@ -65,100 +66,6 @@
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#endif
#define FLASH_CMD_CFI 0x98
#define FLASH_CMD_READ_ID 0x90
#define FLASH_CMD_RESET 0xff
#define FLASH_CMD_BLOCK_ERASE 0x20
#define FLASH_CMD_ERASE_CONFIRM 0xD0
#define FLASH_CMD_WRITE 0x40
#define FLASH_CMD_PROTECT 0x60
#define FLASH_CMD_PROTECT_SET 0x01
#define FLASH_CMD_PROTECT_CLEAR 0xD0
#define FLASH_CMD_CLEAR_STATUS 0x50
#define FLASH_CMD_READ_STATUS 0x70
#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
#define FLASH_CMD_WRITE_BUFFER_PROG 0xE9
#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
#define FLASH_STATUS_DONE 0x80
#define FLASH_STATUS_ESS 0x40
#define FLASH_STATUS_ECLBS 0x20
#define FLASH_STATUS_PSLBS 0x10
#define FLASH_STATUS_VPENS 0x08
#define FLASH_STATUS_PSS 0x04
#define FLASH_STATUS_DPS 0x02
#define FLASH_STATUS_R 0x01
#define FLASH_STATUS_PROTECT 0x01
#define AMD_CMD_RESET 0xF0
#define AMD_CMD_WRITE 0xA0
#define AMD_CMD_ERASE_START 0x80
#define AMD_CMD_ERASE_SECTOR 0x30
#define AMD_CMD_UNLOCK_START 0xAA
#define AMD_CMD_UNLOCK_ACK 0x55
#define AMD_CMD_WRITE_TO_BUFFER 0x25
#define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29
#define AMD_STATUS_TOGGLE 0x40
#define AMD_STATUS_ERROR 0x20
#define ATM_CMD_UNLOCK_SECT 0x70
#define ATM_CMD_SOFTLOCK_START 0x80
#define ATM_CMD_LOCK_SECT 0x40
#define FLASH_CONTINUATION_CODE 0x7F
#define FLASH_OFFSET_MANUFACTURER_ID 0x00
#define FLASH_OFFSET_DEVICE_ID 0x01
#define FLASH_OFFSET_DEVICE_ID2 0x0E
#define FLASH_OFFSET_DEVICE_ID3 0x0F
#define FLASH_OFFSET_CFI 0x55
#define FLASH_OFFSET_CFI_ALT 0x555
#define FLASH_OFFSET_CFI_RESP 0x10
#define FLASH_OFFSET_PRIMARY_VENDOR 0x13
/* extended query table primary address */
#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15
#define FLASH_OFFSET_WTOUT 0x1F
#define FLASH_OFFSET_WBTOUT 0x20
#define FLASH_OFFSET_ETOUT 0x21
#define FLASH_OFFSET_CETOUT 0x22
#define FLASH_OFFSET_WMAX_TOUT 0x23
#define FLASH_OFFSET_WBMAX_TOUT 0x24
#define FLASH_OFFSET_EMAX_TOUT 0x25
#define FLASH_OFFSET_CEMAX_TOUT 0x26
#define FLASH_OFFSET_SIZE 0x27
#define FLASH_OFFSET_INTERFACE 0x28
#define FLASH_OFFSET_BUFFER_SIZE 0x2A
#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
#define FLASH_OFFSET_ERASE_REGIONS 0x2D
#define FLASH_OFFSET_PROTECT 0x02
#define FLASH_OFFSET_USER_PROTECTION 0x85
#define FLASH_OFFSET_INTEL_PROTECTION 0x81
#define CFI_CMDSET_NONE 0
#define CFI_CMDSET_INTEL_EXTENDED 1
#define CFI_CMDSET_AMD_STANDARD 2
#define CFI_CMDSET_INTEL_STANDARD 3
#define CFI_CMDSET_AMD_EXTENDED 4
#define CFI_CMDSET_MITSU_STANDARD 256
#define CFI_CMDSET_MITSU_EXTENDED 257
#define CFI_CMDSET_SST 258
#define CFI_CMDSET_INTEL_PROG_REGIONS 512
#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
# undef FLASH_CMD_RESET
# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
#endif
typedef union {
unsigned char c;
unsigned short w;
unsigned long l;
unsigned long long ll;
} cfiword_t;
#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */
static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT };
static uint flash_verbose = 1;
@ -178,38 +85,6 @@ flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
#endif
/* CFI standard query structure */
struct cfi_qry {
u8 qry[3];
u16 p_id;
u16 p_adr;
u16 a_id;
u16 a_adr;
u8 vcc_min;
u8 vcc_max;
u8 vpp_min;
u8 vpp_max;
u8 word_write_timeout_typ;
u8 buf_write_timeout_typ;
u8 block_erase_timeout_typ;
u8 chip_erase_timeout_typ;
u8 word_write_timeout_max;
u8 buf_write_timeout_max;
u8 block_erase_timeout_max;
u8 chip_erase_timeout_max;
u8 dev_size;
u16 interface_desc;
u16 max_buf_write_size;
u8 num_erase_regions;
u32 erase_region_info[NUM_ERASE_REGIONS];
} __attribute__((packed));
struct cfi_pri_hdr {
u8 pri[3];
u8 major_version;
u8 minor_version;
} __attribute__((packed));
static void __flash_write8(u8 value, void *addr)
{
__raw_writeb(value, addr);
@ -452,8 +327,8 @@ static ulong flash_read_long (flash_info_t * info, flash_sect_t sect,
/*
* Write a proper sized command to the correct address
*/
static void flash_write_cmd (flash_info_t * info, flash_sect_t sect,
uint offset, u32 cmd)
void flash_write_cmd (flash_info_t * info, flash_sect_t sect,
uint offset, u32 cmd)
{
void *addr;
@ -1699,15 +1574,25 @@ static void flash_read_cfi (flash_info_t *info, void *buf,
p[i] = flash_read_uchar(info, start + i);
}
void __flash_cmd_reset(flash_info_t *info)
{
/*
* We do not yet know what kind of commandset to use, so we issue
* the reset command in both Intel and AMD variants, in the hope
* that AMD flash roms ignore the Intel command.
*/
flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
}
void flash_cmd_reset(flash_info_t *info)
__attribute__((weak,alias("__flash_cmd_reset")));
static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
{
int cfi_offset;
/* We do not yet know what kind of commandset to use, so we issue
the reset command in both Intel and AMD variants, in the hope
that AMD flash roms ignore the Intel command. */
flash_write_cmd (info, 0, 0, AMD_CMD_RESET);
flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
/* Issue FLASH reset command */
flash_cmd_reset(info);
for (cfi_offset=0;
cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint);

1
drivers/mtd/spi/atmel.c
View file

@ -2,6 +2,7 @@
* Atmel SPI DataFlash support
*
* Copyright (C) 2008 Atmel Corporation
* Licensed under the GPL-2 or later.
*/
#include <common.h>

1
drivers/mtd/spi/spi_flash.c
View file

@ -2,6 +2,7 @@
* SPI flash interface
*
* Copyright (C) 2008 Atmel Corporation
* Licensed under the GPL-2 or later.
*/
#include <common.h>

10
drivers/net/phy/miiphybb.c
View file

@ -119,7 +119,7 @@ struct bb_miiphy_bus bb_miiphy_buses[] = {
};
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
sizeof(bb_miiphy_buses[0]);
sizeof(bb_miiphy_buses[0]);
#endif
void bb_miiphy_init(void)
@ -167,7 +167,7 @@ static inline struct bb_miiphy_bus *bb_miiphy_getbus(char *devname)
* and write).
*/
static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
unsigned char addr, unsigned char reg)
unsigned char addr, unsigned char reg)
{
int j;
@ -247,7 +247,7 @@ static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
* 0 on success
*/
int bb_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
unsigned char reg, unsigned short *value)
{
short rdreg; /* register working value */
int v;
@ -328,7 +328,7 @@ int bb_miiphy_read(char *devname, unsigned char addr,
* 0 on success
*/
int bb_miiphy_write (char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
unsigned char reg, unsigned short value)
{
struct bb_miiphy_bus *bus;
int j; /* counter */
@ -377,4 +377,4 @@ int bb_miiphy_write (char *devname, unsigned char addr,
bus->delay(bus);
return 0;
}
}

2
drivers/net/smc911x.c
View file

@ -148,7 +148,7 @@ static int smc911x_init(struct eth_device *dev, bd_t * bd)
{
struct chip_id *id = dev->priv;
printf(DRIVERNAME ": detected %s controller\n", id->name);
printf(DRIVERNAME ": detected %s controller\n", id->name);
smc911x_reset(dev);

2
drivers/net/smc911x.h
View file

@ -393,6 +393,7 @@ static inline void smc911x_reg_write(struct eth_device *dev,
#define CHIP_9216 0x116a
#define CHIP_9217 0x117a
#define CHIP_9218 0x118a
#define CHIP_9220 0x9220
#define CHIP_9221 0x9221
struct chip_id {
@ -410,6 +411,7 @@ static const struct chip_id chip_ids[] = {
{ CHIP_9216, "LAN9216" },
{ CHIP_9217, "LAN9217" },
{ CHIP_9218, "LAN9218" },
{ CHIP_9220, "LAN9220" },
{ CHIP_9221, "LAN9221" },
{ 0, NULL },
};

18
drivers/pci/fsl_pci_init.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2007 Freescale Semiconductor, Inc.
* Copyright 2007-2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -413,13 +413,27 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
}
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
struct pci_controller *hose, int busno)
struct pci_controller *hose, int busno, int pcie_ep)
{
volatile ccsr_fsl_pci_t *pci;
struct pci_region *r;
pci = (ccsr_fsl_pci_t *) pci_info->regs;
if (pcie_ep) {
volatile pit_t *pi = &pci->pit[2];
pci_setup_indirect(hose, (u32)&pci->cfg_addr,
(u32)&pci->cfg_data);
out_be32(&pi->pitar, 0);
out_be32(&pi->piwbar, 0);
out_be32(&pi->piwar, PIWAR_EN | PIWAR_LOCAL |
PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_IWS_4K);
fsl_pci_config_unlock(hose);
return 0;
}
/* on non-PCIe controllers we don't have pme_msg_det so this code
* should do nothing since the read will return 0
*/

2
drivers/qe/fdt.c
View file

@ -85,6 +85,8 @@ void ft_qe_setup(void *blob)
"bus-frequency", gd->qe_clk, 1);
do_fixup_by_compat_u32(blob, "fsl,qe",
"brg-frequency", gd->brg_clk, 1);
do_fixup_by_compat_u32(blob, "fsl,qe-gtm",
"clock-frequency", gd->qe_clk / 2, 1);
fdt_fixup_qe_firmware(blob);
#endif
}

4
examples/standalone/stubs.c
View file

@ -181,9 +181,9 @@ gd_t *global_data;
" or %%g1, %%g7, %%g1\n" \
" ld [%%g1], %%g1\n" \
" ld [%%g1 + %1], %%g1\n" \
" call %%g1\n" \
" jmp %%g1\n" \
" nop\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x) : "g1" );
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" );
#else
#error stubs definition missing for this architecture

1
include/asm-arm/arch-davinci/gpio_defs.h
View file

@ -50,4 +50,3 @@ struct davinci_gpio_bank {
};
#endif

3
include/asm-blackfin/config.h
View file

@ -18,6 +18,9 @@
# define CONFIG_BFIN_SCRATCH_REG retn
#endif
/* Relocation to SDRAM works on all Blackfin boards */
#define CONFIG_RELOC_FIXUP_WORKS
/* Make sure the structure is properly aligned */
#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned

1
include/asm-blackfin/global_data.h
View file

@ -44,7 +44,6 @@ typedef struct global_data {
unsigned long baudrate;
unsigned long have_console; /* serial_init() was called */
phys_size_t ram_size; /* RAM size */
unsigned long reloc_off; /* Relocation Offset */
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)

10
include/asm-ppc/config.h
View file

@ -47,6 +47,16 @@
#define CONFIG_MAX_CPUS 1
#endif
/*
* Provide a default boot page translation virtual address that lines up with
* Freescale's default e500 reset page.
*/
#if (defined(CONFIG_E500) && defined(CONFIG_MP))
#ifndef CONFIG_BPTR_VIRT_ADDR
#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
#endif
#endif
/* Relocation to SDRAM works on all PPC boards */
#define CONFIG_RELOC_FIXUP_WORKS

3
include/asm-ppc/fsl_pci.h
View file

@ -62,6 +62,7 @@ typedef struct pci_inbound_window {
#define PIWAR_LOCAL 0x00f00000
#define PIWAR_READ_SNOOP 0x00050000
#define PIWAR_WRITE_SNOOP 0x00005000
#define PIWAR_IWS_4K 0x0000000b
u32 res2[3];
} pit_t;
@ -171,7 +172,7 @@ struct fsl_pci_info {
};
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
struct pci_controller *hose, int busno);
struct pci_controller *hose, int busno, int pcie_ep);
#define SET_STD_PCI_INFO(x, num) \
{ \

4
include/asm-ppc/immap_512x.h
View file

@ -215,8 +215,8 @@ typedef struct clk512x {
#define CLOCK_SCCR2_DIU_EN 0x80000000
#define CLOCK_SCCR2_AXE_EN 0x40000000
#define CLOCK_SCCR2_MEM_EN 0x20000000
#define CLOCK_SCCR2_USB2_EN 0x10000000
#define CLOCK_SCCR2_USB1_EN 0x08000000
#define CLOCK_SCCR2_USB1_EN 0x10000000
#define CLOCK_SCCR2_USB2_EN 0x08000000
#define CLOCK_SCCR2_I2C_EN 0x04000000
#define CLOCK_SCCR2_BDLC_EN 0x02000000
#define CLOCK_SCCR2_SDHC_EN 0x01000000

1
include/config_cmd_all.h
View file

@ -30,6 +30,7 @@
#define CONFIG_CMD_DOC /* Disk-On-Chip Support */
#define CONFIG_CMD_DTT /* Digital Therm and Thermostat */
#define CONFIG_CMD_ECHO /* echo arguments */
#define CONFIG_CMD_EDITENV /* editenv */
#define CONFIG_CMD_EEPROM /* EEPROM read/write support */
#define CONFIG_CMD_ELF /* ELF (VxWorks) load/boot cmd */
#define CONFIG_CMD_SAVEENV /* saveenv */

1
include/config_cmd_default.h
View file

@ -20,6 +20,7 @@
#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_ECHO /* echo arguments */
#define CONFIG_CMD_EDITENV /* editenv */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_IMI /* iminfo */
#define CONFIG_CMD_ITEST /* Integer (and string) test */

39
include/configs/MPC8569MDS.h
View file

@ -70,6 +70,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_HWCONFIG
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
@ -180,6 +181,29 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Chip select 3 - NAND */
#define CONFIG_SYS_NAND_BASE 0xFC000000
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
#define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
/*
* SDRAM on the LocalBus
@ -206,6 +230,7 @@ extern unsigned long get_clock_freq(void);
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#define CONFIG_SERIAL_MULTI 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
@ -258,8 +283,10 @@ extern unsigned long get_clock_freq(void);
#define PLPPAR1_I2C_BIT_MASK 0x0000000F
#define PLPPAR1_I2C2_VAL 0x00000000
#define PLPPAR1_ESDHC_VAL 0x0000000A
#define PLPDIR1_I2C_BIT_MASK 0x0000000F
#define PLPDIR1_I2C2_VAL 0x0000000F
#define PLPDIR1_ESDHC_VAL 0x00000006
/*
* General PCI
@ -450,6 +477,18 @@ extern unsigned long get_clock_freq(void);
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_MMC 1
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif
/*
* Miscellaneous configurable options
*/

2
include/configs/MPC8610HPCD.h
View file

@ -102,8 +102,6 @@
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
#define MPC86xx_DDR_SDRAM_CLK_CNTL
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

2
include/configs/MPC8641HPCN.h
View file

@ -141,8 +141,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
#define MPC86xx_DDR_SDRAM_CLK_CNTL
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

90
include/configs/P1_P2_RDB.h
View file

@ -43,6 +43,22 @@
#define CONFIG_P2020
#endif
#ifdef CONFIG_MK_NAND
#define CONFIG_NAND_U_BOOT 1
#define CONFIG_RAMBOOT_NAND 1
#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000
#endif
#ifdef CONFIG_MK_SDCARD
#define CONFIG_RAMBOOT_SDCARD 1
#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
#endif
#ifdef CONFIG_MK_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH 1
#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
@ -82,16 +98,34 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_MEMTEST_END 0x1fffffff
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
* Config the L2 Cache as L2 SRAM
*/
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
#else
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#endif
#define CONFIG_SYS_L2_SIZE (512 << 10)
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */
/* CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
/* CONFIG_SYS_IMMR */
#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
#else
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#endif
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
@ -158,6 +192,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
|| defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
@ -177,7 +218,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
#ifndef CONFIG_NAND_SPL
#define CONFIG_SYS_NAND_BASE 0xffa00000
#else
#define CONFIG_SYS_NAND_BASE 0xfff00000
#endif
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
@ -187,6 +232,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
/* NAND boot: 4K NAND loader config */
#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
/* NAND flash config */
#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
@ -202,10 +256,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
| OR_FCM_TRLX \
| OR_FCM_EHTR)
#ifdef CONFIG_RAMBOOT_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#endif
#define CONFIG_SYS_VSC7385_BASE 0xffb00000
@ -221,7 +282,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
//#define CONFIG_CONS_INDEX 2
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
@ -371,14 +431,26 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* Environment
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
#define CONFIG_ENV_ADDR 0xfff80000
#else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_NAND)
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
#else
#define CONFIG_ENV_IS_IN_FLASH 1
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
#define CONFIG_ENV_ADDR 0xfff80000
#else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */

8
include/configs/XPEDITE5370.h
View file

@ -48,6 +48,13 @@
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* Multicore config
*/
#define CONFIG_MP
#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
/*
* DDR config
*/
@ -109,6 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
* 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
* 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
* 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
* 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable

2
include/configs/amcc-common.h
View file

@ -156,6 +156,8 @@
*/
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
/* Update size in "reg" property of NOR FLASH device tree nodes */
#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
/*
* Booting and default environment

1
include/configs/davinci_dm6467evm.h
View file

@ -129,4 +129,3 @@
#endif
#endif /* __CONFIG_H */

12
include/configs/galaxy5200.h
View file

@ -88,15 +88,21 @@
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
/* even with bootdelay=0 */
#undef CONFIG_BOOTARGS
#define CONFIG_BOOT_RETRY_TIME 120 /* Reset if no command is entered */
#define CONFIG_RESET_TO_RETRY
#define CONFIG_PREBOOT "echo;" \
"echo Welcome to U-Boot;"\
"echo"
#define CONFIG_BOOTCOMMAND "go ff300004 0; go ff300004 2 2;" \
"bootm ff040000 ff900000 fffc0000"
#define CONFIG_BOOTARGS "console=ttyPSC0,115200"
#define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0"
/*
* IPB Bus clocking configuration.
*/
@ -210,7 +216,7 @@
/* Chip Select configuration for NAND flash */
#define CONFIG_SYS_CS1_START 0x20000000
#define CONFIG_SYS_CS1_SIZE 0x90000
#define CONFIG_SYS_CS1_CFG 0x0002d900
#define CONFIG_SYS_CS1_CFG 0x00025b00
/* Chip Select configuration for Epson S1D13513 */
#define CONFIG_SYS_CS3_START 0x10000000

2
include/configs/mcc200.h
View file

@ -398,7 +398,7 @@
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
#elif
#else
#error "Wrong QUART expander number."
#endif

1
include/configs/sbc35_a9g20.h
View file

@ -161,6 +161,7 @@
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_OFFSET_REDUND 0x80000
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"

4
include/configs/sbc8349.h
View file

@ -158,7 +158,7 @@
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \
(2 << BR_PS_SHIFT) | /* 32 bit port size */ \
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
BR_V) /* valid */
#define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */
@ -304,7 +304,7 @@
#define CONFIG_SYS_I2C1_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET
/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
/* TSEC */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000

2
include/configs/sbc8641d.h
View file

@ -121,8 +121,6 @@
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
#define MPC86xx_DDR_SDRAM_CLK_CNTL
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

6
include/configs/sequoia.h
View file

@ -243,6 +243,11 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
/* I2C bootstrap EEPROM */
#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
#define CONFIG_DTT_AD7414 1 /* use AD7414 */
@ -300,6 +305,7 @@
/*
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_CMD_CHIP_CONFIG
#define CONFIG_CMD_DTT
#define CONFIG_CMD_FAT
#define CONFIG_CMD_NAND

1
include/configs/tny_a9260.h
View file

@ -138,6 +138,7 @@
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_OFFSET_REDUND 0x80000
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"

2
include/configs/vme8349.h
View file

@ -224,7 +224,7 @@
#define CONFIG_SYS_I2C1_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET
/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */

2
include/fdt_support.h
View file

@ -79,5 +79,7 @@ void ft_pci_setup(void *blob, bd_t *bd);
void set_working_fdt_addr(void *addr);
int fdt_resize(void *blob);
int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size);
#endif /* ifdef CONFIG_OF_LIBFDT */
#endif /* ifndef __FDT_SUPPORT_H */

157
include/mtd/cfi_flash.h Normal file
View file

@ -0,0 +1,157 @@
/*
* (C) Copyright 2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __CFI_FLASH_H__
#define __CFI_FLASH_H__
#define FLASH_CMD_CFI 0x98
#define FLASH_CMD_READ_ID 0x90
#define FLASH_CMD_RESET 0xff
#define FLASH_CMD_BLOCK_ERASE 0x20
#define FLASH_CMD_ERASE_CONFIRM 0xD0
#define FLASH_CMD_WRITE 0x40
#define FLASH_CMD_PROTECT 0x60
#define FLASH_CMD_PROTECT_SET 0x01
#define FLASH_CMD_PROTECT_CLEAR 0xD0
#define FLASH_CMD_CLEAR_STATUS 0x50
#define FLASH_CMD_READ_STATUS 0x70
#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
#define FLASH_CMD_WRITE_BUFFER_PROG 0xE9
#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
#define FLASH_STATUS_DONE 0x80
#define FLASH_STATUS_ESS 0x40
#define FLASH_STATUS_ECLBS 0x20
#define FLASH_STATUS_PSLBS 0x10
#define FLASH_STATUS_VPENS 0x08
#define FLASH_STATUS_PSS 0x04
#define FLASH_STATUS_DPS 0x02
#define FLASH_STATUS_R 0x01
#define FLASH_STATUS_PROTECT 0x01
#define AMD_CMD_RESET 0xF0
#define AMD_CMD_WRITE 0xA0
#define AMD_CMD_ERASE_START 0x80
#define AMD_CMD_ERASE_SECTOR 0x30
#define AMD_CMD_UNLOCK_START 0xAA
#define AMD_CMD_UNLOCK_ACK 0x55
#define AMD_CMD_WRITE_TO_BUFFER 0x25
#define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29
#define AMD_STATUS_TOGGLE 0x40
#define AMD_STATUS_ERROR 0x20
#define ATM_CMD_UNLOCK_SECT 0x70
#define ATM_CMD_SOFTLOCK_START 0x80
#define ATM_CMD_LOCK_SECT 0x40
#define FLASH_CONTINUATION_CODE 0x7F
#define FLASH_OFFSET_MANUFACTURER_ID 0x00
#define FLASH_OFFSET_DEVICE_ID 0x01
#define FLASH_OFFSET_DEVICE_ID2 0x0E
#define FLASH_OFFSET_DEVICE_ID3 0x0F
#define FLASH_OFFSET_CFI 0x55
#define FLASH_OFFSET_CFI_ALT 0x555
#define FLASH_OFFSET_CFI_RESP 0x10
#define FLASH_OFFSET_PRIMARY_VENDOR 0x13
/* extended query table primary address */
#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15
#define FLASH_OFFSET_WTOUT 0x1F
#define FLASH_OFFSET_WBTOUT 0x20
#define FLASH_OFFSET_ETOUT 0x21
#define FLASH_OFFSET_CETOUT 0x22
#define FLASH_OFFSET_WMAX_TOUT 0x23
#define FLASH_OFFSET_WBMAX_TOUT 0x24
#define FLASH_OFFSET_EMAX_TOUT 0x25
#define FLASH_OFFSET_CEMAX_TOUT 0x26
#define FLASH_OFFSET_SIZE 0x27
#define FLASH_OFFSET_INTERFACE 0x28
#define FLASH_OFFSET_BUFFER_SIZE 0x2A
#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
#define FLASH_OFFSET_ERASE_REGIONS 0x2D
#define FLASH_OFFSET_PROTECT 0x02
#define FLASH_OFFSET_USER_PROTECTION 0x85
#define FLASH_OFFSET_INTEL_PROTECTION 0x81
#define CFI_CMDSET_NONE 0
#define CFI_CMDSET_INTEL_EXTENDED 1
#define CFI_CMDSET_AMD_STANDARD 2
#define CFI_CMDSET_INTEL_STANDARD 3
#define CFI_CMDSET_AMD_EXTENDED 4
#define CFI_CMDSET_MITSU_STANDARD 256
#define CFI_CMDSET_MITSU_EXTENDED 257
#define CFI_CMDSET_SST 258
#define CFI_CMDSET_INTEL_PROG_REGIONS 512
#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
# undef FLASH_CMD_RESET
# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
#endif
#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */
typedef union {
unsigned char c;
unsigned short w;
unsigned long l;
unsigned long long ll;
} cfiword_t;
/* CFI standard query structure */
struct cfi_qry {
u8 qry[3];
u16 p_id;
u16 p_adr;
u16 a_id;
u16 a_adr;
u8 vcc_min;
u8 vcc_max;
u8 vpp_min;
u8 vpp_max;
u8 word_write_timeout_typ;
u8 buf_write_timeout_typ;
u8 block_erase_timeout_typ;
u8 chip_erase_timeout_typ;
u8 word_write_timeout_max;
u8 buf_write_timeout_max;
u8 block_erase_timeout_max;
u8 chip_erase_timeout_max;
u8 dev_size;
u16 interface_desc;
u16 max_buf_write_size;
u8 num_erase_regions;
u32 erase_region_info[NUM_ERASE_REGIONS];
} __attribute__((packed));
struct cfi_pri_hdr {
u8 pri[3];
u8 major_version;
u8 minor_version;
} __attribute__((packed));
void flash_write_cmd(flash_info_t * info, flash_sect_t sect,
uint offset, u32 cmd);
#endif /* __CFI_FLASH_H__ */

7
include/ppc440.h
View file

@ -1701,9 +1701,14 @@
#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
#endif /* CONFIG_440GX */
#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define CPR0_ICFG_RLI_MASK 0x80000000
#define CPR0_SPCID_SPCIDV0_MASK 0x03000000
#define CPR0_SPCID_SPCIDV0_DIV1 0x01000000
#define CPR0_SPCID_SPCIDV0_DIV2 0x02000000
#define CPR0_SPCID_SPCIDV0_DIV3 0x03000000
#define CPR0_SPCID_SPCIDV0_DIV4 0x00000000
#define CPR0_PERD_PERDV0_MASK 0x07000000
#endif

2
include/ppc4xx.h
View file

@ -221,6 +221,8 @@ static inline void set_mcsr(u32 val)
asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
}
int ppc4xx_pci_sync_clock_config(u32 async);
#endif /* __ASSEMBLY__ */
/* for multi-cpu support */

6
lib_blackfin/board.c
View file

@ -278,7 +278,6 @@ static void board_net_init_r(bd_t *bd)
bb_miiphy_init();
#endif
#ifdef CONFIG_CMD_NET
uchar enetaddr[6];
char *s;
if ((s = getenv("bootfile")) != NULL)
@ -288,15 +287,11 @@ static void board_net_init_r(bd_t *bd)
printf("Net: ");
eth_initialize(gd->bd);
eth_getenv_enetaddr("ethaddr", enetaddr);
printf("MAC: %pM\n", enetaddr);
#endif
}
void board_init_r(gd_t * id, ulong dest_addr)
{
extern void malloc_bin_reloc(void);
char *s;
bd_t *bd;
gd = id;
@ -310,7 +305,6 @@ void board_init_r(gd_t * id, ulong dest_addr)
/* initialize malloc() area */
mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
malloc_bin_reloc();
#if !defined(CONFIG_SYS_NO_FLASH)
/* Initialize the flash and protect u-boot by default */

37
lib_generic/string.c
View file

@ -403,10 +403,26 @@ char *strswab(const char *s)
*/
void * memset(void * s,int c,size_t count)
{
char *xs = (char *) s;
unsigned long *sl = (unsigned long *) s;
unsigned long cl = 0;
char *s8;
int i;
/* do it one word at a time (32 bits or 64 bits) while possible */
if ( ((ulong)s & (sizeof(*sl) - 1)) == 0) {
for (i = 0; i < sizeof(*sl); i++) {
cl <<= 8;
cl |= c & 0xff;
}
while (count >= sizeof(*sl)) {
*sl++ = cl;
count -= sizeof(*sl);
}
}
/* fill 8 bits at a time */
s8 = (char *)sl;
while (count--)
*xs++ = c;
*s8++ = c;
return s;
}
@ -446,12 +462,23 @@ char * bcopy(const char * src, char * dest, int count)
* You should not use this function to access IO space, use memcpy_toio()
* or memcpy_fromio() instead.
*/
void * memcpy(void * dest,const void *src,size_t count)
void * memcpy(void *dest, const void *src, size_t count)
{
char *tmp = (char *) dest, *s = (char *) src;
unsigned long *dl = (unsigned long *)dest, *sl = (unsigned long *)src;
char *d8, *s8;
/* while all data is aligned (common case), copy a word at a time */
if ( (((ulong)dest | (ulong)src) & (sizeof(*dl) - 1)) == 0) {
while (count >= sizeof(*dl)) {
*dl++ = *sl++;
count -= sizeof(*dl);
}
}
/* copy the reset one byte at a time */
d8 = (char *)dl;
s8 = (char *)sl;
while (count--)
*tmp++ = *s++;
*d8++ = *s8++;
return dest;
}

2
lib_nios/board.c
View file

@ -49,7 +49,6 @@ DECLARE_GLOBAL_DATA_PTR;
*/
extern void malloc_bin_reloc (void);
typedef int (init_fnc_t) (void);
@ -115,7 +114,6 @@ void board_init (void)
/* The Malloc area is immediately below the monitor copy in RAM */
mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
malloc_bin_reloc();
WATCHDOG_RESET ();
bd->bi_flashsize = flash_init();

2
lib_nios2/board.c
View file

@ -52,7 +52,6 @@ DECLARE_GLOBAL_DATA_PTR;
*/
extern void malloc_bin_reloc (void);
typedef int (init_fnc_t) (void);
@ -121,7 +120,6 @@ void board_init (void)
/* The Malloc area is immediately below the monitor copy in RAM */
mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
malloc_bin_reloc();
WATCHDOG_RESET ();
bd->bi_flashsize = flash_init();

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