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arm: socfpga: cache: Enable PL310 L2 cache

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Enable the PL310 L2 cache controller support for the SoCFPGA.
With the cache related issues resolved, this is safe to be done.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
This commit is contained in:
Marek Vasut 2014-09-15 01:45:14 +02:00
parent 40e7bcdee7
commit b5e9b29625
1 changed files with 2 additions and 0 deletions
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2
include/configs/socfpga_cyclone5.h
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@ -27,6 +27,8 @@
#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/* base address for .text section */
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET