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ARM: AM43xx: Change DDR3 Reset Value

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The bit DDR3_RST_DEF_VAL inside CTRL_DDR_IO represents the default value
of the ddr reset value for DDR3 before the EMIF takes over. We must have
this bit set high so that on exit from DeepSleep0 within the kernel the
reset line has the proper value.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
This commit is contained in:
Dave Gerlach 2014-02-18 07:32:01 -05:00 committed by Tom Rini
parent f84880f0f3
commit b56b9a0884
1 changed files with 1 additions and 1 deletions
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arch/arm/cpu/armv7/am33xx/emif4.c
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@ -113,7 +113,7 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
;
writel(0x0, &ddrctrl->ddrioctrl);
writel(0x80000000, &ddrctrl->ddrioctrl);
config_io_ctrl(ioregs);