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ARM: atmel: sama5d4: can access DDR in interleave mode

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The SAMAA5D4 SoC can access DDR in interleave mode.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
This commit is contained in:
Bo Shen 2014-12-15 13:24:36 +08:00 committed by Andreas Bießmann
parent 569bbd3ceb
commit b54dd1b3ad
1 changed files with 1 additions and 1 deletions
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arch/arm/cpu/at91-common/mpddrc.c
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@ -19,7 +19,7 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
static int ddr2_decodtype_is_seq(u32 cr) static int ddr2_decodtype_is_seq(u32 cr)
{ {
#if defined(CONFIG_SAMA5D3) #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED) if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
return 0; return 0;
#endif #endif