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vexpress64: Add BASER_FVP vexpress board variant
The BASER_FVP board variant is implemented on top of the BASE_FVP board config (which, in turn, is based on the Juno Versatile Express board config). They all share a similar memory map - for BASER_FVP the map is inverted from the BASE_FVP (https://developer.arm.com/documentation/100964/1114/Base-Platform/Base---memory/BaseR-Platform-memory-map) * Create new TARGET_VEXPRESS64_BASER_FVP target, which uses the same board config as BASE_FVP and JUNO * Adapt vexpress_aemv8a.h header file to support BASER_FVP (and rename to vexpress_aemv8.h) * Enable config to switch to EL1 for the BASER_FVP * Create vexpress_aemv8r defconfig * Provide an MPU memory map for the BASER_FVP For now, only single core boot is supported. Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> [trini: Add MAINTAINERS, move BOOTCOMMAND to defconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Peter Hoyes
Tom Rini
parent
2f5b7b7490
commit
b53bbca63b
7 changed files with 94 additions and 24 deletions
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@ -1185,6 +1185,13 @@ config TARGET_VEXPRESS64_BASE_FVP
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select PL01X_SERIAL
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select SEMIHOSTING
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config TARGET_VEXPRESS64_BASER_FVP
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bool "Support Versatile Express ARMv8r64 FVP BASE model"
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select ARM64
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select DM
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select DM_SERIAL
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select PL01X_SERIAL
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config TARGET_VEXPRESS64_JUNO
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bool "Support Versatile Express Juno Development Platform"
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select ARM64
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@ -1,4 +1,5 @@
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if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO
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if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO || \
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TARGET_VEXPRESS64_BASER_FVP
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config SYS_BOARD
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default "vexpress64"
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@ -7,7 +8,7 @@ config SYS_VENDOR
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default "armltd"
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config SYS_CONFIG_NAME
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default "vexpress_aemv8a"
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default "vexpress_aemv8"
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config JUNO_DTB_PART
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string "NOR flash partition holding DTB"
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@ -14,3 +14,8 @@ JUNO DEVELOPMENT PLATFORM BOARD
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M: Linus Walleij <linus.walleij@linaro.org>
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S: Maintained
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F: configs/vexpress_aemv8a_juno_defconfig
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VEXPRESS64 BASER_FVP
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M: Peter Hoyes <Peter.Hoyes@arm.com>
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S: Maintained
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F: configs/vexpress_aemv8r_defconfig
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@ -18,6 +18,7 @@
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#include <dm/platform_data/serial_pl01x.h>
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#include "pcie.h"
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#include <asm/armv8/mmu.h>
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#include <asm/armv8/mpu.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -54,6 +55,27 @@ static struct mm_region vexpress64_mem_map[] = {
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struct mm_region *mem_map = vexpress64_mem_map;
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static struct mpu_region vexpress64_aemv8r_mem_map[] = {
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{
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.start = 0x0UL,
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.end = 0x7fffffffUL,
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.attrs = PRLAR_ATTRIDX(MT_NORMAL)
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}, {
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.start = 0x80000000UL,
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.end = 0xffffffffUL,
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.attrs = PRLAR_ATTRIDX(MT_DEVICE_NGNRNE)
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}, {
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.start = 0x100000000UL,
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.end = 0xffffffffffUL,
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.attrs = PRLAR_ATTRIDX(MT_NORMAL)
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}, {
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/* List terminator */
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0,
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}
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};
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struct mpu_region *mpu_mem_map = vexpress64_aemv8r_mem_map;
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/* This function gets replaced by platforms supporting PCIe.
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* The replacement function, eg. on Juno, initialises the PCIe bus.
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*/
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19
configs/vexpress_aemv8r_defconfig
Normal file
19
configs/vexpress_aemv8r_defconfig
Normal file
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@ -0,0 +1,19 @@
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CONFIG_ARM=y
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CONFIG_TARGET_VEXPRESS64_BASER_FVP=y
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CONFIG_SYS_TEXT_BASE=0x00001000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_SYS_MEMTEST_START=0x80000000
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CONFIG_SYS_MEMTEST_END=0xff000000
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CONFIG_ENV_SIZE=0x40000
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CONFIG_ENV_SECT_SIZE=0x40000
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CONFIG_IDENT_STRING=" vexpress_aemv8r64"
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_BOOTDELAY=3
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x9c090000 rootfstype=ext4 root=/dev/vda1 rw rootwait"
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CONFIG_USE_BOOTCOMMAND=y
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CONFIG_BOOTCOMMAND="fdt addr ${fdt_addr}; fdt resize; booti $kernel_addr - $fdt_addr"
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_SYS_PROMPT="VExpress64# "
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CONFIG_OF_LIBFDT=y
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@ -25,7 +25,7 @@ or turning on CONFIG_BASE_FVP for the more full featured model.
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Rather than create a new armv8 board similar to armltd/vexpress64, add
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semihosting calls to the existing one, enabled with CONFIG_SEMIHOSTING
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and CONFIG_BASE_FVP both set. Also reuse the existing board config file
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vexpress_aemv8a.h but differentiate the two models by the presence or
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vexpress_aemv8.h but differentiate the two models by the presence or
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absence of CONFIG_BASE_FVP. This change is tested and works on both the
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Foundation and Base fastmodel simulators.
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@ -10,30 +10,36 @@
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#define CONFIG_REMAKE_ELF
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/* Link Definitions */
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#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
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#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
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#else
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/* ATF loads u-boot here for BASE_FVP model */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
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#elif CONFIG_TARGET_VEXPRESS64_JUNO
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
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#endif
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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/* CS register bases for the original memory map. */
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#define V2M_PA_CS0 0x00000000
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#define V2M_PA_CS1 0x14000000
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#define V2M_PA_CS2 0x18000000
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#define V2M_PA_CS3 0x1c000000
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#define V2M_PA_CS4 0x0c000000
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#define V2M_PA_CS5 0x10000000
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#ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP
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#define V2M_BASE 0x00000000
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#define V2M_PA_BASE 0x80000000
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#else
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#define V2M_BASE 0x80000000
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#define V2M_PA_BASE 0x00000000
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#endif
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#define V2M_PA_CS0 (V2M_PA_BASE + 0x00000000)
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#define V2M_PA_CS1 (V2M_PA_BASE + 0x14000000)
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#define V2M_PA_CS2 (V2M_PA_BASE + 0x18000000)
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#define V2M_PA_CS3 (V2M_PA_BASE + 0x1c000000)
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#define V2M_PA_CS4 (V2M_PA_BASE + 0x0c000000)
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#define V2M_PA_CS5 (V2M_PA_BASE + 0x10000000)
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#define V2M_PERIPH_OFFSET(x) (x << 16)
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#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
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#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
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#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
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#define V2M_BASE 0x80000000
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/* Common peripherals relative to CS7. */
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#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
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#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
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@ -68,27 +74,27 @@
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#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 24000000 /* 24MHz */
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#define COUNTER_FREQUENCY 100000000 /* 100MHz */
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/* Generic Interrupt Controller Definitions */
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#ifdef CONFIG_GICV3
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#define GICD_BASE (0x2f000000)
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#define GICR_BASE (0x2f100000)
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#define GICD_BASE (V2M_PA_BASE + 0x2f000000)
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#define GICR_BASE (V2M_PA_BASE + 0x2f100000)
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#else
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#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
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#define GICD_BASE (0x2f000000)
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#define GICC_BASE (0x2c000000)
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#elif CONFIG_TARGET_VEXPRESS64_JUNO
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#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
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#define GICD_BASE (0x2C010000)
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#define GICC_BASE (0x2C02f000)
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#else
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#define GICD_BASE (V2M_PA_BASE + 0x2f000000)
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#define GICC_BASE (V2M_PA_BASE + 0x2c000000)
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#endif
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#endif /* !CONFIG_GICV3 */
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#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
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/* The Vexpress64 simulators use SMSC91C111 */
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#define CONFIG_SMC91111 1
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#define CONFIG_SMC91111_BASE (0x01A000000)
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#define CONFIG_SMC91111_BASE (V2M_PA_BASE + 0x01A000000)
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#endif
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/* PL011 Serial Configuration */
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@ -113,7 +119,7 @@
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#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
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#define PHYS_SDRAM_2 (0x880000000)
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#define PHYS_SDRAM_2_SIZE 0x180000000
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#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP && CONFIG_NR_DRAM_BANKS == 2
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#elif CONFIG_NR_DRAM_BANKS == 2
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#define PHYS_SDRAM_2 (0x880000000)
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#define PHYS_SDRAM_2_SIZE 0x80000000
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#endif
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@ -200,6 +206,12 @@
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" booti $kernel_addr - $fdt_addr; " \
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"fi"
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#endif
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#elif CONFIG_TARGET_VEXPRESS64_BASER_FVP
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"kernel_addr=0x00800000\0" \
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"fdt_addr=0x03000000\0" \
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"boot_addr=0x0007f800\0"
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#endif
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/* Monitor Command Prompt */
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@ -213,7 +225,7 @@
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/* Store environment at top of flash in the same location as blank.img */
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/* in the Juno firmware. */
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#else
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#define CONFIG_SYS_FLASH_BASE 0x0C000000
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#define CONFIG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000)
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/* 256 x 256KiB sectors */
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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/* Store environment at top of flash */
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@ -230,4 +242,8 @@
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
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#define FLASH_MAX_SECTOR_SIZE 0x00040000
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#ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP
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#define CONFIG_ARMV8_SWITCH_TO_EL1
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#endif
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#endif /* __VEXPRESS_AEMV8A_H */
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