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Merge branch '2018-12-26-master-imports'

Browse source 
- Misc TI platform fixes
- mt7629 fix for Linux compatible SMP support
- Other small regression fixes
This commit is contained in:
Tom Rini 2018-12-27 07:50:24 -05:00
commit b47b381037
13 changed files with 114 additions and 27 deletions
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5
api/api_storage.c
View file

@ -99,6 +99,7 @@ static int dev_stor_get(int type, int *more, struct device_info *di)
{
struct blk_desc *dd;
int found = 0;
int found_last = 0;
int i = 0;
/* Wasn't configured for this type, return 0 directly */
@ -111,9 +112,13 @@ static int dev_stor_get(int type, int *more, struct device_info *di)
if (di->cookie ==
(void *)blk_get_dev(specs[type].name, i)) {
i += 1;
found_last = 1;
break;
}
}
if (!found_last)
i = 0;
}
for (; i < specs[type].max_dev; i++) {

2
arch/arm/mach-k3/config.mk
View file

@ -37,7 +37,7 @@ cmd_gencert = cat $(srctree)/tools/k3_x509template.txt | sed $(SED_OPTS) > u-boo
ifeq ($(CONFIG_SYS_K3_KEY), "")
KEY=u-boot-spl-eckey.pem
else
KEY=$(patsubst "%",%,$(CONFIG_SYS_K3_KEY))
KEY=$(patsubst "%",$(srctree)/%,$(CONFIG_SYS_K3_KEY))
endif
u-boot-spl-eckey.pem: FORCE

52
arch/arm/mach-mediatek/mt7629/lowlevel_init.S
View file

@ -5,6 +5,14 @@
#include <linux/linkage.h>
#define WAIT_CODE_SRAM_BASE 0x0010ff00
#define SLAVE_JUMP_REG 0x10202034
#define SLAVE1_MAGIC_REG 0x10202038
#define SLAVE1_MAGIC_NUM 0x534c4131
#define GIC_CPU_BASE 0x10320000
ENTRY(lowlevel_init)
#ifndef CONFIG_SPL_BUILD
@ -28,6 +36,7 @@ ENTRY(lowlevel_init)
mrc p15, 0, r0, c0, c0, 5
ands r1, r0, #0x40000000
bne go @ Go if UP
/* read slave CPU number */
ands r0, r0, #0x0f
beq go @ Go if core0 on primary core tile
b secondary
@ -37,14 +46,41 @@ go:
mov pc, lr
secondary:
/* read slave CPU number into r0 firstly */
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #0x0f
/* enable GIC as cores will be waken up by IPI */
ldr r2, =GIC_CPU_BASE
mov r1, #0xf0
str r1, [r2, #4]
mov r1, #1
str r1, [r2, #0]
ldr r1, [r2]
orr r1, #1
str r1, [r2]
/* copy wait code into SRAM */
ldr r0, =slave_cpu_wait
ldm r0, {r1 - r8} @ slave_cpu_wait has eight insns
ldr r0, =WAIT_CODE_SRAM_BASE
stm r0, {r1 - r8}
/* pass args to slave_cpu_wait */
ldr r0, =SLAVE1_MAGIC_REG
ldr r1, =SLAVE1_MAGIC_NUM
/* jump to wait code in SRAM */
ldr pc, =WAIT_CODE_SRAM_BASE
loop:
dsb
isb
wfi @Zzz...
b loop
#endif
ENDPROC(lowlevel_init)
/* This function will be copied into SRAM */
ENTRY(slave_cpu_wait)
wfi
ldr r2, [r0]
cmp r2, r1
bne slave_cpu_wait
movw r0, #:lower16:SLAVE_JUMP_REG
movt r0, #:upper16:SLAVE_JUMP_REG
ldr r1, [r0]
mov pc, r1
ENDPROC(slave_cpu_wait)

5
arch/arm/mach-omap2/omap3/Kconfig
View file

@ -3,18 +3,23 @@ if OMAP34XX
# We only enable the clocks for the GPIO banks that a given board requies.
config OMAP3_GPIO_2
bool
default y if CMD_GPIO
config OMAP3_GPIO_3
bool
default y if CMD_GPIO
config OMAP3_GPIO_4
bool
default y if CMD_GPIO
config OMAP3_GPIO_5
bool
default y if CMD_GPIO
config OMAP3_GPIO_6
bool
default y if CMD_GPIO
choice
prompt "OMAP3 board select"

10
arch/arm/mach-omap2/omap3/clock.c
View file

@ -750,23 +750,23 @@ void per_clocks_enable(void)
setbits_le32(&prcm_base->iclken_per, 0x00000800);
#endif
#if (CONFIG_IS_ENABLED(OMAP3_GPIO_2) || CONFIG_IS_ENABLED(CMD_GPIO))
#if defined(CONFIG_OMAP3_GPIO_2)
setbits_le32(&prcm_base->fclken_per, 0x00002000);
setbits_le32(&prcm_base->iclken_per, 0x00002000);
#endif
#if (CONFIG_IS_ENABLED(OMAP3_GPIO_3) || CONFIG_IS_ENABLED(CMD_GPIO))
#if defined(CONFIG_OMAP3_GPIO_3)
setbits_le32(&prcm_base->fclken_per, 0x00004000);
setbits_le32(&prcm_base->iclken_per, 0x00004000);
#endif
#if (CONFIG_IS_ENABLED(OMAP3_GPIO_4) || CONFIG_IS_ENABLED(CMD_GPIO))
#if defined(CONFIG_OMAP3_GPIO_4)
setbits_le32(&prcm_base->fclken_per, 0x00008000);
setbits_le32(&prcm_base->iclken_per, 0x00008000);
#endif
#if (CONFIG_IS_ENABLED(OMAP3_GPIO_5) || CONFIG_IS_ENABLED(CMD_GPIO))
#if defined(CONFIG_OMAP3_GPIO_5)
setbits_le32(&prcm_base->fclken_per, 0x00010000);
setbits_le32(&prcm_base->iclken_per, 0x00010000);
#endif
#if (CONFIG_IS_ENABLED(OMAP3_GPIO_6) || CONFIG_IS_ENABLED(CMD_GPIO))
#if defined(CONFIG_OMAP3_GPIO_6)
setbits_le32(&prcm_base->fclken_per, 0x00020000);
setbits_le32(&prcm_base->iclken_per, 0x00020000);
#endif

36
doc/README.commands
View file

@ -28,6 +28,42 @@ comp: Pointer to the completion function. May be NULL.
entering the command arguments to complete the entry. Command
completion is only available if CONFIG_AUTO_COMPLETE is defined.
Sub-command definition
----------------------
Likewise an array of cmd_tbl_t holding sub-commands can be created using either
of the following macros:
* U_BOOT_CMD_MKENT(name, maxargs, repeatable, command, "usage", "help")
* U_BOOT_CMD_MKENTCOMPLETE(name, maxargs, repeatable, command, "usage, "help",
comp)
This table has to be evaluated in the command function of the main command, e.g.
static cmd_tbl_t cmd_sub[] = {
U_BOOT_CMD_MKENT(foo, CONFIG_SYS_MAXARGS, 1, do_foo, "", ""),
U_BOOT_CMD_MKENT(bar, CONFIG_SYS_MAXARGS, 1, do_bar, "", ""),
};
static int do_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
cmd_tbl_t *cp;
if (argc < 2)
return CMD_RET_USAGE;
/* drop sub-command argument */
argc--;
argv++;
cp = find_cmd_tbl(argv[0], cmd_ut_sub, ARRAY_SIZE(cmd_sub));
if (cp)
return cp->cmd(cmdtp, flag, argc, argv);
return CMD_RET_USAGE;
}
Command function
----------------

3
drivers/net/phy/phy.c
View file

@ -656,7 +656,8 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
phy_probe(dev);
bus->phymap[addr] = dev;
if (addr >= 0 && addr < PHY_MAX_ADDR)
bus->phymap[addr] = dev;
return dev;
}

4
drivers/pinctrl/pinctrl-uclass.c
View file

@ -117,9 +117,9 @@ static int pinconfig_post_bind(struct udevice *dev)
int ret;
dev_for_each_subnode(node, dev) {
if (pre_reloc_only &&
!ofnode_pre_reloc(node))
if (pre_reloc_only ^ ofnode_pre_reloc(node))
continue;
/*
* If this node has "compatible" property, this is not
* a pin configuration node, but a normal device. skip.

2
drivers/power/regulator/regulator-uclass.c
View file

@ -113,7 +113,7 @@ int regulator_set_enable(struct udevice *dev, bool enable)
uc_pdata = dev_get_uclass_platdata(dev);
if (!enable && uc_pdata->always_on)
return -EACCES;
return 0;
return ops->set_enable(dev, enable);
}

2
include/configs/mt7623.h
View file

@ -46,7 +46,7 @@
/* DRAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* This is neede for kernel booting */
/* This is needed for kernel booting */
#define FDT_HIGH "fdt_high=0xac000000\0"
/* Extra environment variables */

4
include/configs/omap3_igep00x0.h
View file

@ -20,10 +20,6 @@
#define CONFIG_REVISION_TAG 1
/* GPIO banks */
#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO bank 2 */
#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO bank 4 */
/* TPS65950 */
#define PBIASLITEVMODE1 (1 << 8)

9
scripts/check-config.sh
View file

@ -17,6 +17,15 @@
set -e
set -u
PROG_NAME="${0##*/}"
usage() {
echo "$PROG_NAME <path to u-boot.cfg> <path to whitelist file> <source dir>"
exit 1
}
[ $# -ge 3 ] || usage
path="$1"
whitelist="$2"
srctree="$3"

7
test/overlay/Kconfig
View file

@ -1,11 +1,10 @@
config UT_OVERLAY
bool "Enable Device Tree Overlays Unit Tests"
depends on OF_LIBFDT_OVERLAY
depends on UNIT_TEST
depends on UNIT_TEST && OF_CONTROL
default y
select OF_LIBFDT_OVERLAY
help
This enables the 'ut overlay' command which runs a series of unit
tests on the fdt overlay code.
If all is well then all tests pass although there will be a few
messages printed along the way.
Be warned that it requires an out-of-tree dtc compiler with patches
to support the DT overlays, otherwise it will fail.