mirror of
https://github.com/AsahiLinux/u-boot
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sbc82xx: delete support for obsolete SBC8240/SBC8260
The EST SBC8260 is over 10 years old, and the SBC8240 older than that. With the tiny amount of RAM (by today's standards), there really isn't anyone interested in running the latest U-boot on these EOL products anymore. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> CC: jon.diekema@smiths-aerospace.com
This commit is contained in:
Paul Gortmaker
Wolfgang Denk
parent
2c32003a5e
commit
b30d41cad6
16 changed files with 4 additions and 3123 deletions
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@ -134,10 +134,6 @@ Wolfgang Denk <wd@denx.de>
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PCIPPC2 MPC750
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PCIPPC6 MPC750
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Jon Diekema <jon.diekema@smiths-aerospace.com>
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sbc8260 MPC8260
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Alex Dubov <oakad@yahoo.com>
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mpq101 MPC8548
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@ -687,7 +687,7 @@ eth_loopback_test (void)
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immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\
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CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\
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CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16;
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#elif defined(CONFIG_SBC8260) || defined(CONFIG_SACSng)
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#elif defined(CONFIG_SACSng)
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/*
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* Attention: this is board-specific
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* 1, FCC2
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@ -1,44 +0,0 @@
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#
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS = $(BOARD).o flash.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -1,140 +0,0 @@
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The supported features of the SBC8240/8245 board are:
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8240 or 8245 processor
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66MHz & 100MHz bus speed
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Decrementer timer
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1 UART channel (Console channel)
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8240 Interrupt Controller
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8240 PCI bridge
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8240 Memory Controller
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SDRAM (16, 64 MB Memory DIMM)
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FLASH 512K On board
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FLASH 4MB On board
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Memory Map from CPU point of view:
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Start Size Access to
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-----------------------------------------------------
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0x00000000 64MB SDRAM DIMM
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0xFF000000 4MB On Board FLASH
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0xFFF00000 512K On Board FLASH or SRAM (Configured by jumper)
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0xFFE00000 8K EEPROM
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0xFFE80000 8Bit LED
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0xFFF80000 8Bit UART
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Setting the board Jumpers & Switches:
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In order to get the board running with the default configuration the
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jumpers need to be set as follows:
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General Jumpers:
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____________________________________________
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| Jumpers | Jumpers | Jumpers |
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|-------------|--------------|---------------|
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|JP1 1-2 | JP14 1-2 | JP27 1-2 |
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|JP5 Open | JP15 1-2 | JP28 2-3 |
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|JP8 1-2 | JP16 1-2 | JP33 Open |
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|JP9 1-2 | JP17 1-2 | JP37 Close |
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|JP10 1-2 | JP18 1-2 | |
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|JP11 2-3 | JP19 1-2 | |
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|JP12 1-2 | JP20 1-2 | |
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|JP13 1-2 | JP25 Open | |
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|_____________|______________|_______________|
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Bus speed Jumpers:
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_________________________
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| 100MHz Bus | 66 MHz Bus |
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|------------|------------|
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| JP2 1-2 | JP2 1-2 |
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| JP3 1-2 | JP3 2-3 |
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| JP4 1-2 | JP4 2-3 |
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| JP6 1-2 | JP6 2-3 |
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| JP7 1-2 | JP7 1-2 |
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|____________|____________|
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U-Boot 1.1.2 (Jun 24 2004 - 17:01:04)
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CPU: MPC8240 Revision 1.1 at 247.500 MHz: 16 kB I-Cache 16 kB D-Cache
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Board: sbc8240 Revision 255 Local Bus at 99 MHz
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DRAM: 64 MB
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FLASH: 512 kB
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00 11 8086 1229 0200 00
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In: serial
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Out: serial
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Err: serial
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Net: i82559#0
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Welcome to U-Boot for the sbc8240
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Type ? or help to get on-line help
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Hit any key to stop autoboot: 0
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=> printenv
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bootcmd=version;echo;tftpboot $loadaddr $loadfile;bootvx
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bootdelay=5
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baudrate=9600
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ethaddr=DE:AD:BE:EF:01:01
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ipaddr=192.168.193.102
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preboot=echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type "? or help" to get on-line help;echo
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netmask=255.255.255.248
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clocks_in_mhz=1
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bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 tn=sbc8240 o=fei
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ipaddr=192.168.193.102
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loadfile=vxWorks.st
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loadaddr=0x01000000
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net_load=tftpboot $loadaddr $loadfile
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serverip=192.168.193.99
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ethact=i82559#0
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stdin=serial
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stdout=serial
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stderr=serial
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Environment size: 631/16380 bytes
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=> boot
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U-Boot 1.1.2 (Jun 24 2004 - 17:01:04)
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Using i82559#0 device
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TFTP from server 192.168.193.99; our IP address is 192.168.193.102
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Filename 'vxWorks.st'.
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Load address: 0x1000000
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Loading: #################################################################
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#################################################################
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##############################################################
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done
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Bytes transferred = 979927 (ef3d7 hex)
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## Ethernet MAC address not copied to NV RAM
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Loading .text @ 0x00100000 (758848 bytes)
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Loading .data @ 0x001b9440 (79904 bytes)
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Clearing .bss @ 0x001ccc60 (20288 bytes)
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## Using bootline (@ 0x4200): $fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 tn=sbc8240 o=fei
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## Starting vxWorks at 0x00100000 ...
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Adding 2845 symbols for standalone.
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]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
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]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
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]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
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]]]]]]]]]]] ]]]] ]]]]]]]]]] ]] ]]]] (R)
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] ]]]]]]]]] ]]]]]] ]]]]]]]] ]] ]]]]
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]] ]]]]]]] ]]]]]]]] ]]]]]] ] ]] ]]]]
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]]] ]]]]] ] ]]] ] ]]]] ]]] ]]]]]]]]] ]]]] ]] ]]]] ]] ]]]]]
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]]]] ]]] ]] ] ]]] ]] ]]]]] ]]]]]] ]] ]]]]]]] ]]]] ]] ]]]]
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]]]]] ] ]]]] ]]]]] ]]]]]]]] ]]]] ]] ]]]] ]]]]]]] ]]]]
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]]]]]] ]]]]] ]]]]]] ] ]]]]] ]]]] ]] ]]]] ]]]]]]]] ]]]]
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]]]]]]] ]]]]] ] ]]]]]] ] ]]] ]]]] ]] ]]]] ]]]] ]]]] ]]]]
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]]]]]]]] ]]]]] ]]] ]]]]]]] ] ]]]]]]] ]]]] ]]]] ]]]] ]]]]]
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]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
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]]]]]]]]]]]]]]]]]]]]]]]]]]]]] Development System
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]]]]]]]]]]]]]]]]]]]]]]]]]]]]
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]]]]]]]]]]]]]]]]]]]]]]]]]]] VxWorks version 5.5.1
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]]]]]]]]]]]]]]]]]]]]]]]]]] KERNEL: WIND version 2.6
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]]]]]]]]]]]]]]]]]]]]]]]]] Copyright Wind River Systems, Inc., 1984-2003
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CPU: MPC8240 -- Wind River BSP. SBC8240 Board. Processor #0.
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Memory Size: 0x2000000. BSP version 1.2/28.
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->
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@ -1,638 +0,0 @@
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/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Modified 4/5/2001
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* Wait for completion of each sector erase command issued
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* 4/5/2001
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* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
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*/
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#include <common.h>
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#include <mpc824x.h>
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#include <asm/processor.h>
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#if CONFIG_SYS_MAX_FLASH_BANKS != 1
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#error "CONFIG_SYS_MAX_FLASH_BANKS must be 1"
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#endif
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (vu_long * addr, flash_info_t * info);
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static int write_word (flash_info_t * info, ulong dest, ulong data);
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static void flash_get_offsets (ulong base, flash_info_t * info);
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#define ADDR0 0x5555
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#define ADDR1 0x2aaa
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#define FLASH_WORD_SIZE unsigned char
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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unsigned long size_b0;
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/* Init: no FLASHes known */
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flash_info[0].flash_id = FLASH_UNKNOWN;
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/* Static FLASH Bank configuration here - FIXME XXX */
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size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size_b0, size_b0 << 20);
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}
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/* Only one bank */
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/* Setup offsets */
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flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
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/* Monitor protection ON by default */
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(void) flash_protect (FLAG_PROTECT_SET,
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FLASH_BASE0_PRELIM,
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FLASH_BASE0_PRELIM + monitor_flash_len - 1,
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&flash_info[0]);
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flash_info[0].size = size_b0;
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return size_b0;
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_get_offsets (ulong base, flash_info_t * info)
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{
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int i;
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/* set up sector start address table */
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if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
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(info->flash_id == FLASH_AM040)) {
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for (i = 0; i < info->sector_count; i++)
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info->start[i] = base + (i * 0x00010000);
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} else {
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if (info->flash_id & FLASH_BTYPE) {
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/* set sector offsets for bottom boot block type */
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info->start[0] = base + 0x00000000;
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info->start[1] = base + 0x00004000;
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info->start[2] = base + 0x00006000;
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info->start[3] = base + 0x00008000;
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for (i = 4; i < info->sector_count; i++) {
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info->start[i] =
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base + (i * 0x00010000) - 0x00030000;
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}
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} else {
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/* set sector offsets for top boot block type */
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i = info->sector_count - 1;
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info->start[i--] = base + info->size - 0x00004000;
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info->start[i--] = base + info->size - 0x00006000;
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info->start[i--] = base + info->size - 0x00008000;
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for (; i >= 0; i--) {
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info->start[i] = base + i * 0x00010000;
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}
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}
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}
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t * info)
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{
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int i;
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int k;
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int size;
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int erased;
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volatile unsigned long *flash;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD:
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printf ("AMD ");
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break;
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case FLASH_MAN_FUJ:
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printf ("FUJITSU ");
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break;
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case FLASH_MAN_SST:
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printf ("SST ");
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break;
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default:
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printf ("Unknown Vendor ");
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AM040:
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printf ("AM29F040 (512 Kbit, uniform sector size)\n");
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break;
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case FLASH_AM400B:
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printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM400T:
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printf ("AM29LV400T (4 Mbit, top boot sector)\n");
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break;
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case FLASH_AM800B:
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printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM800T:
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printf ("AM29LV800T (8 Mbit, top boot sector)\n");
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break;
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case FLASH_AM160B:
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printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM160T:
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printf ("AM29LV160T (16 Mbit, top boot sector)\n");
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break;
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case FLASH_AM320B:
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printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM320T:
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printf ("AM29LV320T (32 Mbit, top boot sector)\n");
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break;
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case FLASH_SST800A:
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printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
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break;
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case FLASH_SST160A:
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printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
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break;
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default:
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printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld KB in %d Sectors\n",
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info->size >> 10, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i = 0; i < info->sector_count; ++i) {
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/*
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* Check if whole sector is erased
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*/
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if (i != (info->sector_count - 1))
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size = info->start[i + 1] - info->start[i];
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else
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size = info->start[0] + info->size - info->start[i];
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erased = 1;
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flash = (volatile unsigned long *) info->start[i];
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size = size >> 2; /* divide by 4 for longword access */
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for (k = 0; k < size; k++) {
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if (*flash++ != 0xffffffff) {
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erased = 0;
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break;
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}
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}
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s%s",
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info->start[i],
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erased ? " E" : " ", info->protect[i] ? "RO " : " "
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);
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}
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printf ("\n");
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return;
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}
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/*-----------------------------------------------------------------------
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*/
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/*-----------------------------------------------------------------------
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*/
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/*
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* The following code cannot be run from FLASH!
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*/
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static ulong flash_get_size (vu_long * addr, flash_info_t * info)
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{
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short i;
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FLASH_WORD_SIZE value;
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ulong base = (ulong) addr;
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volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
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/* Write auto select command: read Manufacturer ID */
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addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
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addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
|
||||
|
||||
value = addr2[0];
|
||||
|
||||
switch (value) {
|
||||
case (FLASH_WORD_SIZE) AMD_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
case (FLASH_WORD_SIZE) FUJ_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_FUJ;
|
||||
break;
|
||||
case (FLASH_WORD_SIZE) SST_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_SST;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
value = addr2[1]; /* device ID */
|
||||
|
||||
switch (value) {
|
||||
case (FLASH_WORD_SIZE) AMD_ID_F040B:
|
||||
info->flash_id += FLASH_AM040;
|
||||
info->sector_count = 8;
|
||||
info->size = 0x0080000; /* => 512 ko */
|
||||
break;
|
||||
case (FLASH_WORD_SIZE) AMD_ID_LV040B:
|
||||
info->flash_id += FLASH_AM040;
|
||||
info->sector_count = 8;
|
||||
info->size = 0x0080000; /* => 512 ko */
|
||||
break;
|
||||
case (FLASH_WORD_SIZE) AMD_ID_LV400T:
|
||||
info->flash_id += FLASH_AM400T;
|
||||
info->sector_count = 11;
|
||||
info->size = 0x00080000;
|
||||
break; /* => 0.5 MB */
|
||||
|
||||
case (FLASH_WORD_SIZE) AMD_ID_LV400B:
|
||||
info->flash_id += FLASH_AM400B;
|
||||
info->sector_count = 11;
|
||||
info->size = 0x00080000;
|
||||
break; /* => 0.5 MB */
|
||||
|
||||
case (FLASH_WORD_SIZE) AMD_ID_LV800T:
|
||||
info->flash_id += FLASH_AM800T;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
|
||||
case (FLASH_WORD_SIZE) AMD_ID_LV800B:
|
||||
info->flash_id += FLASH_AM800B;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
|
||||
case (FLASH_WORD_SIZE) AMD_ID_LV160T:
|
||||
info->flash_id += FLASH_AM160T;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00200000;
|
||||
break; /* => 2 MB */
|
||||
|
||||
case (FLASH_WORD_SIZE) AMD_ID_LV160B:
|
||||
info->flash_id += FLASH_AM160B;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00200000;
|
||||
break; /* => 2 MB */
|
||||
#if 0 /* enable when device IDs are available */
|
||||
case (FLASH_WORD_SIZE) AMD_ID_LV320T:
|
||||
info->flash_id += FLASH_AM320T;
|
||||
info->sector_count = 67;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 4 MB */
|
||||
|
||||
case (FLASH_WORD_SIZE) AMD_ID_LV320B:
|
||||
info->flash_id += FLASH_AM320B;
|
||||
info->sector_count = 67;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 4 MB */
|
||||
#endif
|
||||
case (FLASH_WORD_SIZE) SST_ID_xF800A:
|
||||
info->flash_id += FLASH_SST800A;
|
||||
info->sector_count = 16;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
|
||||
case (FLASH_WORD_SIZE) SST_ID_xF160A:
|
||||
info->flash_id += FLASH_SST160A;
|
||||
info->sector_count = 32;
|
||||
info->size = 0x00200000;
|
||||
break; /* => 2 MB */
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return (0); /* => no or unknown flash */
|
||||
|
||||
}
|
||||
|
||||
/* set up sector start address table */
|
||||
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
|
||||
(info->flash_id == FLASH_AM040)) {
|
||||
for (i = 0; i < info->sector_count; i++)
|
||||
info->start[i] = base + (i * 0x00010000);
|
||||
} else {
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
info->start[0] = base + 0x00000000;
|
||||
info->start[1] = base + 0x00004000;
|
||||
info->start[2] = base + 0x00006000;
|
||||
info->start[3] = base + 0x00008000;
|
||||
for (i = 4; i < info->sector_count; i++) {
|
||||
info->start[i] =
|
||||
base + (i * 0x00010000) - 0x00030000;
|
||||
}
|
||||
} else {
|
||||
/* set sector offsets for top boot block type */
|
||||
i = info->sector_count - 1;
|
||||
info->start[i--] = base + info->size - 0x00004000;
|
||||
info->start[i--] = base + info->size - 0x00006000;
|
||||
info->start[i--] = base + info->size - 0x00008000;
|
||||
for (; i >= 0; i--) {
|
||||
info->start[i] = base + i * 0x00010000;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
/* D0 = 1 if protected */
|
||||
addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
|
||||
info->protect[i] = 0;
|
||||
else
|
||||
info->protect[i] = addr2[2] & 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH.
|
||||
*/
|
||||
if (info->flash_id != FLASH_UNKNOWN) {
|
||||
addr2 = (FLASH_WORD_SIZE *) info->start[0];
|
||||
*addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
|
||||
}
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
int wait_for_DQ7 (flash_info_t * info, int sect)
|
||||
{
|
||||
ulong start, now, last;
|
||||
volatile FLASH_WORD_SIZE *addr =
|
||||
(FLASH_WORD_SIZE *) (info->start[sect]);
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
|
||||
(FLASH_WORD_SIZE) 0x00800080) {
|
||||
if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return -1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
|
||||
volatile FLASH_WORD_SIZE *addr2;
|
||||
int flag, prot, sect, l_sect;
|
||||
int i;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("Can't erase unknown flash type - aborted\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
|
||||
printf ("Erasing sector %p\n", addr2); /* CLH */
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) ==
|
||||
FLASH_MAN_SST) {
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
|
||||
addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
|
||||
for (i = 0; i < 50; i++)
|
||||
udelay (1000); /* wait 1 ms */
|
||||
} else {
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
|
||||
addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
|
||||
}
|
||||
l_sect = sect;
|
||||
/*
|
||||
* Wait for each sector to complete, it's more
|
||||
* reliable. According to AMD Spec, you must
|
||||
* issue all erase commands within a specified
|
||||
* timeout. This has been seen to fail, especially
|
||||
* if printf()s are included (for debug)!!
|
||||
*/
|
||||
wait_for_DQ7 (info, sect);
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
wait_for_DQ7 (info, l_sect);
|
||||
|
||||
DONE:
|
||||
#endif
|
||||
/* reset to read mode */
|
||||
addr = (FLASH_WORD_SIZE *) info->start[0];
|
||||
addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
for (; i < 4 && cnt > 0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt == 0 && i < 4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i = 0; i < 4; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i < 4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
|
||||
return (write_word (info, wp, data));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t * info, ulong dest, ulong data)
|
||||
{
|
||||
volatile FLASH_WORD_SIZE *addr2 =
|
||||
(FLASH_WORD_SIZE *) (info->start[0]);
|
||||
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
|
||||
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
|
||||
ulong start;
|
||||
int i;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((volatile FLASH_WORD_SIZE *) dest) &
|
||||
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
|
||||
int flag;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
|
||||
|
||||
dest2[i] = data2[i];
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
|
||||
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
|
||||
|
||||
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -1,111 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
|
||||
*
|
||||
* (C) Copyright 2001, 2002
|
||||
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
|
||||
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc824x.h>
|
||||
#include <asm/processor.h>
|
||||
#include <pci.h>
|
||||
#include <netdev.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define BOARD_REV_REG 0xFE80002B
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
char revision = *(volatile char *)(BOARD_REV_REG);
|
||||
char buf[32];
|
||||
|
||||
puts ("Board: sbc8240 ");
|
||||
printf("Revision %d ", revision);
|
||||
printf("Local Bus at %s MHz\n", strmhz(buf, gd->bus_clk));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
long size;
|
||||
long new_bank0_end;
|
||||
long mear1;
|
||||
long emear1;
|
||||
|
||||
size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
|
||||
|
||||
new_bank0_end = size - 1;
|
||||
mear1 = mpc824x_mpc107_getreg(MEAR1);
|
||||
emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
||||
mear1 = (mear1 & 0xFFFFFF00) |
|
||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
||||
emear1 = (emear1 & 0xFFFFFF00) |
|
||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
|
||||
mpc824x_mpc107_setreg(MEAR1, mear1);
|
||||
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
||||
|
||||
return (size);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize PCI Devices, report devices found.
|
||||
*/
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
static struct pci_config_table pci_sandpoint_config_table[] = {
|
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
|
||||
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
|
||||
PCI_ENET0_MEMADDR,
|
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
|
||||
|
||||
{ }
|
||||
};
|
||||
#endif
|
||||
|
||||
struct pci_controller hose = {
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
config_table: pci_sandpoint_config_table,
|
||||
#endif
|
||||
};
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
pci_mpc824x_init(&hose);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MISC_INIT_R
|
||||
/* ------------------------------------------------------------------------- */
|
||||
int misc_init_r (void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_LED_BASE
|
||||
*((unsigned char *) (CONFIG_SYS_LED_BASE)) = 0xFF;
|
||||
#endif /* CONFIG_SYS_LED_BASE */
|
||||
|
||||
return (0);
|
||||
}
|
||||
#endif /* CONFIG_MISC_INIT_R */
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := sbc8260.o flash.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -1,392 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Flash Routines for AMD 29F080B devices
|
||||
*
|
||||
*--------------------------------------------------------------------
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc8xx.h>
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size;
|
||||
int i;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* for now, only support the 4 MB Flash SIMM */
|
||||
size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
|
||||
|
||||
/*
|
||||
* protect monitor and environment sectors
|
||||
*/
|
||||
|
||||
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_SYS_MONITOR_BASE,
|
||||
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
|
||||
# ifndef CONFIG_ENV_SIZE
|
||||
# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
# endif
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_ENV_ADDR,
|
||||
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
return /*size*/ (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info (flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch ((info->flash_id >> 16) & 0xff) {
|
||||
case 0x1:
|
||||
printf ("AMD ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case AMD_ID_F040B:
|
||||
printf ("AM29F040B (4 Mbit)\n");
|
||||
break;
|
||||
case AMD_ID_F080B:
|
||||
printf ("AM29F080B (8 Mbit)\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i=0; i<info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s",
|
||||
info->start[i],
|
||||
info->protect[i] ? " (RO)" : " "
|
||||
);
|
||||
}
|
||||
printf ("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
|
||||
{
|
||||
short i;
|
||||
vu_long vendor, devid;
|
||||
ulong base = (ulong)addr;
|
||||
|
||||
/* printf("addr = %08lx\n", (unsigned long)addr); */
|
||||
|
||||
/* Reset and Write auto select command: read Manufacturer ID */
|
||||
addr[0] = 0xf0f0f0f0;
|
||||
addr[0x0555] = 0xAAAAAAAA;
|
||||
addr[0x02AA] = 0x55555555;
|
||||
addr[0x0555] = 0x90909090;
|
||||
udelay (1000);
|
||||
|
||||
vendor = addr[0];
|
||||
/* printf("vendor = %08lx\n", vendor); */
|
||||
if (vendor != 0x01010101) {
|
||||
info->size = 0;
|
||||
goto out;
|
||||
}
|
||||
|
||||
devid = addr[1];
|
||||
/* printf("devid = %08lx\n", devid); */
|
||||
|
||||
if ((devid & 0xff) == AMD_ID_F080B) {
|
||||
info->flash_id = (vendor & 0xff) << 16 | AMD_ID_F080B;
|
||||
/* we have 16 sectors with 64KB each x 4 */
|
||||
info->sector_count = 16;
|
||||
info->size = 4 * info->sector_count * 64*1024;
|
||||
}
|
||||
else {
|
||||
info->size = 0;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* sector base address */
|
||||
info->start[i] = base + i * (info->size / info->sector_count);
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
/* D0 = 1 if protected */
|
||||
addr = (volatile unsigned long *)(info->start[i]);
|
||||
info->protect[i] = addr[2] & 1;
|
||||
}
|
||||
|
||||
/* reset command */
|
||||
addr = (vu_long *)info->start[0];
|
||||
|
||||
out:
|
||||
addr[0] = 0xf0f0f0f0;
|
||||
|
||||
return info->size;
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
vu_long *addr = (vu_long*)(info->start[0]);
|
||||
int flag, prot, sect, l_sect;
|
||||
ulong start, now, last;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[0x0555] = 0xAAAAAAAA;
|
||||
addr[0x02AA] = 0x55555555;
|
||||
addr[0x0555] = 0x80808080;
|
||||
addr[0x0555] = 0xAAAAAAAA;
|
||||
addr[0x02AA] = 0x55555555;
|
||||
udelay (100);
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr = (vu_long*)(info->start[sect]);
|
||||
addr[0] = 0x30303030;
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
addr = (vu_long*)(info->start[l_sect]);
|
||||
while ((addr[0] & 0x80808080) != 0x80808080) {
|
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
serial_putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
addr = (volatile unsigned long *)info->start[0];
|
||||
addr[0] = 0xF0F0F0F0; /* reset bank */
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
for (; i<4 && cnt>0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt==0 && i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i=0; i<4; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
return (write_word(info, wp, data));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data)
|
||||
{
|
||||
vu_long *addr = (vu_long*)(info->start[0]);
|
||||
ulong start;
|
||||
int flag;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((vu_long *)dest) & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[0x0555] = 0xAAAAAAAA;
|
||||
addr[0x02AA] = 0x55555555;
|
||||
addr[0x0555] = 0xA0A0A0A0;
|
||||
|
||||
*((vu_long *)dest) = data;
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
|
@ -1,289 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2001
|
||||
* Advent Networks, Inc. <http://www.adventnetworks.com>
|
||||
* Jay Monkman <jtm@smoothsmoothie.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ioports.h>
|
||||
#include <mpc8260.h>
|
||||
|
||||
/*
|
||||
* I/O Port configuration table
|
||||
*
|
||||
* if conf is 1, then that port pin will be configured at boot time
|
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry
|
||||
*/
|
||||
|
||||
const iop_conf_t iop_conf_tab[4][32] = {
|
||||
|
||||
/* Port A configuration */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */
|
||||
/* PA30 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */
|
||||
/* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */
|
||||
/* PA28 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */
|
||||
/* PA27 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */
|
||||
/* PA26 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */
|
||||
/* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
|
||||
/* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
|
||||
/* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
|
||||
/* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
|
||||
/* PA21 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
|
||||
/* PA20 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
|
||||
/* PA19 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
|
||||
/* PA18 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
|
||||
/* PA17 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */
|
||||
/* PA16 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */
|
||||
/* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */
|
||||
/* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */
|
||||
/* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */
|
||||
/* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */
|
||||
/* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */
|
||||
/* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */
|
||||
/* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
|
||||
/* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
|
||||
/* PA7 */ { 1, 0, 0, 1, 0, 0 }, /* PA7 */
|
||||
/* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* PA6 */
|
||||
/* PA5 */ { 1, 0, 0, 1, 0, 0 }, /* PA5 */
|
||||
/* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* PA4 */
|
||||
/* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* PA3 */
|
||||
/* PA2 */ { 1, 0, 0, 1, 0, 0 }, /* PA2 */
|
||||
/* PA1 */ { 1, 0, 0, 1, 0, 0 }, /* PA1 */
|
||||
/* PA0 */ { 1, 0, 0, 1, 0, 0 } /* PA0 */
|
||||
},
|
||||
|
||||
/* Port B configuration */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
|
||||
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
|
||||
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
|
||||
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
|
||||
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
|
||||
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
|
||||
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
|
||||
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
|
||||
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
|
||||
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
|
||||
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
|
||||
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
|
||||
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
|
||||
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
|
||||
/* PB17 */ { 1, 0, 0, 1, 0, 0 }, /* PB17 */
|
||||
/* PB16 */ { 1, 0, 0, 1, 0, 0 }, /* PB16 */
|
||||
/* PB15 */ { 1, 0, 0, 1, 0, 0 }, /* PB15 */
|
||||
/* PB14 */ { 1, 0, 0, 1, 0, 0 }, /* PB14 */
|
||||
/* PB13 */ { 1, 0, 0, 1, 0, 0 }, /* PB13 */
|
||||
/* PB12 */ { 1, 0, 0, 1, 0, 0 }, /* PB12 */
|
||||
/* PB11 */ { 1, 0, 0, 1, 0, 0 }, /* PB11 */
|
||||
/* PB10 */ { 1, 0, 0, 1, 0, 0 }, /* PB10 */
|
||||
/* PB9 */ { 1, 0, 0, 1, 0, 0 }, /* PB9 */
|
||||
/* PB8 */ { 1, 0, 0, 1, 0, 0 }, /* PB8 */
|
||||
/* PB7 */ { 1, 0, 0, 1, 0, 0 }, /* PB7 */
|
||||
/* PB6 */ { 1, 0, 0, 1, 0, 0 }, /* PB6 */
|
||||
/* PB5 */ { 1, 0, 0, 1, 0, 0 }, /* PB5 */
|
||||
/* PB4 */ { 1, 0, 0, 1, 0, 0 }, /* PB4 */
|
||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||
},
|
||||
|
||||
/* Port C */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PC31 */ { 1, 0, 0, 1, 0, 0 }, /* PC31 */
|
||||
/* PC30 */ { 1, 0, 0, 1, 0, 0 }, /* PC30 */
|
||||
/* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
|
||||
/* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* PC28 */
|
||||
/* PC27 */ { 1, 0, 0, 1, 0, 0 }, /* PC27 */
|
||||
/* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* PC26 */
|
||||
/* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* PC25 */
|
||||
/* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* PC24 */
|
||||
/* PC23 */ { 1, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
|
||||
/* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
|
||||
/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
|
||||
/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
|
||||
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
|
||||
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
|
||||
/* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 */
|
||||
/* PC16 */ { 1, 0, 0, 1, 0, 0 }, /* PC16 */
|
||||
/* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* PC15 */
|
||||
/* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
|
||||
/* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* PC13 */
|
||||
/* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* PC12 */
|
||||
/* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* PC11 */
|
||||
/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
|
||||
/* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
|
||||
/* PC8 */ { 1, 0, 0, 1, 0, 0 }, /* PC8 */
|
||||
/* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* PC7 */
|
||||
/* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* PC6 */
|
||||
/* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* PC5 */
|
||||
/* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* PC4 */
|
||||
/* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* PC3 */
|
||||
/* PC2 */ { 1, 0, 0, 1, 0, 1 }, /* ENET FDE */
|
||||
/* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* ENET DSQE */
|
||||
/* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* ENET LBK */
|
||||
},
|
||||
|
||||
/* Port D */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
|
||||
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
|
||||
/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
|
||||
/* PD28 */ { 1, 0, 0, 1, 0, 0 }, /* PD28 */
|
||||
/* PD27 */ { 1, 0, 0, 1, 0, 0 }, /* PD27 */
|
||||
/* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* PD26 */
|
||||
/* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* PD25 */
|
||||
/* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* PD24 */
|
||||
/* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* PD23 */
|
||||
/* PD22 */ { 1, 0, 0, 1, 0, 0 }, /* PD22 */
|
||||
/* PD21 */ { 1, 0, 0, 1, 0, 0 }, /* PD21 */
|
||||
/* PD20 */ { 1, 0, 0, 1, 0, 0 }, /* PD20 */
|
||||
/* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* PD19 */
|
||||
/* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* PD18 */
|
||||
/* PD17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
|
||||
/* PD16 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
|
||||
#if defined(CONFIG_SOFT_I2C)
|
||||
/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
|
||||
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
|
||||
#else
|
||||
#if defined(CONFIG_HARD_I2C)
|
||||
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
||||
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
|
||||
#else /* normal I/O port pins */
|
||||
/* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* I2C SDA */
|
||||
/* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* I2C SCL */
|
||||
#endif
|
||||
#endif
|
||||
/* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* PD13 */
|
||||
/* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* PD12 */
|
||||
/* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* PD11 */
|
||||
/* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* PD10 */
|
||||
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
|
||||
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
|
||||
/* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* PD7 */
|
||||
/* PD6 */ { 1, 0, 0, 1, 0, 1 }, /* PD6 */
|
||||
/* PD5 */ { 1, 0, 0, 1, 0, 1 }, /* PD5 */
|
||||
/* PD4 */ { 1, 0, 0, 1, 0, 1 }, /* PD4 */
|
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||
}
|
||||
};
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
puts ("Board: EST SBC8260\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
phys_size_t initdram (int board_type)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile memctl8260_t *memctl = &immap->im_memctl;
|
||||
volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
|
||||
ulong psdmr = CONFIG_SYS_PSDMR;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
|
||||
*
|
||||
* "At system reset, initialization software must set up the
|
||||
* programmable parameters in the memory controller banks registers
|
||||
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
|
||||
* system software should execute the following initialization sequence
|
||||
* for each SDRAM device.
|
||||
*
|
||||
* 1. Issue a PRECHARGE-ALL-BANKS command
|
||||
* 2. Issue eight CBR REFRESH commands
|
||||
* 3. Issue a MODE-SET command to initialize the mode register
|
||||
*
|
||||
* The initial commands are executed by setting P/LSDMR[OP] and
|
||||
* accessing the SDRAM with a single-byte transaction."
|
||||
*
|
||||
* The appropriate BRx/ORx registers have already been set when we
|
||||
* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
|
||||
*/
|
||||
|
||||
memctl->memc_psrt = CONFIG_SYS_PSRT;
|
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
|
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
|
||||
*ramaddr = c;
|
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
|
||||
for (i = 0; i < 8; i++)
|
||||
*ramaddr = c;
|
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
|
||||
*ramaddr = c;
|
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
||||
*ramaddr = c;
|
||||
|
||||
/* return total ram size */
|
||||
return (CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MISC_INIT_R
|
||||
/* ------------------------------------------------------------------------- */
|
||||
int misc_init_r (void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_LED_BASE
|
||||
uchar ds = *(unsigned char *) (CONFIG_SYS_LED_BASE + 1);
|
||||
uchar ss;
|
||||
uchar tmp[64];
|
||||
int res;
|
||||
|
||||
if ((ds != 0) && (ds != 0xff)) {
|
||||
res = getenv_f("ethaddr", tmp, sizeof (tmp));
|
||||
if (res > 0) {
|
||||
ss = ((ds >> 4) & 0x0f);
|
||||
ss += ss < 0x0a ? '0' : ('a' - 10);
|
||||
tmp[15] = ss;
|
||||
|
||||
ss = (ds & 0x0f);
|
||||
ss += ss < 0x0a ? '0' : ('a' - 10);
|
||||
tmp[16] = ss;
|
||||
|
||||
tmp[17] = '\0';
|
||||
setenv ("ethaddr", tmp);
|
||||
/* set the led to show the address */
|
||||
*((unsigned char *) (CONFIG_SYS_LED_BASE + 1)) = ds;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_SYS_LED_BASE */
|
||||
return (0);
|
||||
}
|
||||
#endif /* CONFIG_MISC_INIT_R */
|
||||
|
|
@ -417,7 +417,6 @@ OXC powerpc mpc824x oxc
|
|||
PN62 powerpc mpc824x pn62
|
||||
Sandpoint8240 powerpc mpc824x sandpoint
|
||||
Sandpoint8245 powerpc mpc824x sandpoint
|
||||
sbc8240 powerpc mpc824x
|
||||
utx8245 powerpc mpc824x
|
||||
debris powerpc mpc824x - etin
|
||||
kvme080 powerpc mpc824x - etin
|
||||
|
|
@ -457,7 +456,6 @@ Rattler8248 powerpc mpc8260 rattler -
|
|||
RPXsuper powerpc mpc8260 rpxsuper
|
||||
rsdproto powerpc mpc8260
|
||||
sacsng powerpc mpc8260
|
||||
sbc8260 powerpc mpc8260
|
||||
ZPC1900 powerpc mpc8260 zpc1900
|
||||
MPC8260ADS powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS
|
||||
MPC8260ADS_33MHz powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@
|
|||
#undef CONFIG_SYS_SBC_BOOT_LOW
|
||||
|
||||
/* What should the base address of the main FLASH be and how big is
|
||||
* it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sbc8260/config.mk
|
||||
* it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE.
|
||||
* The main FLASH is whichever is connected to *CS0. U-Boot expects
|
||||
* this to be the SIMM.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@
|
|||
#define CONFIG_SYS_SBC_BOOT_LOW 1
|
||||
|
||||
/* What should the base address of the main FLASH be and how big is
|
||||
* it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sbc8260/config.mk
|
||||
* it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE.
|
||||
* The main FLASH is whichever is connected to *CS0. U-Boot expects
|
||||
* this to be the SIMM.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -10,8 +10,7 @@
|
|||
* Advent Networks, Inc. <http://www.adventnetworks.com>
|
||||
* Jay Monkman <jtm@smoothsmoothie.com>
|
||||
*
|
||||
* Configuration settings for the WindRiver SBC8260 board.
|
||||
* See http://www.windriver.com/products/html/sbc8260.html
|
||||
* Configuration settings for the SACSng 8260 board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
|
@ -547,7 +546,6 @@
|
|||
*****************************************************************************/
|
||||
|
||||
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
|
||||
#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
|
||||
#define CONFIG_SACSng 1 /* munged for the SACSng */
|
||||
#define CONFIG_CPM2 1 /* Has a CPM2 */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,364 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Configuration settings for the sbc8240 board.
|
||||
*/
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC824X 1
|
||||
#define CONFIG_MPC8240 1
|
||||
#define CONFIG_WRSBC8240 1
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
|
||||
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type \"? or help\" to get on-line help;echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "version;echo;tftpboot $loadaddr $loadfile;bootvx" /* autoboot command */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st " \
|
||||
"e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 " \
|
||||
"tn=sbc8240 o=fei \0" \
|
||||
"env_startaddr=FFF70000\0" \
|
||||
"env_endaddr=FFF7FFFF\0" \
|
||||
"loadfile=vxWorks.st\0" \
|
||||
"loadaddr=0x01000000\0" \
|
||||
"net_load=tftpboot $loadaddr $loadfile\0" \
|
||||
"uboot_startaddr=FFF00000\0" \
|
||||
"uboot_endaddr=FFF3FFFF\0" \
|
||||
"update=tftp $loadaddr /u-boot.bin;" \
|
||||
"protect off $uboot_startaddr $uboot_endaddr;" \
|
||||
"era $uboot_startaddr $uboot_endaddr;" \
|
||||
"cp.b $loadaddr $uboot_startaddr $filesize;" \
|
||||
"protect on $uboot_startaddr $uboot_endaddr\0" \
|
||||
"zapenv=protect off $env_startaddr $env_endaddr;" \
|
||||
"era $env_startaddr $env_endaddr;" \
|
||||
"protect on $env_startaddr $env_endaddr\0"
|
||||
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_BSP
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_SAVEENV
|
||||
#define CONFIG_CMD_FLASH
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SDRAM
|
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
|
||||
#if 1
|
||||
#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
|
||||
#define CONFIG_IPADDR 192.168.193.102
|
||||
#define CONFIG_NETMASK 255.255.255.248
|
||||
#define CONFIG_SERVERIP 192.168.193.99
|
||||
|
||||
#define CONFIG_STATUS_LED /* Status LED enabled */
|
||||
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
|
||||
|
||||
#define STATUS_LED_BIT 0x00000001
|
||||
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
|
||||
#define STATUS_LED_STATE STATUS_LED_BLINKING
|
||||
#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
|
||||
#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/* LEDs */
|
||||
typedef unsigned int led_id_t;
|
||||
|
||||
#define __led_toggle(_msk) \
|
||||
do { \
|
||||
*((volatile char *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
|
||||
} while(0)
|
||||
|
||||
#define __led_set(_msk, _st) \
|
||||
do { \
|
||||
if ((_st)) \
|
||||
*((volatile char *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
|
||||
else \
|
||||
*((volatile char *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
|
||||
} while(0)
|
||||
|
||||
#define __led_init(msk, st) __led_set(msk, st)
|
||||
|
||||
#endif
|
||||
|
||||
#define CONFIG_MISC_INIT_R
|
||||
#define CONFIG_SYS_LED_BASE 0xFFE80000
|
||||
|
||||
/* Print Buffer Size
|
||||
*/
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFFF00000
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
|
||||
|
||||
#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
|
||||
|
||||
/* Maximum amount of RAM.
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
|
||||
|
||||
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#else
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
|
||||
#define CONFIG_SYS_NS16550_CLK 3686400
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 0xFFF80000
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
* For the detail description refer to the MPC8240 user's manual.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
|
||||
|
||||
/* Bit-field values for MCCR1.
|
||||
*/
|
||||
#define CONFIG_SYS_ROMNAL 0
|
||||
#define CONFIG_SYS_ROMFAL 7
|
||||
|
||||
/* Bit-field values for MCCR2.
|
||||
*/
|
||||
#define CONFIG_SYS_REFINT 430 /* Refresh interval */
|
||||
|
||||
/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
|
||||
*/
|
||||
#define CONFIG_SYS_BSTOPRE 192
|
||||
|
||||
/* Bit-field values for MCCR3.
|
||||
*/
|
||||
#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
|
||||
#define CONFIG_SYS_RDLAT 3 /* Data latancy from read command */
|
||||
|
||||
/* Bit-field values for MCCR4.
|
||||
*/
|
||||
#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
|
||||
#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
|
||||
#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
|
||||
#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
|
||||
#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
|
||||
#define CONFIG_SYS_ACTORW 2
|
||||
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
|
||||
|
||||
/* Memory bank settings.
|
||||
* Only bits 20-29 are actually used from these vales to set the
|
||||
* start/end addresses. The upper two bits will always be 0, and the lower
|
||||
* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
|
||||
* address. Refer to the MPC8240 book.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_BANK0_START 0x00000000
|
||||
#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
|
||||
#define CONFIG_SYS_BANK0_ENABLE 1
|
||||
#define CONFIG_SYS_BANK1_START 0x3ff00000
|
||||
#define CONFIG_SYS_BANK1_END 0x3fffffff
|
||||
#define CONFIG_SYS_BANK1_ENABLE 0
|
||||
#define CONFIG_SYS_BANK2_START 0x3ff00000
|
||||
#define CONFIG_SYS_BANK2_END 0x3fffffff
|
||||
#define CONFIG_SYS_BANK2_ENABLE 0
|
||||
#define CONFIG_SYS_BANK3_START 0x3ff00000
|
||||
#define CONFIG_SYS_BANK3_END 0x3fffffff
|
||||
#define CONFIG_SYS_BANK3_ENABLE 0
|
||||
#define CONFIG_SYS_BANK4_START 0x3ff00000
|
||||
#define CONFIG_SYS_BANK4_END 0x3fffffff
|
||||
#define CONFIG_SYS_BANK4_ENABLE 0
|
||||
#define CONFIG_SYS_BANK5_START 0x3ff00000
|
||||
#define CONFIG_SYS_BANK5_END 0x3fffffff
|
||||
#define CONFIG_SYS_BANK5_ENABLE 0
|
||||
#define CONFIG_SYS_BANK6_START 0x3ff00000
|
||||
#define CONFIG_SYS_BANK6_END 0x3fffffff
|
||||
#define CONFIG_SYS_BANK6_ENABLE 0
|
||||
#define CONFIG_SYS_BANK7_START 0x3ff00000
|
||||
#define CONFIG_SYS_BANK7_END 0x3fffffff
|
||||
#define CONFIG_SYS_BANK7_ENABLE 0
|
||||
|
||||
#define CONFIG_SYS_ODCR 0xff
|
||||
|
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
||||
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
|
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
||||
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
|
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* Max number of sectors in one bank */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
|
||||
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
|
||||
|
||||
/* Warining: environment is not EMBEDDED in the U-Boot code.
|
||||
* It's stored in flash separately.
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR 0xFFF70000
|
||||
#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
|
||||
#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_PNP /* we need Plug 'n Play */
|
||||
#define CONFIG_NET_MULTI /* Multi ethernet cards support */
|
||||
#define CONFIG_TULIP
|
||||
#define CONFIG_EEPRO100
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
|
||||
#endif /* __CONFIG_H */
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -308,9 +308,6 @@ void status_led_set (int led, int state);
|
|||
/***** STx XTc ********************************************************/
|
||||
#elif defined(CONFIG_STXXTC)
|
||||
/* XXX empty just to avoid the error */
|
||||
/***** sbc8240 ********************************************************/
|
||||
#elif defined(CONFIG_WRSBC8240)
|
||||
/* XXX empty just to avoid the error */
|
||||
/************************************************************************/
|
||||
#elif defined(CONFIG_NIOS2)
|
||||
/* XXX empty just to avoid the error */
|
||||
|
|
|
|||
Loading…
Reference in a new issue