diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c index 0d37ce83c8..c280ab7d0f 100644 --- a/arch/arm/cpu/arm720t/tegra-common/spl.c +++ b/arch/arm/cpu/arm720t/tegra-common/spl.c @@ -23,105 +23,42 @@ * MA 02111-1307 USA */ #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include #include "cpu.h" +#include #include #include #include #include #include -#include -#include -#include -#include +#include -DECLARE_GLOBAL_DATA_PTR; -/* Define global data structure pointer to it*/ -static gd_t gdata __attribute__ ((section(".data"))); -static bd_t bdata __attribute__ ((section(".data"))); - -inline void hang(void) -{ - puts("### ERROR ### Please RESET the board ###\n"); - for (;;) - ; -} - -void board_init_f(ulong dummy) -{ - board_init_uart_f(); - - /* Initialize periph GPIOs */ - gpio_early_init_uart(); - - /* - * We call relocate_code() with relocation target same as the - * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting - * skipped. Instead, only .bss initialization will happen. That's - * all we need - */ - debug(">>board_init_f()\n"); - relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE); -} - -/* This requires UART clocks to be enabled */ -static void preloader_console_init(void) -{ - const char *u_boot_rev = U_BOOT_VERSION; - - gd = &gdata; - gd->bd = &bdata; - gd->flags |= GD_FLG_RELOC; - gd->baudrate = CONFIG_BAUDRATE; - - serial_init(); /* serial communications setup */ - - gd->have_console = 1; - - /* Avoid a second "U-Boot" coming from this string */ - u_boot_rev = &u_boot_rev[7]; - - printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE, - U_BOOT_TIME); -} - -void board_init_r(gd_t *id, ulong dummy) +void spl_board_init(void) { struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; /* enable JTAG */ writel(0xC0, &pmt->pmt_cfg_ctl); - debug(">>spl:board_init_r()\n"); + board_init_uart_f(); - mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START, - CONFIG_SYS_SPL_MALLOC_SIZE); - -#ifdef CONFIG_SPL_BOARD_INIT - spl_board_init(); -#endif + /* Initialize periph GPIOs */ + gpio_early_init_uart(); clock_early_init(); - serial_init(); preloader_console_init(); - - start_cpu((u32)CONFIG_SYS_TEXT_BASE); - halt_avp(); - /* not reached */ } -int board_usb_init(const void *blob) +u32 spl_boot_device(void) { - return 0; + return BOOT_DEVICE_RAM; +} + +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + debug("image entry point: 0x%X\n", spl_image->entry_point); + + start_cpu((u32)spl_image->entry_point); + halt_avp(); } diff --git a/arch/arm/include/asm/arch-tegra20/spl.h b/arch/arm/include/asm/arch-tegra20/spl.h new file mode 100644 index 0000000000..5e453c5cc7 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra20/spl.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2012 + * NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#define BOOT_DEVICE_RAM 1 + +#endif diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 5b048e0094..15bd9bb146 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -169,6 +169,7 @@ #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_TEXT_BASE 0x0010c000 +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ @@ -186,6 +187,9 @@ /* Defines for SPL */ #define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_TEXT_BASE 0x00108000 #define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \