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armv8/gic: Fix GIC v2 initialization
Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable interrupts to the primary CPU. This fixes issues seen after booting a Linux kernel from U-Boot. Suggested-by: Marc Zyngier <marc.zyngier@arm.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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1 changed files with 9 additions and 1 deletions
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@ -46,11 +46,19 @@ ENTRY(gic_init_secure)
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ldr w9, [x0, GICD_TYPER]
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ldr w9, [x0, GICD_TYPER]
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and w10, w9, #0x1f /* ITLinesNumber */
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and w10, w9, #0x1f /* ITLinesNumber */
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cbz w10, 1f /* No SPIs */
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cbz w10, 1f /* No SPIs */
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add x11, x0, (GICD_IGROUPRn + 4)
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add x11, x0, GICD_IGROUPRn
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mov w9, #~0 /* Config SPIs as Grp1 */
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mov w9, #~0 /* Config SPIs as Grp1 */
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str w9, [x11], #0x4
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0: str w9, [x11], #0x4
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0: str w9, [x11], #0x4
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sub w10, w10, #0x1
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sub w10, w10, #0x1
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cbnz w10, 0b
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cbnz w10, 0b
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ldr x1, =GICC_BASE /* GICC_CTLR */
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mov w0, #3 /* EnableGrp0 | EnableGrp1 */
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str w0, [x1]
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mov w0, #1 << 7 /* allow NS access to GICC_PMR */
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str w0, [x1, #4] /* GICC_PMR */
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#endif
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#endif
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1:
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1:
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ret
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ret
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