mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
Merge tag '20200316-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next
i2c: for next - i2c-gpio: make it possible to run deblock sequence on driver probe - i2c-gpio: add clock stretching support - updates the Designware I2C driver for high speed mode, fix a bug and add some improvements. - add DM support for memory based bootcounter driver
This commit is contained in:
Tom Rini
commit
b180e32ea3
12 changed files with 315 additions and 109 deletions
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@ -16,6 +16,10 @@ Optional:
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The resulting transfer speed can be adjusted by setting the delay[us]
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between gpio-toggle operations. Speed [Hz] = 1000000 / 4 * udelay[us],
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It not defined, then default is 5us (~50KHz).
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* i2c-gpio,deblock
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Run deblocking sequence when the driver gets probed.
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* i2c-gpio,scl-output-only;
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Set if SCL is an output only
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Example:
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21
doc/device-tree-bindings/misc/bootcounter.txt
Normal file
21
doc/device-tree-bindings/misc/bootcounter.txt
Normal file
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@ -0,0 +1,21 @@
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U-Boot bootcounter Devicetree Binding
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=====================================
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The device tree node describes the U-Boot bootcounter
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memory based device binding.
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Required properties :
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- compatible : "u-boot,bootcount";
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- single-word : set this, if you have only one word space
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for storing the bootcounter.
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Example
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-------
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MPC83xx based board:
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bootcount@0x13ff8 {
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compatible = "u-boot,bootcount";
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reg = <0x13ff8 0x08>;
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};
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@ -106,6 +106,13 @@ config DM_BOOTCOUNT_I2C_EEPROM
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pointing to the underlying i2c eeprom device) and an optional 'offset'
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property are supported.
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config BOOTCOUNT_MEM
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bool "Support memory based bootcounter"
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help
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Enabling Memory based bootcount, typically in a SoC register which
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is not cleared on softreset.
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compatible = "u-boot,bootcount";
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endmenu
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endif
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@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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obj-$(CONFIG_BOOTCOUNT_GENERIC) += bootcount.o
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obj-$(CONFIG_BOOTCOUNT_MEM) += bootcount.o
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obj-$(CONFIG_BOOTCOUNT_AT91) += bootcount_at91.o
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obj-$(CONFIG_BOOTCOUNT_AM33XX) += bootcount_davinci.o
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obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o
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@ -8,6 +8,7 @@
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#include <cpu_func.h>
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#include <linux/compiler.h>
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#if !defined(CONFIG_DM_BOOTCOUNT)
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/* Now implement the generic default functions */
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__weak void bootcount_store(ulong a)
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{
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@ -49,3 +50,94 @@ __weak ulong bootcount_load(void)
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return raw_bootcount_load(reg);
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#endif /* defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD) */
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}
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#else
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#include <dm.h>
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/*
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* struct bootcount_mem_priv - private bootcount mem driver data
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*
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* @base: base address used for bootcounter
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* @singleword: if true use only one 32 bit word for bootcounter
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*/
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struct bootcount_mem_priv {
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phys_addr_t base;
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bool singleword;
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};
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static int bootcount_mem_get(struct udevice *dev, u32 *a)
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{
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struct bootcount_mem_priv *priv = dev_get_priv(dev);
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void *reg = (void *)priv->base;
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u32 magic = CONFIG_SYS_BOOTCOUNT_MAGIC;
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if (priv->singleword) {
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u32 tmp = raw_bootcount_load(reg);
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if ((tmp & 0xffff0000) != (magic & 0xffff0000))
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return -ENODEV;
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*a = (tmp & 0x0000ffff);
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} else {
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if (raw_bootcount_load(reg + 4) != magic)
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return -ENODEV;
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*a = raw_bootcount_load(reg);
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}
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return 0;
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};
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static int bootcount_mem_set(struct udevice *dev, const u32 a)
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{
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struct bootcount_mem_priv *priv = dev_get_priv(dev);
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void *reg = (void *)priv->base;
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u32 magic = CONFIG_SYS_BOOTCOUNT_MAGIC;
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uintptr_t flush_start = rounddown(priv->base,
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CONFIG_SYS_CACHELINE_SIZE);
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uintptr_t flush_end;
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if (priv->singleword) {
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raw_bootcount_store(reg, (magic & 0xffff0000) | a);
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flush_end = roundup(priv->base + 4,
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CONFIG_SYS_CACHELINE_SIZE);
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} else {
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raw_bootcount_store(reg, a);
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raw_bootcount_store(reg + 4, magic);
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flush_end = roundup(priv->base + 8,
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CONFIG_SYS_CACHELINE_SIZE);
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}
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flush_dcache_range(flush_start, flush_end);
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return 0;
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};
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static const struct bootcount_ops bootcount_mem_ops = {
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.get = bootcount_mem_get,
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.set = bootcount_mem_set,
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};
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static int bootcount_mem_probe(struct udevice *dev)
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{
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struct bootcount_mem_priv *priv = dev_get_priv(dev);
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priv->base = (phys_addr_t)dev_read_addr(dev);
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if (dev_read_bool(dev, "single-word"))
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priv->singleword = true;
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return 0;
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}
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static const struct udevice_id bootcount_mem_ids[] = {
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{ .compatible = "u-boot,bootcount" },
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{ }
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};
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U_BOOT_DRIVER(bootcount_mem) = {
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.name = "bootcount-mem",
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.id = UCLASS_BOOTCOUNT,
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.priv_auto_alloc_size = sizeof(struct bootcount_mem_priv),
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.probe = bootcount_mem_probe,
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.of_match = bootcount_mem_ids,
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.ops = &bootcount_mem_ops,
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};
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#endif
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@ -203,14 +203,16 @@ static int calc_bus_speed(struct dw_i2c *priv, int speed, ulong bus_clk,
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const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
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struct i2c_regs *regs = priv->regs;
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enum i2c_speed_mode i2c_spd;
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u32 comp_param1;
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int spk_cnt;
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int ret;
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comp_param1 = readl(®s->comp_param1);
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if (priv)
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scl_sda_cfg = priv->scl_sda_cfg;
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/* Allow high speed if there is no config, or the config allows it */
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if (speed >= I2C_SPEED_HIGH_RATE &&
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(!scl_sda_cfg || scl_sda_cfg->has_high_speed))
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if (speed >= I2C_SPEED_HIGH_RATE)
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i2c_spd = IC_SPEED_MODE_HIGH;
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else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
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i2c_spd = IC_SPEED_MODE_FAST_PLUS;
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@ -219,6 +221,13 @@ static int calc_bus_speed(struct dw_i2c *priv, int speed, ulong bus_clk,
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else
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i2c_spd = IC_SPEED_MODE_STANDARD;
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/* Check is high speed possible and fall back to fast mode if not */
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if (i2c_spd == IC_SPEED_MODE_HIGH) {
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if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
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!= DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH)
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i2c_spd = IC_SPEED_MODE_FAST;
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}
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/* Get the proper spike-suppression count based on target speed */
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if (!priv || !priv->has_spk_cnt)
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spk_cnt = 0;
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@ -231,6 +240,9 @@ static int calc_bus_speed(struct dw_i2c *priv, int speed, ulong bus_clk,
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if (i2c_spd == IC_SPEED_MODE_STANDARD) {
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config->scl_hcnt = scl_sda_cfg->ss_hcnt;
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config->scl_lcnt = scl_sda_cfg->ss_lcnt;
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} else if (i2c_spd == IC_SPEED_MODE_HIGH) {
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config->scl_hcnt = scl_sda_cfg->hs_hcnt;
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config->scl_lcnt = scl_sda_cfg->hs_lcnt;
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} else {
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config->scl_hcnt = scl_sda_cfg->fs_hcnt;
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config->scl_lcnt = scl_sda_cfg->fs_lcnt;
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@ -274,7 +286,7 @@ static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
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switch (config.speed_mode) {
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case IC_SPEED_MODE_HIGH:
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cntl |= IC_CON_SPD_SS;
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cntl |= IC_CON_SPD_HS;
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writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
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writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
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break;
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@ -138,22 +138,27 @@ struct i2c_regs {
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#define IC_STATUS_TFNF 0x0002
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#define IC_STATUS_ACT 0x0001
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#define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3))
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#define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK (BIT(2) | BIT(3))
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/**
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* struct dw_scl_sda_cfg - I2C timing configuration
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*
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* @has_high_speed: Support high speed (3.4Mbps)
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* @ss_hcnt: Standard speed high time in ns
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* @fs_hcnt: Fast speed high time in ns
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* @hs_hcnt: High speed high time in ns
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* @ss_lcnt: Standard speed low time in ns
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* @fs_lcnt: Fast speed low time in ns
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* @hs_lcnt: High speed low time in ns
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* @sda_hold: SDA hold time
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*/
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struct dw_scl_sda_cfg {
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bool has_high_speed;
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u32 ss_hcnt;
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u32 fs_hcnt;
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u32 hs_hcnt;
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u32 ss_lcnt;
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u32 fs_lcnt;
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u32 hs_lcnt;
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u32 sda_hold;
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};
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@ -32,23 +32,50 @@ struct i2c_gpio_bus {
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int udelay;
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/* sda, scl */
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struct gpio_desc gpios[PIN_COUNT];
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int (*get_sda)(struct i2c_gpio_bus *bus);
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void (*set_sda)(struct i2c_gpio_bus *bus, int bit);
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void (*set_scl)(struct i2c_gpio_bus *bus, int bit);
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};
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static int i2c_gpio_sda_get(struct gpio_desc *sda)
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static int i2c_gpio_sda_get(struct i2c_gpio_bus *bus)
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{
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struct gpio_desc *sda = &bus->gpios[PIN_SDA];
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return dm_gpio_get_value(sda);
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}
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static void i2c_gpio_sda_set(struct gpio_desc *sda, int bit)
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static void i2c_gpio_sda_set(struct i2c_gpio_bus *bus, int bit)
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{
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struct gpio_desc *sda = &bus->gpios[PIN_SDA];
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if (bit)
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dm_gpio_set_dir_flags(sda, GPIOD_IS_IN);
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else
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dm_gpio_set_dir_flags(sda, GPIOD_IS_OUT);
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}
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static void i2c_gpio_scl_set(struct gpio_desc *scl, int bit)
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static void i2c_gpio_scl_set(struct i2c_gpio_bus *bus, int bit)
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{
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struct gpio_desc *scl = &bus->gpios[PIN_SCL];
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int count = 0;
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if (bit) {
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dm_gpio_set_dir_flags(scl, GPIOD_IS_IN);
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while (!dm_gpio_get_value(scl) && count++ < 100000)
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udelay(1);
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if (!dm_gpio_get_value(scl))
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pr_err("timeout waiting on slave to release scl\n");
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} else {
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dm_gpio_set_dir_flags(scl, GPIOD_IS_OUT);
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}
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}
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/* variant for output only gpios which cannot support clock stretching */
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static void i2c_gpio_scl_set_output_only(struct i2c_gpio_bus *bus, int bit)
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{
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struct gpio_desc *scl = &bus->gpios[PIN_SCL];
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ulong flags = GPIOD_IS_OUT;
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if (bit)
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@ -56,65 +83,60 @@ static void i2c_gpio_scl_set(struct gpio_desc *scl, int bit)
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dm_gpio_set_dir_flags(scl, flags);
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}
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static void i2c_gpio_write_bit(struct gpio_desc *scl, struct gpio_desc *sda,
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int delay, uchar bit)
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static void i2c_gpio_write_bit(struct i2c_gpio_bus *bus, int delay, uchar bit)
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{
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i2c_gpio_scl_set(scl, 0);
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bus->set_scl(bus, 0);
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udelay(delay);
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i2c_gpio_sda_set(sda, bit);
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bus->set_sda(bus, bit);
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udelay(delay);
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i2c_gpio_scl_set(scl, 1);
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bus->set_scl(bus, 1);
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udelay(2 * delay);
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}
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static int i2c_gpio_read_bit(struct gpio_desc *scl, struct gpio_desc *sda,
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int delay)
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static int i2c_gpio_read_bit(struct i2c_gpio_bus *bus, int delay)
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{
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int value;
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i2c_gpio_scl_set(scl, 1);
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bus->set_scl(bus, 1);
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udelay(delay);
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value = i2c_gpio_sda_get(sda);
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value = bus->get_sda(bus);
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udelay(delay);
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i2c_gpio_scl_set(scl, 0);
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bus->set_scl(bus, 0);
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udelay(2 * delay);
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return value;
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}
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/* START: High -> Low on SDA while SCL is High */
|
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static void i2c_gpio_send_start(struct gpio_desc *scl, struct gpio_desc *sda,
|
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int delay)
|
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static void i2c_gpio_send_start(struct i2c_gpio_bus *bus, int delay)
|
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{
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udelay(delay);
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i2c_gpio_sda_set(sda, 1);
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bus->set_sda(bus, 1);
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udelay(delay);
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i2c_gpio_scl_set(scl, 1);
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bus->set_scl(bus, 1);
|
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udelay(delay);
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i2c_gpio_sda_set(sda, 0);
|
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bus->set_sda(bus, 0);
|
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udelay(delay);
|
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}
|
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|
||||
/* STOP: Low -> High on SDA while SCL is High */
|
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static void i2c_gpio_send_stop(struct gpio_desc *scl, struct gpio_desc *sda,
|
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int delay)
|
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static void i2c_gpio_send_stop(struct i2c_gpio_bus *bus, int delay)
|
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{
|
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i2c_gpio_scl_set(scl, 0);
|
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bus->set_scl(bus, 0);
|
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udelay(delay);
|
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i2c_gpio_sda_set(sda, 0);
|
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bus->set_sda(bus, 0);
|
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udelay(delay);
|
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i2c_gpio_scl_set(scl, 1);
|
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bus->set_scl(bus, 1);
|
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udelay(delay);
|
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i2c_gpio_sda_set(sda, 1);
|
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bus->set_sda(bus, 1);
|
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udelay(delay);
|
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}
|
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|
||||
/* ack should be I2C_ACK or I2C_NOACK */
|
||||
static void i2c_gpio_send_ack(struct gpio_desc *scl, struct gpio_desc *sda,
|
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int delay, int ack)
|
||||
static void i2c_gpio_send_ack(struct i2c_gpio_bus *bus, int delay, int ack)
|
||||
{
|
||||
i2c_gpio_write_bit(scl, sda, delay, ack);
|
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i2c_gpio_scl_set(scl, 0);
|
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i2c_gpio_write_bit(bus, delay, ack);
|
||||
bus->set_scl(bus, 0);
|
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udelay(delay);
|
||||
}
|
||||
|
||||
|
|
@ -123,44 +145,41 @@ static void i2c_gpio_send_ack(struct gpio_desc *scl, struct gpio_desc *sda,
|
|||
* to clock any confused device back into an idle state. Also send a
|
||||
* <stop> at the end of the sequence for belts & suspenders.
|
||||
*/
|
||||
static void i2c_gpio_send_reset(struct gpio_desc *scl, struct gpio_desc *sda,
|
||||
int delay)
|
||||
static void i2c_gpio_send_reset(struct i2c_gpio_bus *bus, int delay)
|
||||
{
|
||||
int j;
|
||||
|
||||
for (j = 0; j < 9; j++)
|
||||
i2c_gpio_write_bit(scl, sda, delay, 1);
|
||||
i2c_gpio_write_bit(bus, delay, 1);
|
||||
|
||||
i2c_gpio_send_stop(scl, sda, delay);
|
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i2c_gpio_send_stop(bus, delay);
|
||||
}
|
||||
|
||||
/* Set sda high with low clock, before reading slave data */
|
||||
static void i2c_gpio_sda_high(struct gpio_desc *scl, struct gpio_desc *sda,
|
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int delay)
|
||||
static void i2c_gpio_sda_high(struct i2c_gpio_bus *bus, int delay)
|
||||
{
|
||||
i2c_gpio_scl_set(scl, 0);
|
||||
bus->set_scl(bus, 0);
|
||||
udelay(delay);
|
||||
i2c_gpio_sda_set(sda, 1);
|
||||
bus->set_sda(bus, 1);
|
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udelay(delay);
|
||||
}
|
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|
||||
/* Send 8 bits and look for an acknowledgement */
|
||||
static int i2c_gpio_write_byte(struct gpio_desc *scl, struct gpio_desc *sda,
|
||||
int delay, uchar data)
|
||||
static int i2c_gpio_write_byte(struct i2c_gpio_bus *bus, int delay, uchar data)
|
||||
{
|
||||
int j;
|
||||
int nack;
|
||||
|
||||
for (j = 0; j < 8; j++) {
|
||||
i2c_gpio_write_bit(scl, sda, delay, data & 0x80);
|
||||
i2c_gpio_write_bit(bus, delay, data & 0x80);
|
||||
data <<= 1;
|
||||
}
|
||||
|
||||
udelay(delay);
|
||||
|
||||
/* Look for an <ACK>(negative logic) and return it */
|
||||
i2c_gpio_sda_high(scl, sda, delay);
|
||||
nack = i2c_gpio_read_bit(scl, sda, delay);
|
||||
i2c_gpio_sda_high(bus, delay);
|
||||
nack = i2c_gpio_read_bit(bus, delay);
|
||||
|
||||
return nack; /* not a nack is an ack */
|
||||
}
|
||||
|
|
@ -169,31 +188,29 @@ static int i2c_gpio_write_byte(struct gpio_desc *scl, struct gpio_desc *sda,
|
|||
* if ack == I2C_ACK, ACK the byte so can continue reading, else
|
||||
* send I2C_NOACK to end the read.
|
||||
*/
|
||||
static uchar i2c_gpio_read_byte(struct gpio_desc *scl, struct gpio_desc *sda,
|
||||
int delay, int ack)
|
||||
static uchar i2c_gpio_read_byte(struct i2c_gpio_bus *bus, int delay, int ack)
|
||||
{
|
||||
int data;
|
||||
int j;
|
||||
|
||||
i2c_gpio_sda_high(scl, sda, delay);
|
||||
i2c_gpio_sda_high(bus, delay);
|
||||
data = 0;
|
||||
for (j = 0; j < 8; j++) {
|
||||
data <<= 1;
|
||||
data |= i2c_gpio_read_bit(scl, sda, delay);
|
||||
data |= i2c_gpio_read_bit(bus, delay);
|
||||
}
|
||||
i2c_gpio_send_ack(scl, sda, delay, ack);
|
||||
i2c_gpio_send_ack(bus, delay, ack);
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
/* send start and the slave chip address */
|
||||
int i2c_send_slave_addr(struct gpio_desc *scl, struct gpio_desc *sda, int delay,
|
||||
uchar chip)
|
||||
int i2c_send_slave_addr(struct i2c_gpio_bus *bus, int delay, uchar chip)
|
||||
{
|
||||
i2c_gpio_send_start(scl, sda, delay);
|
||||
i2c_gpio_send_start(bus, delay);
|
||||
|
||||
if (i2c_gpio_write_byte(scl, sda, delay, chip)) {
|
||||
i2c_gpio_send_stop(scl, sda, delay);
|
||||
if (i2c_gpio_write_byte(bus, delay, chip)) {
|
||||
i2c_gpio_send_stop(bus, delay);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
|
|
@ -204,29 +221,27 @@ static int i2c_gpio_write_data(struct i2c_gpio_bus *bus, uchar chip,
|
|||
uchar *buffer, int len,
|
||||
bool end_with_repeated_start)
|
||||
{
|
||||
struct gpio_desc *scl = &bus->gpios[PIN_SCL];
|
||||
struct gpio_desc *sda = &bus->gpios[PIN_SDA];
|
||||
unsigned int delay = bus->udelay;
|
||||
int failures = 0;
|
||||
|
||||
debug("%s: chip %x buffer %p len %d\n", __func__, chip, buffer, len);
|
||||
|
||||
if (i2c_send_slave_addr(scl, sda, delay, chip << 1)) {
|
||||
if (i2c_send_slave_addr(bus, delay, chip << 1)) {
|
||||
debug("i2c_write, no chip responded %02X\n", chip);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
while (len-- > 0) {
|
||||
if (i2c_gpio_write_byte(scl, sda, delay, *buffer++))
|
||||
if (i2c_gpio_write_byte(bus, delay, *buffer++))
|
||||
failures++;
|
||||
}
|
||||
|
||||
if (!end_with_repeated_start) {
|
||||
i2c_gpio_send_stop(scl, sda, delay);
|
||||
i2c_gpio_send_stop(bus, delay);
|
||||
return failures;
|
||||
}
|
||||
|
||||
if (i2c_send_slave_addr(scl, sda, delay, (chip << 1) | 0x1)) {
|
||||
if (i2c_send_slave_addr(bus, delay, (chip << 1) | 0x1)) {
|
||||
debug("i2c_write, no chip responded %02X\n", chip);
|
||||
return -EIO;
|
||||
}
|
||||
|
|
@ -237,16 +252,14 @@ static int i2c_gpio_write_data(struct i2c_gpio_bus *bus, uchar chip,
|
|||
static int i2c_gpio_read_data(struct i2c_gpio_bus *bus, uchar chip,
|
||||
uchar *buffer, int len)
|
||||
{
|
||||
struct gpio_desc *scl = &bus->gpios[PIN_SCL];
|
||||
struct gpio_desc *sda = &bus->gpios[PIN_SDA];
|
||||
unsigned int delay = bus->udelay;
|
||||
|
||||
debug("%s: chip %x buffer: %p len %d\n", __func__, chip, buffer, len);
|
||||
|
||||
while (len-- > 0)
|
||||
*buffer++ = i2c_gpio_read_byte(scl, sda, delay, len == 0);
|
||||
*buffer++ = i2c_gpio_read_byte(bus, delay, len == 0);
|
||||
|
||||
i2c_gpio_send_stop(scl, sda, delay);
|
||||
i2c_gpio_send_stop(bus, delay);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -277,14 +290,12 @@ static int i2c_gpio_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
|
|||
static int i2c_gpio_probe(struct udevice *dev, uint chip, uint chip_flags)
|
||||
{
|
||||
struct i2c_gpio_bus *bus = dev_get_priv(dev);
|
||||
struct gpio_desc *scl = &bus->gpios[PIN_SCL];
|
||||
struct gpio_desc *sda = &bus->gpios[PIN_SDA];
|
||||
unsigned int delay = bus->udelay;
|
||||
int ret;
|
||||
|
||||
i2c_gpio_send_start(scl, sda, delay);
|
||||
ret = i2c_gpio_write_byte(scl, sda, delay, (chip << 1) | 0);
|
||||
i2c_gpio_send_stop(scl, sda, delay);
|
||||
i2c_gpio_send_start(bus, delay);
|
||||
ret = i2c_gpio_write_byte(bus, delay, (chip << 1) | 0);
|
||||
i2c_gpio_send_stop(bus, delay);
|
||||
|
||||
debug("%s: bus: %d (%s) chip: %x flags: %x ret: %d\n",
|
||||
__func__, dev->seq, dev->name, chip, chip_flags, ret);
|
||||
|
|
@ -295,12 +306,25 @@ static int i2c_gpio_probe(struct udevice *dev, uint chip, uint chip_flags)
|
|||
static int i2c_gpio_set_bus_speed(struct udevice *dev, unsigned int speed_hz)
|
||||
{
|
||||
struct i2c_gpio_bus *bus = dev_get_priv(dev);
|
||||
struct gpio_desc *scl = &bus->gpios[PIN_SCL];
|
||||
struct gpio_desc *sda = &bus->gpios[PIN_SDA];
|
||||
|
||||
bus->udelay = 1000000 / (speed_hz << 2);
|
||||
|
||||
i2c_gpio_send_reset(scl, sda, bus->udelay);
|
||||
i2c_gpio_send_reset(bus, bus->udelay);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int i2c_gpio_drv_probe(struct udevice *dev)
|
||||
{
|
||||
if (dev_read_bool(dev, "i2c-gpio,deblock")) {
|
||||
/* @200kHz 9 clocks = 44us, 62us is ok */
|
||||
const unsigned int DELAY_ABORT_SEQ = 62;
|
||||
struct i2c_gpio_bus *bus = dev_get_priv(dev);
|
||||
|
||||
return i2c_deblock_gpio_loop(&bus->gpios[PIN_SDA],
|
||||
&bus->gpios[PIN_SCL],
|
||||
16, 5, DELAY_ABORT_SEQ);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -320,6 +344,13 @@ static int i2c_gpio_ofdata_to_platdata(struct udevice *dev)
|
|||
bus->udelay = fdtdec_get_int(blob, node, "i2c-gpio,delay-us",
|
||||
DEFAULT_UDELAY);
|
||||
|
||||
bus->get_sda = i2c_gpio_sda_get;
|
||||
bus->set_sda = i2c_gpio_sda_set;
|
||||
if (fdtdec_get_bool(blob, node, "i2c-gpio,scl-output-only"))
|
||||
bus->set_scl = i2c_gpio_scl_set_output_only;
|
||||
else
|
||||
bus->set_scl = i2c_gpio_scl_set;
|
||||
|
||||
return 0;
|
||||
error:
|
||||
pr_err("Can't get %s gpios! Error: %d", dev->name, ret);
|
||||
|
|
@ -341,6 +372,7 @@ U_BOOT_DRIVER(i2c_gpio) = {
|
|||
.name = "i2c-gpio",
|
||||
.id = UCLASS_I2C,
|
||||
.of_match = i2c_gpio_ids,
|
||||
.probe = i2c_gpio_drv_probe,
|
||||
.ofdata_to_platdata = i2c_gpio_ofdata_to_platdata,
|
||||
.priv_auto_alloc_size = sizeof(struct i2c_gpio_bus),
|
||||
.ops = &i2c_gpio_ops,
|
||||
|
|
|
|||
|
|
@ -501,35 +501,53 @@ static int i2c_gpio_get_pin(struct gpio_desc *pin)
|
|||
return dm_gpio_get_value(pin);
|
||||
}
|
||||
|
||||
static int i2c_deblock_gpio_loop(struct gpio_desc *sda_pin,
|
||||
struct gpio_desc *scl_pin)
|
||||
int i2c_deblock_gpio_loop(struct gpio_desc *sda_pin,
|
||||
struct gpio_desc *scl_pin,
|
||||
unsigned int scl_count,
|
||||
unsigned int start_count,
|
||||
unsigned int delay)
|
||||
{
|
||||
int counter = 9;
|
||||
int ret = 0;
|
||||
int i, ret = -EREMOTEIO;
|
||||
|
||||
i2c_gpio_set_pin(sda_pin, 1);
|
||||
i2c_gpio_set_pin(scl_pin, 1);
|
||||
udelay(5);
|
||||
udelay(delay);
|
||||
|
||||
/* Toggle SCL until slave release SDA */
|
||||
while (counter-- >= 0) {
|
||||
while (scl_count-- >= 0) {
|
||||
i2c_gpio_set_pin(scl_pin, 1);
|
||||
udelay(5);
|
||||
udelay(delay);
|
||||
i2c_gpio_set_pin(scl_pin, 0);
|
||||
udelay(5);
|
||||
if (i2c_gpio_get_pin(sda_pin))
|
||||
udelay(delay);
|
||||
if (i2c_gpio_get_pin(sda_pin)) {
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!ret && start_count) {
|
||||
for (i = 0; i < start_count; i++) {
|
||||
/* Send start condition */
|
||||
udelay(delay);
|
||||
i2c_gpio_set_pin(sda_pin, 1);
|
||||
udelay(delay);
|
||||
i2c_gpio_set_pin(scl_pin, 1);
|
||||
udelay(delay);
|
||||
i2c_gpio_set_pin(sda_pin, 0);
|
||||
udelay(delay);
|
||||
i2c_gpio_set_pin(scl_pin, 0);
|
||||
}
|
||||
}
|
||||
|
||||
/* Then, send I2C stop */
|
||||
i2c_gpio_set_pin(sda_pin, 0);
|
||||
udelay(5);
|
||||
udelay(delay);
|
||||
|
||||
i2c_gpio_set_pin(scl_pin, 1);
|
||||
udelay(5);
|
||||
udelay(delay);
|
||||
|
||||
i2c_gpio_set_pin(sda_pin, 1);
|
||||
udelay(5);
|
||||
udelay(delay);
|
||||
|
||||
if (!i2c_gpio_get_pin(sda_pin) || !i2c_gpio_get_pin(scl_pin))
|
||||
ret = -EREMOTEIO;
|
||||
|
|
@ -561,7 +579,7 @@ static int i2c_deblock_gpio(struct udevice *bus)
|
|||
goto out_no_pinctrl;
|
||||
}
|
||||
|
||||
ret0 = i2c_deblock_gpio_loop(&gpios[PIN_SDA], &gpios[PIN_SCL]);
|
||||
ret0 = i2c_deblock_gpio_loop(&gpios[PIN_SDA], &gpios[PIN_SCL], 9, 0, 5);
|
||||
|
||||
ret = pinctrl_select_state(bus, "default");
|
||||
if (ret) {
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
|
||||
struct i2c_eeprom_drv_data {
|
||||
u32 size; /* size in bytes */
|
||||
u32 pagewidth; /* pagesize = 2^pagewidth */
|
||||
u32 pagesize; /* page size in bytes */
|
||||
u32 addr_offset_mask; /* bits in addr used for offset overflow */
|
||||
u32 offset_len; /* size in bytes of offset */
|
||||
};
|
||||
|
|
@ -99,13 +99,11 @@ static int i2c_eeprom_std_ofdata_to_platdata(struct udevice *dev)
|
|||
u32 pagesize;
|
||||
u32 size;
|
||||
|
||||
if (dev_read_u32(dev, "pagesize", &pagesize) == 0) {
|
||||
if (dev_read_u32(dev, "pagesize", &pagesize) == 0)
|
||||
priv->pagesize = pagesize;
|
||||
} else {
|
||||
else
|
||||
/* 6 bit -> page size of up to 2^63 (should be sufficient) */
|
||||
priv->pagewidth = data->pagewidth;
|
||||
priv->pagesize = (1 << priv->pagewidth);
|
||||
}
|
||||
priv->pagesize = data->pagesize;
|
||||
|
||||
if (dev_read_u32(dev, "size", &size) == 0)
|
||||
priv->size = size;
|
||||
|
|
@ -158,98 +156,98 @@ static int i2c_eeprom_std_probe(struct udevice *dev)
|
|||
|
||||
static const struct i2c_eeprom_drv_data eeprom_data = {
|
||||
.size = 0,
|
||||
.pagewidth = 0,
|
||||
.pagesize = 1,
|
||||
.addr_offset_mask = 0,
|
||||
.offset_len = 1,
|
||||
};
|
||||
|
||||
static const struct i2c_eeprom_drv_data mc24aa02e48_data = {
|
||||
.size = 256,
|
||||
.pagewidth = 3,
|
||||
.pagesize = 8,
|
||||
.addr_offset_mask = 0,
|
||||
.offset_len = 1,
|
||||
};
|
||||
|
||||
static const struct i2c_eeprom_drv_data atmel24c01a_data = {
|
||||
.size = 128,
|
||||
.pagewidth = 3,
|
||||
.pagesize = 8,
|
||||
.addr_offset_mask = 0,
|
||||
.offset_len = 1,
|
||||
};
|
||||
|
||||
static const struct i2c_eeprom_drv_data atmel24c02_data = {
|
||||
.size = 256,
|
||||
.pagewidth = 3,
|
||||
.pagesize = 8,
|
||||
.addr_offset_mask = 0,
|
||||
.offset_len = 1,
|
||||
};
|
||||
|
||||
static const struct i2c_eeprom_drv_data atmel24c04_data = {
|
||||
.size = 512,
|
||||
.pagewidth = 4,
|
||||
.pagesize = 16,
|
||||
.addr_offset_mask = 0x1,
|
||||
.offset_len = 1,
|
||||
};
|
||||
|
||||
static const struct i2c_eeprom_drv_data atmel24c08_data = {
|
||||
.size = 1024,
|
||||
.pagewidth = 4,
|
||||
.pagesize = 16,
|
||||
.addr_offset_mask = 0x3,
|
||||
.offset_len = 1,
|
||||
};
|
||||
|
||||
static const struct i2c_eeprom_drv_data atmel24c08a_data = {
|
||||
.size = 1024,
|
||||
.pagewidth = 4,
|
||||
.pagesize = 16,
|
||||
.addr_offset_mask = 0x3,
|
||||
.offset_len = 1,
|
||||
};
|
||||
|
||||
static const struct i2c_eeprom_drv_data atmel24c16a_data = {
|
||||
.size = 2048,
|
||||
.pagewidth = 4,
|
||||
.pagesize = 16,
|
||||
.addr_offset_mask = 0x7,
|
||||
.offset_len = 1,
|
||||
};
|
||||
|
||||
static const struct i2c_eeprom_drv_data atmel24mac402_data = {
|
||||
.size = 256,
|
||||
.pagewidth = 4,
|
||||
.pagesize = 16,
|
||||
.addr_offset_mask = 0,
|
||||
.offset_len = 1,
|
||||
};
|
||||
|
||||
static const struct i2c_eeprom_drv_data atmel24c32_data = {
|
||||
.size = 4096,
|
||||
.pagewidth = 5,
|
||||
.pagesize = 32,
|
||||
.addr_offset_mask = 0,
|
||||
.offset_len = 2,
|
||||
};
|
||||
|
||||
static const struct i2c_eeprom_drv_data atmel24c64_data = {
|
||||
.size = 8192,
|
||||
.pagewidth = 5,
|
||||
.pagesize = 32,
|
||||
.addr_offset_mask = 0,
|
||||
.offset_len = 2,
|
||||
};
|
||||
|
||||
static const struct i2c_eeprom_drv_data atmel24c128_data = {
|
||||
.size = 16384,
|
||||
.pagewidth = 6,
|
||||
.pagesize = 64,
|
||||
.addr_offset_mask = 0,
|
||||
.offset_len = 2,
|
||||
};
|
||||
|
||||
static const struct i2c_eeprom_drv_data atmel24c256_data = {
|
||||
.size = 32768,
|
||||
.pagewidth = 6,
|
||||
.pagesize = 64,
|
||||
.addr_offset_mask = 0,
|
||||
.offset_len = 2,
|
||||
};
|
||||
|
||||
static const struct i2c_eeprom_drv_data atmel24c512_data = {
|
||||
.size = 65536,
|
||||
.pagewidth = 6,
|
||||
.pagesize = 64,
|
||||
.addr_offset_mask = 0,
|
||||
.offset_len = 2,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -330,6 +330,24 @@ uint i2c_get_chip_addr_offset_mask(struct udevice *dev);
|
|||
*/
|
||||
int i2c_deblock(struct udevice *bus);
|
||||
|
||||
/**
|
||||
* i2c_deblock_gpio_loop() - recover a bus from an unknown state by toggling SDA/SCL
|
||||
*
|
||||
* This is the inner logic used for toggling I2C SDA/SCL lines as GPIOs
|
||||
* for deblocking the I2C bus.
|
||||
*
|
||||
* @sda_pin: SDA GPIO
|
||||
* @scl_pin: SCL GPIO
|
||||
* @scl_count: Number of SCL clock cycles generated to deblock SDA
|
||||
* @start_count:Number of I2C start conditions sent after deblocking SDA
|
||||
* @delay: Delay between SCL clock line changes
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
struct gpio_desc;
|
||||
int i2c_deblock_gpio_loop(struct gpio_desc *sda_pin, struct gpio_desc *scl_pin,
|
||||
unsigned int scl_count, unsigned int start_count,
|
||||
unsigned int delay);
|
||||
|
||||
/**
|
||||
* struct dm_i2c_ops - driver operations for I2C uclass
|
||||
*
|
||||
|
|
|
|||
|
|
@ -16,8 +16,6 @@ struct i2c_eeprom_ops {
|
|||
struct i2c_eeprom {
|
||||
/* The EEPROM's page size in byte */
|
||||
unsigned long pagesize;
|
||||
/* The EEPROM's page width in bits (pagesize = 2^pagewidth) */
|
||||
unsigned pagewidth;
|
||||
/* The EEPROM's capacity in bytes */
|
||||
unsigned long size;
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue