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x86: coreboot: Look for DBG2 UART in SPL too

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If coreboot does not set up sysinfo for the UART, SPL currently hangs.
Use the DBG2 technique there as well. This allows coreboot64 to boot from
coreboot even if the console info is missing from sysinfo

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2023-09-19 21:00:07 -06:00 • committed by Bin Meng
parent 0c45c76ced
commit b1350636e6
2 changed files with 2 additions and 1 deletions
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1
configs/coreboot64_defconfig
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@ -54,4 +54,5 @@ CONFIG_SYS_64BIT_LBA=y
CONFIG_SOUND=y
CONFIG_SOUND_I8254=y
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_SPL_ACPI=y
# CONFIG_GZIP is not set

2
drivers/serial/Kconfig
View file

@ -672,7 +672,7 @@ config COREBOOT_SERIAL
config COREBOOT_SERIAL_FROM_DBG2
bool "Obtain UART from ACPI tables"
depends on COREBOOT_SERIAL
default y if !SPL
default y
help
Select this to try to find a DBG2 record in the ACPI tables, in the
event that coreboot does not provide information about the UART in the