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Merge branch 'for-1.3.0'

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This commit is contained in:
Jon Loeliger 2007-11-07 14:16:49 -06:00
commit b0a41a1184
5 changed files with 12 additions and 5 deletions
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5
board/freescale/common/pixis.c
View file

@ -207,13 +207,16 @@ void read_from_px_regs_altbank(int set)
out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
}
#ifndef CFG_PIXIS_VBOOT_MASK
#define CFG_PIXIS_VBOOT_MASK 0x40
#endif
void set_altbank(void)
{
u8 tmp;
tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
tmp ^= 0x40;
tmp ^= CFG_PIXIS_VBOOT_MASK;
out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
}

4
cpu/mpc86xx/cpu.c
View file

@ -131,7 +131,7 @@ checkcpu(void)
static inline void
soft_restart(unsigned long addr)
{
#ifndef CONFIG_MPC8641HPCN
#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
/*
* SRR0 has system reset vector, SRR1 has default MSR value
@ -159,7 +159,7 @@ soft_restart(unsigned long addr)
void
do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#ifndef CONFIG_MPC8641HPCN
#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
#ifdef CFG_RESET_ADDRESS
ulong addr = CFG_RESET_ADDRESS;

6
cpu/mpc86xx/spd_sdram.c
View file

@ -1270,10 +1270,12 @@ spd_sdram(void)
debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
}
debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2);
#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n",
memsize_ddr1, memsize_ddr2);
debug("\nMemory size of DDR1 = 0x%08lx\n", memsize_ddr1);
/*
* If neither DDR controller is enabled return 0.

1
include/configs/MPC8544DS.h
View file

@ -198,6 +198,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
/* define to use L1 as initial stack */

1
include/configs/MPC8641HPCN.h
View file

@ -201,6 +201,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */