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https://github.com/AsahiLinux/u-boot
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Merge branch 'for-1.3.0'
This commit is contained in:
commit
b0a41a1184
5 changed files with 12 additions and 5 deletions
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@ -207,13 +207,16 @@ void read_from_px_regs_altbank(int set)
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out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
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}
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#ifndef CFG_PIXIS_VBOOT_MASK
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#define CFG_PIXIS_VBOOT_MASK 0x40
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#endif
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void set_altbank(void)
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
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tmp ^= 0x40;
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tmp ^= CFG_PIXIS_VBOOT_MASK;
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out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
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}
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@ -131,7 +131,7 @@ checkcpu(void)
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static inline void
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soft_restart(unsigned long addr)
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{
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#ifndef CONFIG_MPC8641HPCN
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#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
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/*
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* SRR0 has system reset vector, SRR1 has default MSR value
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@ -159,7 +159,7 @@ soft_restart(unsigned long addr)
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void
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do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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#ifndef CONFIG_MPC8641HPCN
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#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
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#ifdef CFG_RESET_ADDRESS
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ulong addr = CFG_RESET_ADDRESS;
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@ -1270,10 +1270,12 @@ spd_sdram(void)
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debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
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debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
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}
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debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2);
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#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
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debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n",
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memsize_ddr1, memsize_ddr2);
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debug("\nMemory size of DDR1 = 0x%08lx\n", memsize_ddr1);
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/*
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* If neither DDR controller is enabled return 0.
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@ -198,6 +198,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
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#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
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#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
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#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
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/* define to use L1 as initial stack */
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@ -201,6 +201,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
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#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
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#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
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#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
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#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
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#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
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