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ram: k3-ddrss: do not touch ctrl regs during training
During LPDDR initialization we will loop through a series of frequency changes in order to train at the various operating frequencies. During this training, accessing the DRAM_CLASS bitfield could happen during a frequency change and cause the read to hang. Store the DRAM type into the main structure to avoid multiple readings while the independent phy is training. Signed-off-by: Bryan Brattlof <bb@ti.com>
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1 changed files with 4 additions and 7 deletions
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@ -138,6 +138,7 @@ struct k3_ddrss_desc {
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u32 ddr_freq1;
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u32 ddr_freq2;
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u32 ddr_fhs_cnt;
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u32 dram_class;
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struct udevice *vtt_supply;
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u32 instance;
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lpddr4_obj *driverdt;
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@ -243,14 +244,11 @@ static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss)
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static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
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{
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u32 dram_class;
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struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
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debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
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dram_class = k3_lpddr4_read_ddr_type(pd);
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switch (dram_class) {
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switch (ddrss->dram_class) {
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case DENALI_CTL_0_DRAM_CLASS_DDR4:
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break;
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case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
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@ -263,13 +261,12 @@ static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
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static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss)
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{
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u32 dram_class;
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int ret;
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lpddr4_privatedata *pd = &ddrss->pd;
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dram_class = k3_lpddr4_read_ddr_type(pd);
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ddrss->dram_class = k3_lpddr4_read_ddr_type(pd);
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switch (dram_class) {
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switch (ddrss->dram_class) {
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case DENALI_CTL_0_DRAM_CLASS_DDR4:
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/* Set to ddr_freq1 from DT for DDR4 */
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ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
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