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Merge branch '2022-07-25-assorted-platform-updates'

Browse source 
- Assorted TI, Apple, Snapdragon and Xen updates.
This commit is contained in:
Tom Rini 2022-07-25 16:40:43 -04:00
commit af18c32973
103 changed files with 1862 additions and 231 deletions
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1
MAINTAINERS
View file

@ -1364,6 +1364,7 @@ F: arch/arm/mach-k3/config_secure.mk
F: configs/am335x_hs_evm_defconfig
F: configs/am335x_hs_evm_uart_defconfig
F: configs/am43xx_hs_evm_defconfig
F: configs/am43xx_hs_evm_qspi_defconfig
F: configs/am57xx_hs_evm_defconfig
F: configs/am57xx_hs_evm_usb_defconfig
F: configs/dra7xx_hs_evm_defconfig

15
arch/arm/Kconfig
View file

@ -2149,21 +2149,6 @@ config TI_SECURE_DEVICE
authenticated) and the code. See the doc/README.ti-secure
file for further details.
if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
config ISW_ENTRY_ADDR
hex "Address in memory or XIP address of bootloader entry point"
default 0x402F4000 if AM43XX
default 0x402F0400 if AM33XX
default 0x40301350 if OMAP54XX
help
After any reset, the boot ROM searches the boot media for a valid
boot image. For non-XIP devices, the ROM then copies the image into
internal memory. For all boot modes, after the ROM processes the
boot image it eventually computes the entry point address depending
on the device type (secure/non-secure), boot media (xip/non-xip) and
image headers.
endif
config SYS_KWD_CONFIG
string "kwbimage config file path"
depends on ARCH_KIRKWOOD || ARCH_MVEBU

3
arch/arm/dts/Makefile
View file

@ -505,6 +505,7 @@ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb
dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb
dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
@ -1193,7 +1194,7 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp15xx-dhcor-avenger96.dtb \
stm32mp15xx-dhcor-drc-compact.dtb
dtb-$(CONFIG_SOC_K3_AM6) += \
dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am654-base-board.dtb \
k3-am654-r5-base-board.dtb \
k3-am65-iot2050-spl.dtb \

9
arch/arm/dts/dragonboard410c.dts
View file

@ -137,9 +137,14 @@
};
};
spmi@200f000 {
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x200f800 0x200 0x2400000 0x400000 0x2c00000 0x400000>;
reg = <0x0200f000 0x001000>,
<0x02400000 0x400000>,
<0x02c00000 0x400000>,
<0x03800000 0x200000>,
<0x0200a000 0x002100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
#address-cells = <0x1>;
#size-cells = <0x1>;
pmic0: pm8916@0 {

11
arch/arm/dts/dragonboard820c.dts
View file

@ -93,11 +93,14 @@
clock-frequency = <200000000>;
};
spmi@400f000 {
spmi_bus: spmi@400f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x400f800 0x200>,
<0x4400000 0x400000>,
<0x4c00000 0x400000>;
reg = <0x0400f000 0x1000>,
<0x04400000 0x800000>,
<0x04c00000 0x800000>,
<0x05800000 0x200000>,
<0x0400a000 0x002100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
#address-cells = <0x1>;
#size-cells = <0x1>;

37
arch/arm/dts/dragonboard845c-uboot.dtsi Normal file
View file

@ -0,0 +1,37 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot addition to handle Qualcomm Robotics RB3 Development Platform
* (dragonboard845c) pins
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
/
{
soc {
u-boot,dm-pre-reloc;
serial@a84000 {
u-boot,dm-pre-reloc;
};
clock-controller@100000 {
u-boot,dm-pre-reloc;
};
pinctrl_north@3900000 {
u-boot,dm-pre-reloc;
};
};
};
&pm8998_pon {
key_vol_down {
gpios = <&pm8998_pon 1 0>;
label = "key_vol_down";
};
key_power {
gpios = <&pm8998_pon 0 0>;
label = "key_power";
};
};

44
arch/arm/dts/dragonboard845c.dts Normal file
View file

@ -0,0 +1,44 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm Robotics RB3 Development (dragonboard845c) board device
* tree source
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
/dts-v1/;
#include "sdm845.dtsi"
/ {
model = "Thundercomm Dragonboard 845c";
compatible = "thundercomm,db845c", "qcom,sdm845";
#address-cells = <2>;
#size-cells = <2>;
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &debug_uart;
};
memory {
device_type = "memory";
reg = <0 0x80000000 0 0xfdfa0000>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
soc: soc {
serial@a84000 {
status = "okay";
};
};
};
#include "dragonboard845c-uboot.dtsi"

16
arch/arm/dts/k3-am625-r5-sk.dts
View file

@ -79,6 +79,15 @@
ti,secure-host;
};
&cbass_mcu {
mcu_esm: esm@4100000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x4100000 0x0 0x1000>;
ti,esm-pins = <0>, <1>, <2>, <85>;
u-boot,dm-spl;
};
};
&cbass_main {
sa3_secproxy: secproxy@44880000 {
u-boot,dm-spl;
@ -96,6 +105,13 @@
mbox-names = "tx", "rx", "boot_notify";
u-boot,dm-spl;
};
main_esm: esm@420000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x420000 0x0 0x1000>;
ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
u-boot,dm-spl;
};
};
&mcu_pmx0 {

1
arch/arm/dts/k3-am64-ddr.dtsi
View file

@ -768,7 +768,6 @@
DDRSS_PI_319_DATA
DDRSS_PI_320_DATA
DDRSS_PI_321_DATA
DDRSS_PI_321_DATA
DDRSS_PI_322_DATA
DDRSS_PI_323_DATA
DDRSS_PI_324_DATA

2
arch/arm/dts/mt7622-bananapi-bpi-r64.dts
View file

@ -182,8 +182,6 @@
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};

2
arch/arm/dts/mt7622-rfb.dts
View file

@ -189,8 +189,6 @@
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};

24
arch/arm/dts/qcs404-evb-uboot.dtsi Normal file
View file

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot addition to handle QCS404 EVB pre-relocation devices
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
/ {
soc {
u-boot,dm-pre-reloc;
pinctrl_north@1300000 {
u-boot,dm-pre-reloc;
};
clock-controller@1800000 {
u-boot,dm-pre-reloc;
};
serial@78b1000 {
u-boot,dm-pre-reloc;
};
};
};

81
arch/arm/dts/qcs404-evb.dts Normal file
View file

@ -0,0 +1,81 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm QCS404 based evaluation board device tree source
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
/dts-v1/;
#include "skeleton64.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
/ {
model = "Qualcomm Technologies, Inc. QCS404 EVB";
compatible = "qcom,qcs404-evb", "qcom,qcs404";
#address-cells = <0x2>;
#size-cells = <0x2>;
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &debug_uart;
};
memory {
device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
soc {
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0x0 0x0 0x0 0xffffffff>;
compatible = "simple-bus";
pinctrl_north@1300000 {
compatible = "qcom,tlmm-qcs404";
reg = <0x1300000 0x200000>;
blsp1_uart2: uart {
pins = "GPIO_17", "GPIO_18";
function = "blsp_uart2";
};
};
gcc: clock-controller@1800000 {
compatible = "qcom,gcc-qcs404";
reg = <0x1800000 0x80000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
debug_uart: serial@78b1000 {
compatible = "qcom,msm-uartdm-v1.4";
reg = <0x78b1000 0x200>;
clock = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
bit-rate = <0xFF>;
pinctrl-names = "uart";
pinctrl-0 = <&blsp1_uart2>;
};
sdhci@7804000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x7804000 0x1000 0x7805000 0x1000>;
clock = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>;
bus-width = <0x8>;
index = <0x0>;
non-removable;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
};
};
};
#include "qcs404-evb-uboot.dtsi"

8
arch/arm/dts/sdm845.dtsi
View file

@ -8,6 +8,7 @@
/dts-v1/;
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include "skeleton64.dtsi"
/ {
@ -18,7 +19,6 @@
compatible = "simple-bus";
gcc: clock-controller@100000 {
u-boot,dm-pre-reloc;
compatible = "qcom,gcc-sdm845";
reg = <0x100000 0x1f0000>;
#clock-cells = <1>;
@ -27,7 +27,6 @@
};
gpio_north: gpio_north@3900000 {
u-boot,dm-pre-reloc;
#gpio-cells = <2>;
compatible = "qcom,sdm845-pinctrl";
reg = <0x3900000 0x400000>;
@ -38,7 +37,6 @@
};
tlmm_north: pinctrl_north@3900000 {
u-boot,dm-pre-reloc;
compatible = "qcom,tlmm-sdm845";
reg = <0x3900000 0x400000>;
gpio-count = <150>;
@ -49,7 +47,7 @@
/* DEBUG UART */
qup_uart9: qup-uart9-default {
pins = "GPIO_4", "GPIO_5";
function = "gpio";
function = "qup9";
};
};
@ -58,7 +56,7 @@
reg = <0xa84000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk";
clocks = <&gcc 0x58>;
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart9>;
qcom,wrapper-core = <0x8a>;

18
arch/arm/dts/starqltechn-uboot.dtsi
View file

@ -16,16 +16,14 @@
serial@a84000 {
u-boot,dm-pre-reloc;
};
gcc {
clock-controller@100000 {
u-boot,dm-pre-reloc;
};
gpio_north@3900000 {
u-boot,dm-pre-reloc;
};
pinctrl@3900000 {
u-boot,dm-pre-reloc;
};
clock-controller@100000 {
u-boot,dm-pre-reloc;
};
gpio_north@3900000 {
u-boot,dm-pre-reloc;
};
pinctrl_north@3900000 {
u-boot,dm-pre-reloc;
};
};
};

2
arch/arm/dts/starqltechn.dts
View file

@ -48,7 +48,7 @@
status = "okay";
};
pinctrl@3900000 {
pinctrl_north@3900000 {
muic_i2c: muic_i2c {
pins = "GPIO_33", "GPIO_34";
drive-strength = <0x2>;

5
arch/arm/mach-apple/board.c
View file

@ -16,7 +16,7 @@
DECLARE_GLOBAL_DATA_PTR;
/* Apple M1 */
/* Apple M1/M2 */
static struct mm_region t8103_mem_map[] = {
{
@ -376,7 +376,8 @@ void build_mem_map(void)
fdt_size_t size;
int i;
if (of_machine_is_compatible("apple,t8103"))
if (of_machine_is_compatible("apple,t8103") ||
of_machine_is_compatible("apple,t8112"))
mem_map = t8103_mem_map;
else if (of_machine_is_compatible("apple,t6000"))
mem_map = t6000_mem_map;

5
arch/arm/mach-davinci/Makefile
View file

@ -7,14 +7,9 @@
obj-y += cpu.o misc.o timer.o psc.o pinmux.o reset.o
obj-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o
obj-$(CONFIG_SOC_DM355) += dm355.o
obj-$(CONFIG_SOC_DM365) += dm365.o
obj-$(CONFIG_SOC_DM644X) += dm644x.o
obj-$(CONFIG_SOC_DM646X) += dm646x.o
obj-$(CONFIG_SOC_DA850) += da850_pinmux.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
obj-$(CONFIG_SOC_DM365) += dm365_lowlevel.o
obj-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o
endif

20
arch/arm/mach-k3/Kconfig
View file

@ -4,8 +4,8 @@ choice
prompt "Texas Instruments' K3 based SoC select"
optional
config SOC_K3_AM6
bool "TI's K3 based AM6 SoC Family Support"
config SOC_K3_AM654
bool "TI's K3 based AM654 SoC Family Support"
config SOC_K3_J721E
bool "TI's K3 based J721E SoC Family Support"
@ -26,7 +26,7 @@ config SYS_SOC
config SYS_K3_NON_SECURE_MSRAM_SIZE
hex
default 0x80000 if SOC_K3_AM6
default 0x80000 if SOC_K3_AM654
default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2
default 0x1c0000 if SOC_K3_AM642
default 0x3c000 if SOC_K3_AM625
@ -38,7 +38,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
hex
default 0x58000 if SOC_K3_AM6
default 0x58000 if SOC_K3_AM654
default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2
default 0x180000 if SOC_K3_AM642
default 0x38000 if SOC_K3_AM625
@ -48,21 +48,21 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
config SYS_K3_MCU_SCRATCHPAD_BASE
hex
default 0x40280000 if SOC_K3_AM6
default 0x40280000 if SOC_K3_AM654
default 0x40280000 if SOC_K3_J721E || SOC_K3_J721S2
help
Describes the base address of MCU Scratchpad RAM.
config SYS_K3_MCU_SCRATCHPAD_SIZE
hex
default 0x200 if SOC_K3_AM6
default 0x200 if SOC_K3_AM654
default 0x200 if SOC_K3_J721E || SOC_K3_J721S2
help
Describes the size of MCU Scratchpad RAM.
config SYS_K3_BOOT_PARAM_TABLE_INDEX
hex
default 0x41c7fbfc if SOC_K3_AM6
default 0x41c7fbfc if SOC_K3_AM654
default 0x41cffbfc if SOC_K3_J721E
default 0x41cfdbfc if SOC_K3_J721S2
default 0x701bebfc if SOC_K3_AM642
@ -176,6 +176,12 @@ config K3_DM_FW
bootloader, it makes RM and PM services not being available
during R5 SPL execution time.
config K3_X509_SWRV
int "SWRV for X509 certificate used for boot images"
default 1
help
SWRV for X509 certificate used for boot images
source "board/ti/am65x/Kconfig"
source "board/ti/am64x/Kconfig"
source "board/ti/am62x/Kconfig"

13
arch/arm/mach-k3/Makefile
View file

@ -3,16 +3,19 @@
# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o j721s2/
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
obj-$(CONFIG_SOC_K3_AM625) += am625_init.o am62x/
obj-$(CONFIG_SOC_K3_J721E) += j721e/ j7200/
obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
obj-$(CONFIG_SOC_K3_AM625) += am62x/
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
obj-$(CONFIG_ARM64) += cache.o
ifeq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_SOC_K3_AM654) += am654_init.o
obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
endif
obj-y += common.o

27
arch/arm/mach-k3/am625_init.c
View file

@ -15,8 +15,6 @@
#include <dm/uclass-internal.h>
#include <dm/pinctrl.h>
#if defined(CONFIG_SPL_BUILD)
/*
* This uninitialized global variable would normal end up in the .bss section,
* but the .bss is cleared between writing and reading this variable, so move
@ -64,6 +62,15 @@ static void ctrl_mmr_unlock(void)
mmr_unlock(PADCFG_MMR1_BASE, 1);
}
static __maybe_unused void enable_mcu_esm_reset(void)
{
/* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */
u32 stat = readl(CTRLMMR_MCU_RST_CTRL);
stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK;
writel(stat, CTRLMMR_MCU_RST_CTRL);
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
@ -142,6 +149,20 @@ void board_init_f(ulong dummy)
/* Output System Firmware version info */
k3_sysfw_print_ver();
if (IS_ENABLED(CONFIG_ESM_K3)) {
/* Probe/configure ESM0 */
ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev);
if (ret)
printf("esm main init failed: %d\n", ret);
/* Probe/configure MCUESM */
ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev);
if (ret)
printf("esm mcu init failed: %d\n", ret);
enable_mcu_esm_reset();
}
#if defined(CONFIG_K3_AM64_DDRSS)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret)
@ -267,5 +288,3 @@ u32 spl_boot_device(void)
return bootmedia;
}
#endif /* CONFIG_SPL_BUILD */

2
arch/arm/mach-k3/am642_init.c
View file

@ -23,7 +23,6 @@
#include <mmc.h>
#include <dm/root.h>
#if defined(CONFIG_SPL_BUILD)
#define MCU_CTRL_MMR0_BASE 0x04500000
#define CTRLMMR_MCU_RST_CTRL 0x04518170
@ -348,7 +347,6 @@ u32 spl_boot_device(void)
else
return __get_backup_bootmedia(devstat);
}
#endif
#if defined(CONFIG_SYS_K3_SPL_ATF)

6
arch/arm/mach-k3/am6_init.c → arch/arm/mach-k3/am654_init.c
View file

@ -26,9 +26,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_K3_LOAD_SYSFW
#ifdef CONFIG_TI_SECURE_DEVICE
struct fwl_data main_cbass_fwls[] = {
{ "MMCSD1_CFG", 2057, 1 },
{ "MMCSD0_CFG", 2058, 1 },
@ -45,7 +43,6 @@ struct fwl_data main_cbass_fwls[] = {
{ "MCU_CPSW0", 1220, 1 },
};
#endif
#endif
static void ctrl_mmr_unlock(void)
{
@ -238,10 +235,8 @@ void board_init_f(ulong dummy)
preloader_console_init();
/* Disable ROM configured firewalls right after loading sysfw */
#ifdef CONFIG_TI_SECURE_DEVICE
remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
#endif
#else
/* Prepare console output */
preloader_console_init();
@ -359,7 +354,6 @@ u32 spl_boot_device(void)
else
return __get_backup_bootmedia(devstat);
}
#endif
#ifdef CONFIG_SYS_K3_SPL_ATF

6
arch/arm/mach-k3/arm64-mmu.c
View file

@ -13,7 +13,7 @@
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#ifdef CONFIG_SOC_K3_AM6
#ifdef CONFIG_SOC_K3_AM654
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
@ -64,7 +64,7 @@ struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
};
struct mm_region *mem_map = am654_mem_map;
#endif /* CONFIG_SOC_K3_AM6 */
#endif /* CONFIG_SOC_K3_AM654 */
#ifdef CONFIG_SOC_K3_J721E
@ -222,7 +222,7 @@ struct mm_region *mem_map = j721s2_mem_map;
#endif /* CONFIG_SOC_K3_J721S2 */
#if (CONFIG_IS_ENABLED(SOC_K3_AM642) || CONFIG_IS_ENABLED(SOC_K3_AM625))
#if defined(CONFIG_SOC_K3_AM642) || defined(CONFIG_SOC_K3_AM625)
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)

13
arch/arm/mach-k3/config.mk
View file

@ -28,6 +28,17 @@ else
KEY=$(patsubst "%",$(srctree)/%,$(CONFIG_SYS_K3_KEY))
endif
# X509 SWRV default
SWRV = $(CONFIG_K3_X509_SWRV)
# On HS use SECDEV provided software revision or warn if not available
ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/keys/swrv.txt),)
SWRV= $(shell cat $(TI_SECURE_DEV_PKG)/keys/swrv.txt)
else
$(warning "WARNING: Software revision file not found. Default may not work on HS hardware.")
endif
endif
# tiboot3.bin is mandated by ROM and ROM only supports R5 boot.
# So restrict tiboot3.bin creation for CPU_V7R.
ifdef CONFIG_CPU_V7R
@ -42,7 +53,7 @@ image_check: $(obj)/u-boot-spl.bin FORCE
tiboot3.bin: image_check FORCE
$(srctree)/tools/k3_gen_x509_cert.sh -c 16 -b $(obj)/u-boot-spl.bin \
-o $@ -l $(CONFIG_SPL_TEXT_BASE) -k $(KEY)
-o $@ -l $(CONFIG_SPL_TEXT_BASE) -r $(SWRV) -k $(KEY)
INPUTS-y += tiboot3.bin
endif

3
arch/arm/mach-k3/include/mach/am62_hardware.h
View file

@ -29,6 +29,7 @@
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13)
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK (~BIT(17))
/* Primary Bootmode MMC Config macros */
#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4
@ -67,6 +68,8 @@
#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058)
#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3)
#define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170)
#define ROM_ENTENDED_BOOT_DATA_INFO 0x43c3f1e0
/* Use Last 2K as Scratch pad */

2
arch/arm/mach-k3/include/mach/hardware.h
View file

@ -6,7 +6,7 @@
#ifndef _ASM_ARCH_HARDWARE_H_
#define _ASM_ARCH_HARDWARE_H_
#ifdef CONFIG_SOC_K3_AM6
#ifdef CONFIG_SOC_K3_AM654
#include "am6_hardware.h"
#endif

2
arch/arm/mach-k3/include/mach/spl.h
View file

@ -6,7 +6,7 @@
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_ARCH_SPL_H_
#ifdef CONFIG_SOC_K3_AM6
#ifdef CONFIG_SOC_K3_AM654
#include "am6_spl.h"
#endif

6
arch/arm/mach-k3/j721e_init.c
View file

@ -24,9 +24,7 @@
#include <mmc.h>
#include <remoteproc.h>
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_K3_LOAD_SYSFW
#ifdef CONFIG_TI_SECURE_DEVICE
struct fwl_data cbass_hc_cfg0_fwls[] = {
{ "PCIE0_CFG", 2560, 8 },
{ "PCIE1_CFG", 2561, 8 },
@ -64,7 +62,6 @@ struct fwl_data cbass_hc_cfg0_fwls[] = {
{ "WKUP_CTRL_MMR0", 131, 16 },
};
#endif
#endif
static void ctrl_mmr_unlock(void)
{
@ -255,7 +252,6 @@ void board_init_f(ulong dummy)
preloader_console_init();
/* Disable ROM configured firewalls right after loading sysfw */
#ifdef CONFIG_TI_SECURE_DEVICE
remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
@ -263,7 +259,6 @@ void board_init_f(ulong dummy)
remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
#endif
#else
/* Prepare console output */
preloader_console_init();
@ -384,7 +379,6 @@ u32 spl_boot_device(void)
else
return __get_backup_bootmedia(main_devstat);
}
#endif
#ifdef CONFIG_SYS_K3_SPL_ATF

3
arch/arm/mach-k3/j721s2_init.c
View file

@ -22,8 +22,6 @@
#include <mmc.h>
#include <remoteproc.h>
#ifdef CONFIG_SPL_BUILD
static void ctrl_mmr_unlock(void)
{
/* Unlock all WKUP_CTRL_MMR0 module registers */
@ -255,7 +253,6 @@ u32 spl_boot_device(void)
else
return __get_backup_bootmedia(main_devstat);
}
#endif
#define J721S2_DEV_MCU_RTI0 295
#define J721S2_DEV_MCU_RTI1 296

4
arch/arm/mach-omap2/config_secure.mk
View file

@ -6,11 +6,11 @@ ifneq ($(TI_SECURE_DEV_PKG),)
ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),)
ifneq ($(CONFIG_SPL_BUILD),)
cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
$(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
$(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_SPL_TEXT_BASE) \
$(if $(KBUILD_VERBOSE:1=), >/dev/null)
else
cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
$(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
$(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_SYS_TEXT_BASE) \
$(if $(KBUILD_VERBOSE:1=), >/dev/null)
endif
else

25
arch/arm/mach-snapdragon/Kconfig
View file

@ -44,6 +44,19 @@ config TARGET_DRAGONBOARD820C
- 3GiB RAM
- 32GiB UFS drive
config TARGET_DRAGONBOARD845C
bool "96Boards Dragonboard 845C"
help
Support for 96Boards Dragonboard 845C aka Robotics RB3 Development
Platform. This board complies with 96Boards Open Platform
Specifications. Features:
- Qualcomm Snapdragon SDA845 SoC
- 4GiB RAM
- 64GiB UFS drive
select MISC_INIT_R
select SDM845
select DM_ETH if NET
config TARGET_STARQLTECHN
bool "Samsung S9 SM-G9600(starqltechn)"
help
@ -56,10 +69,22 @@ config TARGET_STARQLTECHN
select SDM845
select DM_ETH if NET
config TARGET_QCS404EVB
bool "Qualcomm Technologies, Inc. QCS404 EVB"
select LINUX_KERNEL_IMAGE_HEADER
help
Support for Qualcomm Technologies, Inc. QCS404 evaluation board.
Features:
- Qualcomm Snapdragon QCS404 SoC
- 1GiB RAM
- 8GiB eMMC, uSD slot
endchoice
source "board/qualcomm/dragonboard410c/Kconfig"
source "board/qualcomm/dragonboard820c/Kconfig"
source "board/qualcomm/dragonboard845c/Kconfig"
source "board/samsung/starqltechn/Kconfig"
source "board/qualcomm/qcs404-evb/Kconfig"
endif

3
arch/arm/mach-snapdragon/Makefile
View file

@ -15,4 +15,7 @@ obj-y += dram.o
obj-y += pinctrl-snapdragon.o
obj-y += pinctrl-apq8016.o
obj-y += pinctrl-apq8096.o
obj-y += pinctrl-qcs404.o
obj-$(CONFIG_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o
obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o

79
arch/arm/mach-snapdragon/clock-qcs404.c Normal file
View file

@ -0,0 +1,79 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Clock drivers for Qualcomm QCS404
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include "clock-snapdragon.h"
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
/* GPLL0 clock control registers */
#define GPLL0_STATUS_ACTIVE BIT(31)
static struct vote_clk gcc_blsp1_ahb_clk = {
.cbcr_reg = BLSP1_AHB_CBCR,
.ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
.vote_bit = BIT(10) | BIT(5) | BIT(4),
};
static const struct bcr_regs uart2_regs = {
.cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
.cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
.M = BLSP1_UART2_APPS_M,
.N = BLSP1_UART2_APPS_N,
.D = BLSP1_UART2_APPS_D,
};
static const struct bcr_regs sdc_regs = {
.cfg_rcgr = SDCC_CFG_RCGR(1),
.cmd_rcgr = SDCC_CMD_RCGR(1),
.M = SDCC_M(1),
.N = SDCC_N(1),
.D = SDCC_D(1),
};
static struct pll_vote_clk gpll0_vote_clk = {
.status = GPLL0_STATUS,
.status_bit = GPLL0_STATUS_ACTIVE,
.ena_vote = APCS_GPLL_ENA_VOTE,
.vote_bit = BIT(0),
};
ulong msm_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
case GCC_BLSP1_UART2_APPS_CLK:
/* UART: 115200 */
clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
CFG_CLK_SRC_CXO);
clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
break;
case GCC_BLSP1_AHB_CLK:
clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
break;
case GCC_SDCC1_APPS_CLK:
/* SDCC1: 200MHz */
clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0,
CFG_CLK_SRC_GPLL0);
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
break;
case GCC_SDCC1_AHB_CLK:
clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
break;
default:
return 0;
}
return 0;
}

3
arch/arm/mach-snapdragon/clock-sdm845.c
View file

@ -14,6 +14,7 @@
#include <errno.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include "clock-snapdragon.h"
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
@ -84,7 +85,7 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
case 0x58: /*UART2*/
case GCC_QUPV3_WRAP1_S1_CLK: /*UART2*/
return clk_init_uart(priv, rate);
default:
return 0;

1
arch/arm/mach-snapdragon/clock-snapdragon.c
View file

@ -136,6 +136,7 @@ static const struct udevice_id msm_clk_ids[] = {
{ .compatible = "qcom,gcc-msm8996" },
{ .compatible = "qcom,gcc-apq8096" },
{ .compatible = "qcom,gcc-sdm845" },
{ .compatible = "qcom,gcc-qcs404" },
{ }
};

40
arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h Normal file
View file

@ -0,0 +1,40 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Qualcomm QCS404 sysmap
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
#ifndef _MACH_SYSMAP_QCS404_H
#define _MACH_SYSMAP_QCS404_H
#define GICD_BASE (0x0b000000)
#define GICC_BASE (0x0b002000)
/* Clocks: (from CLK_CTL_BASE) */
#define GPLL0_STATUS (0x21000)
#define APCS_GPLL_ENA_VOTE (0x45000)
#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
/* BLSP1 AHB clock (root clock for BLSP) */
#define BLSP1_AHB_CBCR 0x1008
/* Uart clock control registers */
#define BLSP1_UART2_BCR (0x3028)
#define BLSP1_UART2_APPS_CBCR (0x302C)
#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
#define BLSP1_UART2_APPS_CFG_RCGR (0x3038)
#define BLSP1_UART2_APPS_M (0x303C)
#define BLSP1_UART2_APPS_N (0x3040)
#define BLSP1_UART2_APPS_D (0x3044)
/* SD controller clock control registers */
#define SDCC_BCR(n) (((n) * 0x1000) + 0x41000)
#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004)
#define SDCC_CFG_RCGR(n) (((n) * 0x1000) + 0x41008)
#define SDCC_M(n) (((n) * 0x1000) + 0x4100C)
#define SDCC_N(n) (((n) * 0x1000) + 0x41010)
#define SDCC_D(n) (((n) * 0x1000) + 0x41014)
#define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018)
#define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C)
#endif

55
arch/arm/mach-snapdragon/pinctrl-qcs404.c Normal file
View file

@ -0,0 +1,55 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm QCS404 pinctrl
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
#include "pinctrl-snapdragon.h"
#include <common.h>
#define MAX_PIN_NAME_LEN 32
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
static const char * const msm_pinctrl_pins[] = {
"SDC1_RCLK",
"SDC1_CLK",
"SDC1_CMD",
"SDC1_DATA",
"SDC2_CLK",
"SDC2_CMD",
"SDC2_DATA",
};
static const struct pinctrl_function msm_pinctrl_functions[] = {
{"blsp_uart2", 1},
};
static const char *qcs404_get_function_name(struct udevice *dev,
unsigned int selector)
{
return msm_pinctrl_functions[selector].name;
}
static const char *qcs404_get_pin_name(struct udevice *dev,
unsigned int selector)
{
if (selector < 120) {
snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
return pin_name;
} else {
return msm_pinctrl_pins[selector - 120];
}
}
static unsigned int qcs404_get_function_mux(unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
struct msm_pinctrl_data qcs404_data = {
.pin_count = 126,
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
.get_function_name = qcs404_get_function_name,
.get_function_mux = qcs404_get_function_mux,
.get_pin_name = qcs404_get_pin_name,
};

1
arch/arm/mach-snapdragon/pinctrl-snapdragon.c
View file

@ -119,6 +119,7 @@ static const struct udevice_id msm_pinctrl_ids[] = {
#ifdef CONFIG_SDM845
{ .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data },
#endif
{ .compatible = "qcom,tlmm-qcs404", .data = (ulong)&qcs404_data },
{ }
};

1
arch/arm/mach-snapdragon/pinctrl-snapdragon.h
View file

@ -28,5 +28,6 @@ struct pinctrl_function {
extern struct msm_pinctrl_data apq8016_data;
extern struct msm_pinctrl_data apq8096_data;
extern struct msm_pinctrl_data sdm845_data;
extern struct msm_pinctrl_data qcs404_data;
#endif

31
arch/arm/mach-snapdragon/sysmap-qcs404.c Normal file
View file

@ -0,0 +1,31 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm QCS404 memory map
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
#include <common.h>
#include <asm/armv8/mmu.h>
static struct mm_region qcs404_mem_map[] = {
{
.virt = 0x0UL, /* Peripheral block */
.phys = 0x0UL, /* Peripheral block */
.size = 0x8000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL, /* DDR */
.phys = 0x80000000UL, /* DDR */
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = qcs404_mem_map;

12
board/qualcomm/dragonboard845c/Kconfig Normal file
View file

@ -0,0 +1,12 @@
if TARGET_DRAGONBOARD845C
config SYS_BOARD
default "dragonboard845c"
config SYS_CONFIG_NAME
default "dragonboard845c"
config SYS_VENDOR
default "qualcomm"
endif

6
board/qualcomm/dragonboard845c/MAINTAINERS Normal file
View file

@ -0,0 +1,6 @@
Qualcomm Robotics RB3 Development Platform (dragonboard845c)
M: Sumit Garg <sumit.garg@linaro.org>
S: Maintained
F: board/qualcomm/dragonboard845c/
F: include/configs/dragonboard845c.h
F: configs/dragonboard845c_defconfig

9
board/qualcomm/dragonboard845c/Makefile Normal file
View file

@ -0,0 +1,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
#
# This empty file prevents make error.
# Board logic defined in board/qualcomm/common/sdm845.c, no custom logic for dragonboard845c so far.
#
obj-y += dragonboard845c.o

63
board/qualcomm/dragonboard845c/db845c.its Normal file
View file

@ -0,0 +1,63 @@
/*
* U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
*/
/dts-v1/;
/ {
description = "Various kernels, ramdisks and FDT blobs";
#address-cells = <1>;
images {
kernel-1 {
description = "5.15.0-qcomlt-arm64";
data = /incbin/("./db845c_imgs/Image.gz--5.15-r0-dragonboard-845c-20211218193034-511.bin");
type = "kernel";
arch = "arm64";
os = "linux";
compression = "gzip";
load = <0x80000000>;
entry = <0x80000000>;
hash-1 {
algo = "sha1";
};
};
ramdisk-1 {
description = "initramfs-test-full-image-dragonboard-845c";
data = /incbin/("./db845c_imgs/initramfs-test-full-image-dragonboard-845c-20211218193034-511.rootfs.cpio.gz");
type = "ramdisk";
arch = "arm64";
os = "linux";
compression = "gzip";
load = <00000000>;
entry = <00000000>;
hash-1 {
algo = "sha1";
};
};
fdt-1 {
description = "sdm845-db845c-fdt";
data = /incbin/("./db845c_imgs/sdm845-db845c--5.15-r0-dragonboard-845c-20211218193034.dtb");
type = "flat_dt";
arch = "arm64";
compression = "none";
hash-1 {
algo = "sha1";
};
};
};
configurations {
default = "config-1";
config-1 {
description = "db845c kernel-5.15.0 configuration";
kernel = "kernel-1";
ramdisk = "ramdisk-1";
fdt = "fdt-1";
};
};
};

9
board/qualcomm/dragonboard845c/dragonboard845c.c Normal file
View file

@ -0,0 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This empty file prevents make linking error.
* No custom logic for dragonboard845c so far.
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
void noop(void) {}

15
board/qualcomm/qcs404-evb/Kconfig Normal file
View file

@ -0,0 +1,15 @@
if TARGET_QCS404EVB
config SYS_BOARD
default "qcs404-evb"
config SYS_VENDOR
default "qualcomm"
config SYS_SOC
default "qcs404"
config SYS_CONFIG_NAME
default "qcs404-evb"
endif

6
board/qualcomm/qcs404-evb/MAINTAINERS Normal file
View file

@ -0,0 +1,6 @@
Qualcomm Technologies, Inc. QCS404 evaluation board
M: Sumit Garg <sumit.garg@linaro.org>
S: Maintained
F: board/qualcomm/qcs404-evb/
F: include/configs/qcs404-evb.h
F: configs/qcs404evb_defconfig

6
board/qualcomm/qcs404-evb/Makefile Normal file
View file

@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
#
obj-y += qcs404-evb.o

33
board/qualcomm/qcs404-evb/qcs404-evb.c Normal file
View file

@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Board init file for QCS404-EVB
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <env.h>
#include <init.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <fdt_support.h>
#include <asm/arch/dram.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
return fdtdec_setup_mem_size_base();
}
int board_init(void)
{
return 0;
}
void reset_cpu(void)
{
psci_system_reset();
}

64
board/qualcomm/qcs404-evb/qcs404-evb.its Normal file
View file

@ -0,0 +1,64 @@
/*
* U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
*/
/dts-v1/;
/ {
description = "Various kernels, ramdisks and FDT blobs";
#address-cells = <1>;
images {
kernel-1 {
description = "5.18.0-rc1";
data = /incbin/("./qcs404_imgs/Image.gz");
type = "kernel";
arch = "arm64";
os = "linux";
compression = "gzip";
load = <0x80000000>;
entry = <0x80000000>;
hash-1 {
algo = "sha1";
};
};
ramdisk-1 {
description = "Initial ramdisk";
data = /incbin/("./qcs404_imgs/initramfs-tiny-image-qemuarm64-20220618074058-1169.rootfs.cpio.gz");
type = "ramdisk";
arch = "arm64";
os = "linux";
compression = "gzip";
load = <00000000>;
entry = <00000000>;
hash-1 {
algo = "sha1";
};
};
fdt-1 {
description = "qcs404-evb-fdt";
data = /incbin/("./qcs404_imgs/qcs404-evb-4000.dtb");
type = "flat_dt";
arch = "arm64";
compression = "none";
load = <0x83000000>;
hash-1 {
algo = "sha1";
};
};
};
configurations {
default = "config-1";
config-1 {
description = "qcs404-evb kernel-5.18.0-rc1 configuration";
kernel = "kernel-1";
ramdisk = "ramdisk-1";
fdt = "fdt-1";
};
};
};

2
board/siemens/iot2050/Kconfig
View file

@ -9,7 +9,7 @@
config TARGET_IOT2050_A53
bool "IOT2050 running on A53"
select ARM64
select SOC_K3_AM6
select SOC_K3_AM654
select BOARD_LATE_INIT
select SYS_DISABLE_DCACHE_OPS
select BINMAN

18
board/ti/am335x/board.c
View file

@ -966,10 +966,20 @@ int board_fit_config_name_match(const char *name)
return 0;
else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
return 0;
else if (board_is_bben() && !strcmp(name, "am335x-sancloud-bbe"))
return 0;
else
return -1;
else if (board_is_bben()) {
char subtype_id = board_ti_get_config()[1];
if (subtype_id == 'L') {
if (!strcmp(name, "am335x-sancloud-bbe-lite"))
return 0;
} else if (subtype_id == 'I') {
if (!strcmp(name, "am335x-sancloud-bbe-extended-wifi"))
return 0;
} else if (!strcmp(name, "am335x-sancloud-bbe")) {
return 0;
}
}
return -1;
}
#endif

5
board/ti/am335x/mux.c
View file

@ -401,8 +401,13 @@ void enable_board_pin_mux(void)
configure_module_pin_mux(mmc0_pin_mux_sk_evm);
} else if (board_is_bone_lt()) {
if (board_is_bben()) {
char subtype_id = board_ti_get_config()[1];
/* SanCloud Beaglebone LT Enhanced pinmux */
configure_module_pin_mux(rgmii1_pin_mux);
if (subtype_id == 'L')
configure_module_pin_mux(spi0_pin_mux);
} else {
/* Beaglebone LT pinmux */
configure_module_pin_mux(mii1_pin_mux);

4
board/ti/am65x/Kconfig
View file

@ -10,7 +10,7 @@ choice
config TARGET_AM654_A53_EVM
bool "TI K3 based AM654 EVM running on A53"
select ARM64
select SOC_K3_AM6
select SOC_K3_AM654
select SYS_DISABLE_DCACHE_OPS
select BOARD_LATE_INIT
imply TI_I2C_BOARD_DETECT
@ -19,7 +19,7 @@ config TARGET_AM654_R5_EVM
bool "TI K3 based AM654 EVM running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select SOC_K3_AM6
select SOC_K3_AM654
select K3_LOAD_SYSFW
select K3_AM654_DDRSS
imply SYS_K3_SPL_ATF

10
board/ti/am65x/evm.c
View file

@ -115,16 +115,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
return ret;
}
#if defined(CONFIG_TI_SECURE_DEVICE)
/* Make Crypto HW reserved for secure world use */
ret = fdt_disable_node(blob, "/bus@100000/crypto@4e00000");
if (ret < 0)
ret = fdt_disable_node(blob,
"/interconnect@100000/crypto@4E00000");
if (ret)
printf("%s: disabling SA2UL failed %d\n", __func__, ret);
#endif
return 0;
}
#endif

2
cmd/ti/ddr3.c
View file

@ -286,7 +286,7 @@ static int do_ddr_test(struct cmd_tbl *cmdtp,
if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) {
if (!is_ecc_enabled()) {
puts("ECC not enabled. Please Enable ECC any try again\n");
puts("ECC not enabled. Please Enable ECC and try again\n");
return CMD_RET_FAILURE;
}

4
common/spl/Kconfig
View file

@ -256,7 +256,9 @@ config SPL_LDSCRIPT
config SPL_TEXT_BASE
hex "SPL Text Base"
default ISW_ENTRY_ADDR if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
default 0x402F4000 if AM43XX
default 0x402F0400 if AM33XX
default 0x40301350 if OMAP54XX
default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
default 0x20060 if SUN50I_GEN_H6
default 0x00060 if ARCH_SUNXI

2
configs/am335x_evm_defconfig
View file

@ -55,7 +55,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am335x-evm am335x-bone am335x-sancloud-bbe am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
CONFIG_OF_LIST="am335x-evm am335x-bone am335x-sancloud-bbe am335x-sancloud-bbe-lite am335x-sancloud-bbe-extended-wifi am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y

2
configs/am335x_hs_evm_defconfig
View file

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0x40300350
CONFIG_SPL_TEXT_BASE=0x40300350
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_AM33XX=y

2
configs/am335x_hs_evm_uart_defconfig
View file

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0x40301950
CONFIG_SPL_TEXT_BASE=0x40301950
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_AM33XX=y

2
configs/am43xx_evm_usbhost_boot_defconfig
View file

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_ISW_ENTRY_ADDR=0x40300350
CONFIG_SPL_TEXT_BASE=0x40300350
CONFIG_ENV_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"

3
configs/am43xx_hs_evm_defconfig
View file

@ -3,12 +3,11 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0x403018e0
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_ENV_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_SPL_TEXT_BASE=0x403018E0
CONFIG_SPL_TEXT_BASE=0x403018e0
CONFIG_AM43XX=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000

74
configs/am43xx_hs_evm_qspi_defconfig Normal file
View file

@ -0,0 +1,74 @@
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0x300018e0
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x110000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="am43x-epos-evm"
CONFIG_AM43XX=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
CONFIG_ENV_OFFSET_REDUND=0x120000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
CONFIG_QSPI_BOOT=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_MISC_INIT_R is not set
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am4372-generic am437x-sk-evm am437x-idk-evm"
CONFIG_DTB_RESELECT=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RETRY_COUNT=10
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_SYS_RX_ETH_BUFFER=64
CONFIG_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_OMAP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0403
CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
CONFIG_USB_GADGET_DOWNLOAD=y

11
configs/am57xx_hs_evm_defconfig
View file

@ -5,7 +5,7 @@ CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
CONFIG_DEFAULT_DEVICE_TREE="am572x-idk"
CONFIG_OMAP54XX=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
@ -41,6 +41,7 @@ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_ADTIMG=y
@ -55,7 +56,7 @@ CONFIG_BOOTP_DNS2=y
CONFIG_CMD_AVB=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk"
CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am5729-beagleboneai am572x-idk am571x-idk am574x-idk"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
@ -68,9 +69,15 @@ CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DWC_AHCI=y
CONFIG_CLK=y
CONFIG_CLK_CDCE9XX=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_FASTBOOT_BUF_SIZE=0x2F000000

2
configs/am57xx_hs_evm_usb_defconfig
View file

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0x40306d50
CONFIG_SPL_TEXT_BASE=0x40306d50
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DM_GPIO=y

3
configs/am62x_evm_r5_defconfig
View file

@ -97,3 +97,6 @@ CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_LIB_RATIONAL=y
CONFIG_SPL_LIB_RATIONAL=y
CONFIG_ESM_K3=y
CONFIG_SPL_MISC=y
CONFIG_SPL_DRIVERS_MISC=y

2
configs/am65x_evm_a53_defconfig
View file

@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_SOC_K3_AM654=y
CONFIG_TARGET_AM654_A53_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000

2
configs/am65x_evm_r5_defconfig
View file

@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_SOC_K3_AM654=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y
CONFIG_ENV_SIZE=0x20000

2
configs/am65x_evm_r5_usbdfu_defconfig
View file

@ -7,7 +7,7 @@ CONFIG_SPL_MISC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_SOC_K3_AM654=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y
CONFIG_ENV_SIZE=0x20000

2
configs/am65x_evm_r5_usbmsc_defconfig
View file

@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_SOC_K3_AM654=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y
CONFIG_ENV_SIZE=0x20000

2
configs/am65x_hs_evm_a53_defconfig
View file

@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_SOC_K3_AM654=y
CONFIG_TARGET_AM654_A53_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000

2
configs/am65x_hs_evm_r5_defconfig
View file

@ -7,7 +7,7 @@ CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_SOC_K3_AM654=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y
CONFIG_ENV_SIZE=0x20000

2
configs/dra7xx_hs_evm_usb_defconfig
View file

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0x40306d50
CONFIG_SPL_TEXT_BASE=0x40306d50
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2

29
configs/dragonboard845c_defconfig Normal file
View file

@ -0,0 +1,29 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=19000000
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_SNAPDRAGON=y
CONFIG_DEFAULT_DEVICE_TREE="dragonboard845c"
CONFIG_TARGET_DRAGONBOARD845C=y
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 845C"
CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=5
CONFIG_SAVE_PREV_BL_FDT_ADDR=y
CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=512
CONFIG_CMD_GPIO=y
# CONFIG_NET is not set
CONFIG_CLK=y
CONFIG_MSM_GPIO=y
CONFIG_PM8916_GPIO=y
CONFIG_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PM8916=y
CONFIG_MSM_GENI_SERIAL=y
CONFIG_SPMI_MSM=y
CONFIG_LMB_MAX_REGIONS=64

2
configs/iot2050_defconfig
View file

@ -7,7 +7,7 @@ CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM6=y
CONFIG_SOC_K3_AM654=y
CONFIG_TARGET_IOT2050_A53=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000

42
configs/j721e_hs_evm_a72_defconfig
View file

@ -10,7 +10,6 @@ CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_J721E=y
CONFIG_TARGET_J721E_A72_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
@ -19,7 +18,6 @@ CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_ENV_OFFSET_REDUND=0x700000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@ -33,7 +31,7 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_fit_${boot}; run get_overlay_${boot}; run run_fit"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@ -44,6 +42,9 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
@ -53,15 +54,20 @@ CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@ -74,20 +80,23 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),1m(ospi.sysfw),256k(ospi.env.backup),57344k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
CONFIG_CMD_UBI=y
CONFIG_MMC_SPEED_MODE_SET=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="k3-j721e-common-proc-board k3-j721e-sk"
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
@ -103,6 +112,8 @@ CONFIG_CLK_TI_SCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x20000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
@ -112,10 +123,18 @@ CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
@ -133,10 +152,16 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
CONFIG_MULTIPLEXER=y
CONFIG_MUX_MMIO=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PHY=y
CONFIG_SPL_PHY=y
CONFIG_PHY_CADENCE_SIERRA=y
CONFIG_PHY_J721E_WIZ=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
@ -144,7 +169,11 @@ CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_REMOTEPROC_TI_K3_DSP=y
CONFIG_REMOTEPROC_TI_K3_R5F=y
CONFIG_DM_RESET=y
@ -170,6 +199,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451

56
configs/j721e_hs_evm_r5_defconfig
View file

@ -2,14 +2,14 @@ CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_SYS_MALLOC_F_LEN=0x70000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SOC_K3_J721E=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_J721E_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
@ -18,7 +18,6 @@ CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_ENV_OFFSET_REDUND=0x700000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@ -29,12 +28,14 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf5bfc
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc
CONFIG_SPL_BSS_MAX_SIZE=0xa000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_SPL_MALLOC=y
@ -42,11 +43,16 @@ CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
@ -56,10 +62,13 @@ CONFIG_SPL_REMOTEPROC=y
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
@ -67,26 +76,33 @@ CONFIG_CMD_REMOTEPROC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_OF_LIST="k3-j721e-r5-common-proc-board k3-j721e-r5-sk"
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
CONFIG_SPL_CLK_CCF=y
CONFIG_SPL_CLK_K3_PLL=y
CONFIG_SPL_CLK_K3=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_OMAP24XX=y
@ -94,11 +110,22 @@ CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
CONFIG_SPL_FS_LOADER=y
CONFIG_ESM_K3=y
CONFIG_K3_AVS0=y
CONFIG_ESM_PMIC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_HBMC_AM654=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_STMICRO=y
@ -108,7 +135,7 @@ CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_TI_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_TPS65941=y
CONFIG_DM_REGULATOR=y
@ -133,5 +160,18 @@ CONFIG_SYSRESET_TI_SCI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_FS_EXT4=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
CONFIG_LIB_RATIONAL=y
CONFIG_SPL_LIB_RATIONAL=y

2
configs/k2e_evm_defconfig
View file

@ -4,7 +4,7 @@ CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_SPL_TEXT_BASE=0xC100000
CONFIG_SYS_TEXT_BASE=0xC000000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x400

1
configs/k2e_hs_evm_defconfig
View file

@ -4,7 +4,6 @@ CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_SYS_TEXT_BASE=0xC000060
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x400

2
configs/k2g_evm_defconfig
View file

@ -4,7 +4,7 @@ CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC0A0000
CONFIG_SPL_TEXT_BASE=0xC0A0000
CONFIG_SYS_TEXT_BASE=0xC000000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x400

1
configs/k2g_hs_evm_defconfig
View file

@ -4,7 +4,6 @@ CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC0A0000
CONFIG_SYS_TEXT_BASE=0xC000060
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x400

2
configs/k2hk_evm_defconfig
View file

@ -4,7 +4,7 @@ CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC200000
CONFIG_SPL_TEXT_BASE=0xC200000
CONFIG_SYS_TEXT_BASE=0xC000000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x400

1
configs/k2hk_hs_evm_defconfig
View file

@ -4,7 +4,6 @@ CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC200000
CONFIG_SYS_TEXT_BASE=0xC000060
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x400

2
configs/k2l_evm_defconfig
View file

@ -4,7 +4,7 @@ CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_SPL_TEXT_BASE=0xC100000
CONFIG_SYS_TEXT_BASE=0xC000000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x400

1
configs/k2l_hs_evm_defconfig
View file

@ -4,7 +4,6 @@ CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_SYS_TEXT_BASE=0xC000060
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x400

1
configs/nokia_rx51_defconfig
View file

@ -24,7 +24,6 @@ CONFIG_AUTOBOOT_MENU_SHOW=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run sdboot;run emmcboot;run attachboot;echo"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run preboot"
# CONFIG_SYS_DEVICE_NULLDEV is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Nokia RX-51 # "

38
configs/qcs404evb_defconfig Normal file
View file

@ -0,0 +1,38 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=19000000
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_SNAPDRAGON=y
CONFIG_DEFAULT_DEVICE_TREE="qcs404-evb"
CONFIG_TARGET_QCS404EVB=y
CONFIG_IDENT_STRING="\nQualcomm QCS404-EVB"
CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon ignore_loglevel root= clk_ignore_unused"
CONFIG_SAVE_PREV_BL_FDT_ADDR=y
CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=512
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_NET is not set
CONFIG_CLK=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_MSM=y
CONFIG_PINCTRL=y
CONFIG_MSM_SERIAL=y
CONFIG_LMB_MAX_REGIONS=64

1
doc/board/qualcomm/index.rst
View file

@ -8,3 +8,4 @@ Qualcomm
dragonboard410c
sdm845
qcs404

79
doc/board/qualcomm/qcs404.rst Normal file
View file

@ -0,0 +1,79 @@
.. SPDX-License-Identifier: GPL-2.0+
.. sectionauthor:: Sumit Garg <sumit.garg@linaro.org>
QCS404 EVB
==========
About this
----------
This document describes the information about Qualcomm QCS404 evaluation board
and it's usage steps.
U-Boot can be used as a replacement for Qualcomm's original ABL (UEFI) bootloader.
It is loaded as an Android boot image through ABL
Installation
------------
Build
^^^^^
Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
$ export CROSS_COMPILE=<aarch64 toolchain prefix>
$ make qcs404evb_defconfig
$ make
This will build ``u-boot.bin`` in the configured output directory.
Generate FIT image
^^^^^^^^^^^^^^^^^^
A ``qcs404.its`` file can be found in ``board/qualcomm/qcs404-evb/`` directory.
It expects a folder as ``qcs404_imgs/`` in the main directory containing
pre-built kernel, dts and ramdisk images. See ``qcs404.its`` for full path to
images.
- Build FIT image::
mkimage -f qcs404-evb.its qcs404-evb.itb
Pack android boot image
^^^^^^^^^^^^^^^^^^^^^^^
We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel,
and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
with appended dtb, so let's mimic linux to satisfy stock bootloader:
- create dump dtb::
workdir=/tmp/prepare_payload
mkdir -p "$workdir"
cd "$workdir"
mock_dtb="$workdir"/payload_mock.dtb
dtc -I dts -O dtb -o "$mock_dtb" << EOF
/dts-v1/;
/ {
model = "Qualcomm Technologies, Inc. QCS404 EVB 4000";
compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb", "qcom,qcs404";
#address-cells = <2>;
#size-cells = <2>;
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0 0x80000000 0 0>;
};
chosen { };
};
EOF
- gzip u-boot ``gzip u-boot.bin``
- append dtb to gzipped u-boot: ``cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb``
Now we've got everything to build android boot image:::
mkbootimg --kernel u-boot.bin.gz-dtb \
--ramdisk qcs404-evb.itb --pagesize 4096 \
--base 0x80000000 --output boot.img
Flash image on qcs404-evb using fastboot method.

102
doc/board/qualcomm/sdm845.rst
View file

@ -35,9 +35,25 @@ Pack android boot image
^^^^^^^^^^^^^^^^^^^^^^^
We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel,
and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
with appended dtb, so let's mimic linux to satisfy stock bootloader:
with appended dtb, so let's mimic linux to satisfy stock bootloader.
- create dump dtb::
Boards
------------
starqlte
^^^^^^^^^^^^
The starqltechn is a production board for Samsung S9 (SM-G9600) phone,
based on the Qualcomm SDM845 SoC.
Steps:
- Build u-boot::
$ export CROSS_COMPILE=<aarch64 toolchain prefix>
$ make starqltechn_defconfig
$ make
- Create dump dtb::
workdir=/tmp/prepare_payload
mkdir -p "$workdir"
@ -56,10 +72,15 @@ with appended dtb, so let's mimic linux to satisfy stock bootloader:
};
EOF
- gzip u-boot ``gzip u-boot.bin``
- append dtb to gzipped u-boot: ``cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb``
- gzip u-boot::
Now we've got everything to build android boot image:::
gzip u-boot.bin
- Append dtb to gzipped u-boot::
cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb
- Now we've got everything to build android boot image::
mkbootimg --base 0x0 --kernel_offset 0x00008000 \
--ramdisk_offset 0x02000000 --tags_offset 0x01e00000 \
@ -68,16 +89,69 @@ Now we've got everything to build android boot image:::
--kernel u-boot.bin.gz-dtb \
-o boot.img
Flash image with your phone's flashing method.
Boards
------------
starqlte
^^^^^^^^^^^^
The starqltechn is a production board for Samsung S9 (SM-G9600) phone,
based on the Qualcomm SDM845 SoC.
- Flash image with your phone's flashing method.
More information can be found on the `Samsung S9 page`_.
dragonboard845c
^^^^^^^^^^^^^^^
The dragonboard845c is a Qualcomm Robotics RB3 Development Platform, based on
the Qualcomm SDM845 SoC.
Steps:
- Build u-boot::
$ export CROSS_COMPILE=<aarch64 toolchain prefix>
$ make dragonboard845c_defconfig
$ make
- Create dummy dtb::
workdir=/tmp/prepare_payload
mkdir -p "$workdir"
mock_dtb="$workdir"/payload_mock.dtb
dtc -I dts -O dtb -o "$mock_dtb" << EOF
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0 0x80000000 0 0>;
};
chosen { };
};
EOF
- gzip u-boot::
gzip u-boot.bin
- Append dtb to gzipped u-boot::
cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb
- A ``db845c.its`` file can be found in ``board/qualcomm/dragonboard845c/``
directory. It expects a folder as ``db845c_imgs/`` in the main directory
containing pre-built kernel, dts and ramdisk images. See ``db845c.its``
for full path to images::
mkimage -f db845c.its db845c.itb
- Now we've got everything to build android boot image::
mkbootimg --kernel u-boot.bin.gz-dtb --ramdisk db845c.itb \
--output boot.img --pagesize 4096 --base 0x80000000
- Flash boot.img using db845c fastboot method.
More information can be found on the `DragonBoard 845c page`_.
.. _Samsung S9 page: https://en.wikipedia.org/wiki/Samsung_Galaxy_S9
.. _DragonBoard 845c page: https://www.96boards.org/product/rb3-platform/

2
drivers/dma/ti/Makefile
View file

@ -3,7 +3,7 @@
obj-$(CONFIG_TI_K3_NAVSS_UDMA) += k3-udma.o
obj-$(CONFIG_TI_K3_PSIL) += k3-psil-data.o
k3-psil-data-y += k3-psil.o
k3-psil-data-$(CONFIG_SOC_K3_AM6) += k3-psil-am654.o
k3-psil-data-$(CONFIG_SOC_K3_AM654) += k3-psil-am654.o
k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o
k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o

2
drivers/dma/ti/k3-psil.c
View file

@ -16,7 +16,7 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id)
int i;
if (!soc_ep_map) {
if (IS_ENABLED(CONFIG_SOC_K3_AM6))
if (IS_ENABLED(CONFIG_SOC_K3_AM654))
soc_ep_map = &am654_ep_map;
else if (IS_ENABLED(CONFIG_SOC_K3_J721E))
soc_ep_map = &j721e_ep_map;

18
drivers/iommu/apple_dart.c
View file

@ -24,6 +24,12 @@
#define DART_TTBR_VALID BIT(31)
#define DART_TTBR_SHIFT 12
#define DART_T8110_TCR(sid) (0x1000 + 4 * (sid))
#define DART_T8110_TCR_BYPASS_DAPF BIT(2)
#define DART_T8110_TCR_BYPASS_DART BIT(1)
#define DART_T8110_TCR_TRANSLATE_ENABLE BIT(0)
#define DART_T8110_TTBR(sid) (0x1400 + 4 * (sid))
static int apple_dart_probe(struct udevice *dev)
{
void *base;
@ -34,7 +40,16 @@ static int apple_dart_probe(struct udevice *dev)
return -EINVAL;
u32 params2 = readl(base + DART_PARAMS2);
if (params2 & DART_PARAMS2_BYPASS_SUPPORT) {
if (!(params2 & DART_PARAMS2_BYPASS_SUPPORT))
return 0;
if (device_is_compatible(dev, "apple,t8112-dart")) {
for (sid = 0; sid < 256; sid++) {
writel(DART_T8110_TCR_BYPASS_DART | DART_T8110_TCR_BYPASS_DAPF,
base + DART_T8110_TCR(sid));
writel(0, base + DART_T8110_TTBR(sid));
}
} else {
for (sid = 0; sid < 16; sid++) {
writel(DART_TCR_BYPASS_DART | DART_TCR_BYPASS_DAPF,
base + DART_TCR(sid));
@ -49,6 +64,7 @@ static int apple_dart_probe(struct udevice *dev)
static const struct udevice_id apple_dart_ids[] = {
{ .compatible = "apple,t8103-dart" },
{ .compatible = "apple,t6000-dart" },
{ .compatible = "apple,t8112-dart" },
{ /* sentinel */ }
};

96
drivers/mmc/msm_sdhci.c
View file

@ -22,18 +22,17 @@
#define SDCC_MCI_POWER_SW_RST BIT(7)
/* This is undocumented register */
#define SDCC_MCI_VERSION 0x50
#define SDCC_MCI_VERSION_MAJOR_SHIFT 28
#define SDCC_MCI_VERSION_MAJOR_MASK (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT)
#define SDCC_MCI_VERSION_MINOR_MASK 0xff
#define SDCC_MCI_VERSION 0x50
#define SDCC_V5_VERSION 0x318
#define SDCC_VERSION_MAJOR_SHIFT 28
#define SDCC_VERSION_MAJOR_MASK (0xf << SDCC_VERSION_MAJOR_SHIFT)
#define SDCC_VERSION_MINOR_MASK 0xff
#define SDCC_MCI_STATUS2 0x6C
#define SDCC_MCI_STATUS2_MCI_ACT 0x1
#define SDCC_MCI_HC_MODE 0x78
/* Offset to SDHCI registers */
#define SDCC_SDHCI_OFFSET 0x900
/* Non standard (?) SDHCI register */
#define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c
@ -47,6 +46,10 @@ struct msm_sdhc {
void *base;
};
struct msm_sdhc_variant_info {
bool mci_removed;
};
DECLARE_GLOBAL_DATA_PTR;
static int msm_sdc_clk_init(struct udevice *dev)
@ -85,25 +88,8 @@ static int msm_sdc_clk_init(struct udevice *dev)
return 0;
}
static int msm_sdc_probe(struct udevice *dev)
static int msm_sdc_mci_init(struct msm_sdhc *prv)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct msm_sdhc_plat *plat = dev_get_plat(dev);
struct msm_sdhc *prv = dev_get_priv(dev);
struct sdhci_host *host = &prv->host;
u32 core_version, core_minor, core_major;
u32 caps;
int ret;
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
host->max_clk = 0;
/* Init clocks */
ret = msm_sdc_clk_init(dev);
if (ret)
return ret;
/* Reset the core and Enable SDHC mode */
writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST,
prv->base + SDCC_MCI_POWER);
@ -126,12 +112,45 @@ static int msm_sdc_probe(struct udevice *dev)
/* Enable host-controller mode */
writel(1, prv->base + SDCC_MCI_HC_MODE);
core_version = readl(prv->base + SDCC_MCI_VERSION);
return 0;
}
core_major = (core_version & SDCC_MCI_VERSION_MAJOR_MASK);
core_major >>= SDCC_MCI_VERSION_MAJOR_SHIFT;
static int msm_sdc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct msm_sdhc_plat *plat = dev_get_plat(dev);
struct msm_sdhc *prv = dev_get_priv(dev);
const struct msm_sdhc_variant_info *var_info;
struct sdhci_host *host = &prv->host;
u32 core_version, core_minor, core_major;
u32 caps;
int ret;
core_minor = core_version & SDCC_MCI_VERSION_MINOR_MASK;
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
host->max_clk = 0;
/* Init clocks */
ret = msm_sdc_clk_init(dev);
if (ret)
return ret;
var_info = (void *)dev_get_driver_data(dev);
if (!var_info->mci_removed) {
ret = msm_sdc_mci_init(prv);
if (ret)
return ret;
}
if (!var_info->mci_removed)
core_version = readl(prv->base + SDCC_MCI_VERSION);
else
core_version = readl(host->ioaddr + SDCC_V5_VERSION);
core_major = (core_version & SDCC_VERSION_MAJOR_MASK);
core_major >>= SDCC_VERSION_MAJOR_SHIFT;
core_minor = core_version & SDCC_VERSION_MINOR_MASK;
/*
* Support for some capabilities is not advertised by newer
@ -161,9 +180,13 @@ static int msm_sdc_probe(struct udevice *dev)
static int msm_sdc_remove(struct udevice *dev)
{
struct msm_sdhc *priv = dev_get_priv(dev);
const struct msm_sdhc_variant_info *var_info;
/* Disable host-controller mode */
writel(0, priv->base + SDCC_MCI_HC_MODE);
var_info = (void *)dev_get_driver_data(dev);
/* Disable host-controller mode */
if (!var_info->mci_removed)
writel(0, priv->base + SDCC_MCI_HC_MODE);
return 0;
}
@ -195,8 +218,17 @@ static int msm_sdc_bind(struct udevice *dev)
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
static const struct msm_sdhc_variant_info msm_sdhc_mci_var = {
.mci_removed = false,
};
static const struct msm_sdhc_variant_info msm_sdhc_v5_var = {
.mci_removed = true,
};
static const struct udevice_id msm_mmc_ids[] = {
{ .compatible = "qcom,sdhci-msm-v4" },
{ .compatible = "qcom,sdhci-msm-v4", .data = (ulong)&msm_sdhc_mci_var },
{ .compatible = "qcom,sdhci-msm-v5", .data = (ulong)&msm_sdhc_v5_var },
{ }
};

88
drivers/phy/ti/phy-j721e-wiz.c
View file

@ -221,6 +221,44 @@ enum wiz_type {
AM64_WIZ_10G,
};
struct wiz_data {
enum wiz_type type;
const struct reg_field *pll0_refclk_mux_sel;
const struct reg_field *pll1_refclk_mux_sel;
const struct reg_field *refclk_dig_sel;
const struct reg_field *pma_cmn_refclk1_dig_div;
const struct wiz_clk_mux_sel *clk_mux_sel;
unsigned int clk_div_sel_num;
};
static const struct wiz_data j721e_16g_data = {
.type = J721E_WIZ_16G,
.pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
.pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
.refclk_dig_sel = &refclk_dig_sel_16g,
.pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div,
.clk_mux_sel = clk_mux_sel_16g,
.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G,
};
static const struct wiz_data j721e_10g_data = {
.type = J721E_WIZ_10G,
.pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
.pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
.refclk_dig_sel = &refclk_dig_sel_10g,
.clk_mux_sel = clk_mux_sel_10g,
.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
};
static struct wiz_data am64_10g_data = {
.type = AM64_WIZ_10G,
.pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
.pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
.refclk_dig_sel = &refclk_dig_sel_10g,
.clk_mux_sel = clk_mux_sel_10g,
.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
};
#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
#define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
@ -253,6 +291,7 @@ struct wiz {
u32 lane_phy_type[WIZ_MAX_LANES];
struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS];
unsigned int id;
const struct wiz_data *data;
};
struct wiz_div_clk {
@ -667,7 +706,7 @@ static int wiz_regfield_init(struct wiz *wiz)
struct regmap *regmap = wiz->regmap;
int num_lanes = wiz->num_lanes;
struct udevice *dev = wiz->dev;
enum wiz_type type;
const struct wiz_data *data = wiz->data;
int i;
wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
@ -704,36 +743,31 @@ static int wiz_regfield_init(struct wiz *wiz)
return PTR_ERR(wiz->div_sel_field[CMN_REFCLK]);
}
wiz->div_sel_field[CMN_REFCLK1] =
devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk1_dig_div);
if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1])) {
dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1]);
if (data->pma_cmn_refclk1_dig_div) {
wiz->div_sel_field[CMN_REFCLK1] =
devm_regmap_field_alloc(dev, regmap, *data->pma_cmn_refclk1_dig_div);
if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1])) {
dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1]);
}
}
wiz->mux_sel_field[PLL0_REFCLK] =
devm_regmap_field_alloc(dev, regmap, pll0_refclk_mux_sel);
devm_regmap_field_alloc(dev, regmap, *data->pll0_refclk_mux_sel);
if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {
dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);
}
wiz->mux_sel_field[PLL1_REFCLK] =
devm_regmap_field_alloc(dev, regmap, pll1_refclk_mux_sel);
devm_regmap_field_alloc(dev, regmap, *data->pll1_refclk_mux_sel);
if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {
dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
}
type = dev_get_driver_data(dev);
if (type == J721E_WIZ_10G || type == AM64_WIZ_10G)
wiz->mux_sel_field[REFCLK_DIG] =
devm_regmap_field_alloc(dev, regmap,
refclk_dig_sel_10g);
else
wiz->mux_sel_field[REFCLK_DIG] =
devm_regmap_field_alloc(dev, regmap,
refclk_dig_sel_16g);
wiz->mux_sel_field[REFCLK_DIG] =
devm_regmap_field_alloc(dev, regmap, *data->refclk_dig_sel);
if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {
dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);
@ -1059,14 +1093,12 @@ static int j721e_wiz_probe(struct udevice *dev)
wiz->num_lanes = num_lanes;
wiz->dev = dev;
wiz->clk_div_sel = clk_div_sel;
wiz->type = dev_get_driver_data(dev);
if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G) {
wiz->clk_mux_sel = clk_mux_sel_10g;
wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;
} else {
wiz->clk_mux_sel = clk_mux_sel_16g;
wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;
}
wiz->data = (struct wiz_data *)dev_get_driver_data(dev);
wiz->type = wiz->data->type;
wiz->clk_mux_sel = (struct wiz_clk_mux_sel *)wiz->data->clk_mux_sel;
wiz->clk_div_sel_num = wiz->data->clk_div_sel_num;
rc = wiz_get_lane_phy_types(dev, wiz);
if (rc) {
@ -1133,13 +1165,13 @@ static int j721e_wiz_remove(struct udevice *dev)
static const struct udevice_id j721e_wiz_ids[] = {
{
.compatible = "ti,j721e-wiz-16g", .data = J721E_WIZ_16G,
.compatible = "ti,j721e-wiz-16g", .data = (ulong)&j721e_16g_data,
},
{
.compatible = "ti,j721e-wiz-10g", .data = J721E_WIZ_10G,
.compatible = "ti,j721e-wiz-10g", .data = (ulong)&j721e_10g_data,
},
{
.compatible = "ti,am64-wiz-10g", .data = AM64_WIZ_10G,
.compatible = "ti,am64-wiz-10g", .data = (ulong)&am64_10g_data,
},
{}
};

2
drivers/ram/Kconfig
View file

@ -45,7 +45,7 @@ config MPC83XX_SDRAM
config K3_AM654_DDRSS
bool "Enable AM654 DDRSS support"
depends on RAM && SOC_K3_AM6
depends on RAM && SOC_K3_AM654
help
K3 based AM654 devices has DDR memory subsystem that comprises
Synopys DDR controller, Synopsis DDR phy and wrapper logic to

31
drivers/xen/hypervisor.c
View file

@ -144,6 +144,36 @@ struct shared_info *map_shared_info(void *p)
return HYPERVISOR_shared_info;
}
void unmap_shared_info(void)
{
xen_pfn_t shared_info_pfn = virt_to_pfn(HYPERVISOR_shared_info);
struct xen_remove_from_physmap xrfp = {0};
struct xen_memory_reservation reservation = {0};
xen_ulong_t nr_exts = 1;
xrfp.domid = DOMID_SELF;
xrfp.gpfn = shared_info_pfn;
if (HYPERVISOR_memory_op(XENMEM_remove_from_physmap, &xrfp) != 0)
panic("Failed to unmap HYPERVISOR_shared_info\n");
/*
* After removing from physmap there will be a hole in address space on
* HYPERVISOR_shared_info address, so to free memory allocated with
* memalign and prevent exceptions during access to this page we need to
* fill this 4KB hole with XENMEM_populate_physmap before jumping to Linux.
*/
reservation.domid = DOMID_SELF;
reservation.extent_order = 0;
reservation.address_bits = 0;
set_xen_guest_handle(reservation.extent_start, &shared_info_pfn);
reservation.nr_extents = nr_exts;
if (HYPERVISOR_memory_op(XENMEM_populate_physmap, &reservation) != nr_exts)
panic("Failed to populate memory on HYPERVISOR_shared_info addr\n");
/* Now we can return this to memory allocator */
free(HYPERVISOR_shared_info);
}
void do_hypervisor_callback(struct pt_regs *regs)
{
unsigned long l1, l2, l1i, l2i;
@ -251,4 +281,5 @@ void xen_fini(void)
fini_gnttab();
fini_xenbus();
fini_events();
unmap_shared_info();
}

21
include/configs/dragonboard845c.h Normal file
View file

@ -0,0 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration file for Dragonboard 845c, based on Qualcomm SDA845 chip
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
#ifndef __CONFIGS_SDM845_H
#define __CONFIGS_SDM845_H
#include <linux/sizes.h>
#include <asm/arch/sysmap-sdm845.h>
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x5000000\0" \
"bootm_low=0x80000000\0" \
"bootcmd=bootm $prevbl_initrd_start_addr\0"
#endif

21
include/configs/qcs404-evb.h Normal file
View file

@ -0,0 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration file for QCS404 evaluation board
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
#ifndef __CONFIGS_QCS404EVB_H
#define __CONFIGS_QCS404EVB_H
#include <linux/sizes.h>
#include <asm/arch/sysmap-qcs404.h>
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x5000000\0" \
"bootm_low=0x80000000\0" \
"bootcmd=bootm $prevbl_initrd_start_addr\0"
#endif

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