mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 02:08:38 +00:00
Merge with git+ssh://sr@pollux.denx.org/home/sr/git/u-boot/denx/.git
This commit is contained in:
Stefan Roese
commit
aeeced147c
9 changed files with 896 additions and 27 deletions
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|
@ -1,4 +1,11 @@
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/*
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* (C) Copyright 2006
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* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
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* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
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* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
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* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
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* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
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*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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@ -18,10 +25,352 @@
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* MA 02111-1307 USA
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*/
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/* define DEBUG for debug output */
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#undef DEBUG
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <ppc440.h>
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#include "sdram.h"
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#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
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defined(CONFIG_DDR_DATA_EYE)
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/*-----------------------------------------------------------------------------+
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* wait_for_dlllock.
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+----------------------------------------------------------------------------*/
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static int wait_for_dlllock(void)
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{
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unsigned long val;
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int wait = 0;
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/* -----------------------------------------------------------+
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* Wait for the DCC master delay line to finish calibration
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_17);
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val = DDR0_17_DLLLOCKREG_UNLOCKED;
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while (wait != 0xffff) {
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val = mfdcr(ddrcfgd);
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if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
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/* dlllockreg bit on */
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return 0;
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else
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wait++;
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}
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debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
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debug("Waiting for dlllockreg bit to raise\n");
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return -1;
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}
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#endif
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#if defined(CONFIG_DDR_DATA_EYE)
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/*-----------------------------------------------------------------------------+
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* wait_for_dram_init_complete.
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+----------------------------------------------------------------------------*/
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int wait_for_dram_init_complete(void)
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{
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unsigned long val;
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int wait = 0;
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/* --------------------------------------------------------------+
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* Wait for 'DRAM initialization complete' bit in status register
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* -------------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_00);
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while (wait != 0xffff) {
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val = mfdcr(ddrcfgd);
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if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
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/* 'DRAM initialization complete' bit */
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return 0;
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else
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wait++;
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}
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debug("DRAM initialization complete bit in status register did not rise\n");
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return -1;
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}
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#define NUM_TRIES 64
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#define NUM_READS 10
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/*-----------------------------------------------------------------------------+
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* denali_core_search_data_eye.
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+----------------------------------------------------------------------------*/
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void denali_core_search_data_eye(unsigned long memory_size)
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{
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int k, j;
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u32 val;
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u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
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u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
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u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
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u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
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volatile u32 *ram_pointer;
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u32 test[NUM_TRIES] = {
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
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ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
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for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
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/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
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/* -----------------------------------------------------------+
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* De-assert 'start' parameter.
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_02);
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val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
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mtdcr(ddrcfgd, val);
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/* -----------------------------------------------------------+
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* Set 'wr_dqs_shift'
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_09);
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val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
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| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
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mtdcr(ddrcfgd, val);
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/* -----------------------------------------------------------+
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* Set 'dqs_out_shift' = wr_dqs_shift + 32
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* ----------------------------------------------------------*/
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dqs_out_shift = wr_dqs_shift + 32;
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mtdcr(ddrcfga, DDR0_22);
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val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
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| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
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mtdcr(ddrcfgd, val);
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passing_cases = 0;
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for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
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/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
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/* -----------------------------------------------------------+
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* Set 'dll_dqs_delay_X'.
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* ----------------------------------------------------------*/
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/* dll_dqs_delay_0 */
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mtdcr(ddrcfga, DDR0_17);
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val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
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| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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/* dll_dqs_delay_1 to dll_dqs_delay_4 */
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mtdcr(ddrcfga, DDR0_18);
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val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
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| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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/* dll_dqs_delay_5 to dll_dqs_delay_8 */
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mtdcr(ddrcfga, DDR0_19);
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val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
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| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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ppcMsync();
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ppcMbar();
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/* -----------------------------------------------------------+
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* Assert 'start' parameter.
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_02);
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val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
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mtdcr(ddrcfgd, val);
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ppcMsync();
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ppcMbar();
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/* -----------------------------------------------------------+
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* Wait for the DCC master delay line to finish calibration
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* ----------------------------------------------------------*/
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if (wait_for_dlllock() != 0) {
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printf("dlllock did not occur !!!\n");
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printf("denali_core_search_data_eye!!!\n");
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printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
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wr_dqs_shift, dll_dqs_delay_X);
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hang();
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}
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ppcMsync();
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ppcMbar();
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if (wait_for_dram_init_complete() != 0) {
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printf("dram init complete did not occur !!!\n");
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printf("denali_core_search_data_eye!!!\n");
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printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
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wr_dqs_shift, dll_dqs_delay_X);
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hang();
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}
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udelay(100); /* wait 100us to ensure init is really completed !!! */
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/* write values */
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for (j=0; j<NUM_TRIES; j++) {
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ram_pointer[j] = test[j];
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/* clear any cache at ram location */
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
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}
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/* read values back */
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for (j=0; j<NUM_TRIES; j++) {
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for (k=0; k<NUM_READS; k++) {
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/* clear any cache at ram location */
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
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if (ram_pointer[j] != test[j])
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break;
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}
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/* read error */
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if (k != NUM_READS)
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break;
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}
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/* See if the dll_dqs_delay_X value passed.*/
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if (j < NUM_TRIES) {
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/* Failed */
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passing_cases = 0;
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/* break; */
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} else {
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/* Passed */
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if (passing_cases == 0)
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dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
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passing_cases++;
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if (passing_cases >= max_passing_cases) {
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max_passing_cases = passing_cases;
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wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
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dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
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dll_dqs_delay_X_end_window = dll_dqs_delay_X;
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}
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}
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/* -----------------------------------------------------------+
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* De-assert 'start' parameter.
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_02);
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val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
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mtdcr(ddrcfgd, val);
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} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
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} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
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/* -----------------------------------------------------------+
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* Largest passing window is now detected.
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* ----------------------------------------------------------*/
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/* Compute dll_dqs_delay_X value */
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dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
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wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
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debug("DQS calibration - Window detected:\n");
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debug("max_passing_cases = %d\n", max_passing_cases);
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debug("wr_dqs_shift = %d\n", wr_dqs_shift);
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||||
debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
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debug("dll_dqs_delay_X window = %d - %d\n",
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dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
|
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|
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/* -----------------------------------------------------------+
|
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* De-assert 'start' parameter.
|
||||
* ----------------------------------------------------------*/
|
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mtdcr(ddrcfga, DDR0_02);
|
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val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'wr_dqs_shift'
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_09);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
|
||||
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
|
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mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_09=0x%08lx\n", val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'dqs_out_shift' = wr_dqs_shift + 32
|
||||
* ----------------------------------------------------------*/
|
||||
dqs_out_shift = wr_dqs_shift + 32;
|
||||
mtdcr(ddrcfga, DDR0_22);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
|
||||
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
|
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mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_22=0x%08lx\n", val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'dll_dqs_delay_X'.
|
||||
* ----------------------------------------------------------*/
|
||||
/* dll_dqs_delay_0 */
|
||||
mtdcr(ddrcfga, DDR0_17);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
|
||||
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
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debug("DDR0_17=0x%08lx\n", val);
|
||||
|
||||
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
|
||||
mtdcr(ddrcfga, DDR0_18);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_18=0x%08lx\n", val);
|
||||
|
||||
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
|
||||
mtdcr(ddrcfga, DDR0_19);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_19=0x%08lx\n", val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Assert 'start' parameter.
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Wait for the DCC master delay line to finish calibration
|
||||
* ----------------------------------------------------------*/
|
||||
if (wait_for_dlllock() != 0) {
|
||||
printf("dlllock did not occur !!!\n");
|
||||
hang();
|
||||
}
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
if (wait_for_dram_init_complete() != 0) {
|
||||
printf("dram init complete did not occur !!!\n");
|
||||
hang();
|
||||
}
|
||||
udelay(100); /* wait 100us to ensure init is really completed !!! */
|
||||
}
|
||||
#endif /* CONFIG_DDR_DATA_EYE */
|
||||
|
||||
/*************************************************************************
|
||||
*
|
||||
* initdram -- 440EPx's DDR controller is a DENALI Core
|
||||
|
|
@ -30,8 +379,6 @@
|
|||
long int initdram (int board_type)
|
||||
{
|
||||
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
|
||||
volatile ulong val;
|
||||
|
||||
mtsdram(DDR0_02, 0x00000000);
|
||||
|
||||
mtsdram(DDR0_00, 0x0000190A);
|
||||
|
|
@ -64,14 +411,15 @@ long int initdram (int board_type)
|
|||
mtsdram(DDR0_44, 0x00000005);
|
||||
mtsdram(DDR0_02, 0x00000001);
|
||||
|
||||
/*
|
||||
* Wait for DCC master delay line to finish calibration
|
||||
*/
|
||||
mfsdram(DDR0_17, val);
|
||||
while (((val >> 8) & 0x000007f) == 0) {
|
||||
mfsdram(DDR0_17, val);
|
||||
}
|
||||
wait_for_dlllock();
|
||||
#endif /* #ifndef CONFIG_NAND_U_BOOT */
|
||||
|
||||
#ifdef CONFIG_DDR_DATA_EYE
|
||||
/* -----------------------------------------------------------+
|
||||
* Perform data eye search if requested.
|
||||
* ----------------------------------------------------------*/
|
||||
denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20);
|
||||
#endif
|
||||
|
||||
return (CFG_MBYTES_SDRAM << 20);
|
||||
}
|
||||
|
|
|
|||
508
board/amcc/sequoia/sdram.h
Normal file
508
board/amcc/sequoia/sdram.h
Normal file
|
|
@ -0,0 +1,508 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
|
||||
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
|
||||
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
|
||||
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
|
||||
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _SPD_SDRAM_DENALI_H_
|
||||
#define _SPD_SDRAM_DENALI_H_
|
||||
|
||||
#define ppcMsync sync
|
||||
#define ppcMbar eieio
|
||||
|
||||
/* General definitions */
|
||||
#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */
|
||||
#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */
|
||||
#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */
|
||||
#define SDRAM_NONE 0 /* No DIMM detected in Slot */
|
||||
#define MAXRANKS 2 /* 2 ranks maximum */
|
||||
|
||||
/* Supported PLB Frequencies */
|
||||
#define PLB_FREQ_133MHZ 133333333
|
||||
#define PLB_FREQ_152MHZ 152000000
|
||||
#define PLB_FREQ_160MHZ 160000000
|
||||
#define PLB_FREQ_166MHZ 166666666
|
||||
|
||||
/* Denali Core Registers */
|
||||
#define SDRAM_DCR_BASE 0x10
|
||||
|
||||
#define DDR_DCR_BASE 0x10
|
||||
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
|
||||
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Values for ddrcfga register - indirect addressing of these regs
|
||||
+-----------------------------------------------------------------------------*/
|
||||
|
||||
#define DDR0_00 0x00
|
||||
#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
|
||||
#define DDR0_00_INT_ACK_ALL 0x7F000000
|
||||
#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
/* Status */
|
||||
#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
|
||||
/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT0 0x00010000
|
||||
/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT1 0x00020000
|
||||
/* Bit2. Single correctable ECC event detected */
|
||||
#define DDR0_00_INT_STATUS_BIT2 0x00040000
|
||||
/* Bit3. Multiple correctable ECC events detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT3 0x00080000
|
||||
/* Bit4. Single uncorrectable ECC event detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT4 0x00100000
|
||||
/* Bit5. Multiple uncorrectable ECC events detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT5 0x00200000
|
||||
/* Bit6. DRAM initialization complete. */
|
||||
#define DDR0_00_INT_STATUS_BIT6 0x00400000
|
||||
/* Bit7. Logical OR of all lower bits. */
|
||||
#define DDR0_00_INT_STATUS_BIT7 0x00800000
|
||||
|
||||
#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
|
||||
#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
|
||||
#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
|
||||
|
||||
#define DDR0_01 0x01
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
#define DDR0_01_INT_MASK_MASK 0x000000FF
|
||||
#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
|
||||
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
|
||||
|
||||
#define DDR0_02 0x02
|
||||
#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
|
||||
#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)
|
||||
#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)
|
||||
#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
|
||||
#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
|
||||
#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
|
||||
#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
|
||||
#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_02_START_MASK 0x00000001
|
||||
#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
#define DDR0_02_START_OFF 0x00000000
|
||||
#define DDR0_02_START_ON 0x00000001
|
||||
|
||||
#define DDR0_03 0x03
|
||||
#define DDR0_03_BSTLEN_MASK 0x07000000
|
||||
#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_03_CASLAT_MASK 0x00070000
|
||||
#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
|
||||
#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_03_INITAREF_MASK 0x0000000F
|
||||
#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
|
||||
#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
|
||||
|
||||
#define DDR0_04 0x04
|
||||
#define DDR0_04_TRC_MASK 0x1F000000
|
||||
#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_04_TRRD_MASK 0x00070000
|
||||
#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_04_TRTP_MASK 0x00000700
|
||||
#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
|
||||
#define DDR0_05 0x05
|
||||
#define DDR0_05_TMRD_MASK 0x1F000000
|
||||
#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_05_TEMRS_MASK 0x00070000
|
||||
#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_05_TRP_MASK 0x00000F00
|
||||
#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_05_TRAS_MIN_MASK 0x000000FF
|
||||
#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
|
||||
#define DDR0_06 0x06
|
||||
#define DDR0_06_WRITEINTERP_MASK 0x01000000
|
||||
#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_06_TWTR_MASK 0x00070000
|
||||
#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_06_TDLL_MASK 0x0000FF00
|
||||
#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
#define DDR0_06_TRFC_MASK 0x0000007F
|
||||
#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_07 0x07
|
||||
#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
|
||||
#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_07_TFAW_MASK 0x001F0000
|
||||
#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
|
||||
#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
#define DDR0_07_AREFRESH_MASK 0x00000001
|
||||
#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_08 0x08
|
||||
#define DDR0_08_WRLAT_MASK 0x07000000
|
||||
#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_08_TCPD_MASK 0x00FF0000
|
||||
#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_08_DQS_N_EN_MASK 0x00000100
|
||||
#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
|
||||
#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_09 0x09
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_09_RTT_0_MASK 0x00030000
|
||||
#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
|
||||
#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
|
||||
#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_10 0x0A
|
||||
#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
|
||||
#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_10_CS_MAP_MASK 0x00000300
|
||||
#define DDR0_10_CS_MAP_NO_MEM 0x00000000
|
||||
#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
|
||||
#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
|
||||
#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
|
||||
#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
|
||||
|
||||
#define DDR0_11 0x0B
|
||||
#define DDR0_11_SREFRESH_MASK 0x01000000
|
||||
#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_11_TXSNR_MASK 0x00FF0000
|
||||
#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_11_TXSR_MASK 0x0000FF00
|
||||
#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
|
||||
#define DDR0_12 0x0C
|
||||
#define DDR0_12_TCKE_MASK 0x0000007
|
||||
#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
|
||||
#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)
|
||||
|
||||
#define DDR0_13 0x0D
|
||||
|
||||
#define DDR0_14 0x0E
|
||||
#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
|
||||
#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_14_REDUC_MASK 0x00010000
|
||||
#define DDR0_14_REDUC_64BITS 0x00000000
|
||||
#define DDR0_14_REDUC_32BITS 0x00010000
|
||||
#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
|
||||
#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
|
||||
#define DDR0_15 0x0F
|
||||
|
||||
#define DDR0_16 0x10
|
||||
|
||||
#define DDR0_17 0x11
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
|
||||
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
|
||||
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
|
||||
#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
|
||||
#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
|
||||
#define DDR0_18 0x12
|
||||
#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_19 0x13
|
||||
#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_20 0x14
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_21 0x15
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_22 0x16
|
||||
/* ECC */
|
||||
#define DDR0_22_CTRL_RAW_MASK 0x03000000
|
||||
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */
|
||||
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/
|
||||
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */
|
||||
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */
|
||||
#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
|
||||
#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
|
||||
|
||||
|
||||
#define DDR0_23 0x17
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
|
||||
#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
|
||||
#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
|
||||
#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_24 0x18
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)
|
||||
|
||||
#define DDR0_25 0x19
|
||||
#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
|
||||
#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||
#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
|
||||
|
||||
#define DDR0_26 0x1A
|
||||
#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
|
||||
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||
#define DDR0_26_TREF_MASK 0x00003FFF
|
||||
#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
|
||||
#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
|
||||
|
||||
#define DDR0_27 0x1B
|
||||
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
|
||||
#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
|
||||
#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
|
||||
#define DDR0_27_TINIT_MASK 0x0000FFFF
|
||||
#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
|
||||
#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
|
||||
|
||||
#define DDR0_28 0x1C
|
||||
#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
|
||||
#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
|
||||
#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
|
||||
#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
|
||||
#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
|
||||
#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
|
||||
|
||||
#define DDR0_29 0x1D
|
||||
|
||||
#define DDR0_30 0x1E
|
||||
|
||||
#define DDR0_31 0x1F
|
||||
#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
|
||||
#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
|
||||
#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
|
||||
|
||||
#define DDR0_32 0x20
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_33 0x21
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_34 0x22
|
||||
#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_35 0x23
|
||||
#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_36 0x24
|
||||
#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_37 0x25
|
||||
#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_38 0x26
|
||||
#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_39 0x27
|
||||
#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_40 0x28
|
||||
#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_41 0x29
|
||||
#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_42 0x2A
|
||||
#define DDR0_42_ADDR_PINS_MASK 0x07000000
|
||||
#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
|
||||
#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
|
||||
#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
|
||||
|
||||
#define DDR0_43 0x2B
|
||||
#define DDR0_43_TWR_MASK 0x07000000
|
||||
#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_43_APREBIT_MASK 0x000F0000
|
||||
#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
|
||||
#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
|
||||
#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
|
||||
#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
|
||||
#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
|
||||
#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
|
||||
#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_44 0x2C
|
||||
#define DDR0_44_TRCD_MASK 0x000000FF
|
||||
#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
|
||||
#endif /* _SPD_SDRAM_DENALI_H_ */
|
||||
|
|
@ -35,9 +35,9 @@ ulong flash_get_size (ulong base, int banknum);
|
|||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
unsigned long sdr0_cust0;
|
||||
unsigned long sdr0_pfc1, sdr0_pfc2;
|
||||
register uint reg;
|
||||
u32 sdr0_cust0;
|
||||
u32 sdr0_pfc1, sdr0_pfc2;
|
||||
u32 reg;
|
||||
|
||||
mtdcr(ebccfga, xbcfg);
|
||||
mtdcr(ebccfgd, 0xb8400000);
|
||||
|
|
@ -142,6 +142,7 @@ int misc_init_r(void)
|
|||
{
|
||||
uint pbcr;
|
||||
int size_val = 0;
|
||||
u32 reg;
|
||||
#ifdef CONFIG_440EPX
|
||||
unsigned long usb2d0cr = 0;
|
||||
unsigned long usb2phy0cr, usb2h0cr = 0;
|
||||
|
|
@ -335,6 +336,14 @@ int misc_init_r(void)
|
|||
}
|
||||
#endif /* CONFIG_440EPX */
|
||||
|
||||
/*
|
||||
* Clear PLB4A0_ACR[WRP]
|
||||
* This fix will make the MAL burst disabling patch for the Linux
|
||||
* EMAC driver obsolete.
|
||||
*/
|
||||
reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
|
||||
mtdcr(plb4_acr, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -31,9 +31,6 @@
|
|||
DECLARE_GLOBAL_DATA_PTR;
|
||||
#endif
|
||||
|
||||
|
||||
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
|
||||
|
||||
#ifdef CFG_INIT_DCACHE_CS
|
||||
# if (CFG_INIT_DCACHE_CS == 0)
|
||||
# define PBxAP pb0ap
|
||||
|
|
|
|||
|
|
@ -2338,7 +2338,7 @@ int nand_scan (struct mtd_info *mtd, int maxchips)
|
|||
mtd->oobblock = 1024 << (extid & 0x3);
|
||||
extid >>= 2;
|
||||
/* Calc oobsize */
|
||||
mtd->oobsize = (8 << (extid & 0x03)) * (mtd->oobblock / 512);
|
||||
mtd->oobsize = (8 << (extid & 0x01)) * (mtd->oobblock / 512);
|
||||
extid >>= 2;
|
||||
/* Calc blocksize. Blocksize is multiples of 64KiB */
|
||||
mtd->erasesize = (64 * 1024) << (extid & 0x03);
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||||
|
|
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|||
|
|
@ -189,6 +189,9 @@
|
|||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MBYTES_SDRAM (256) /* 256MB */
|
||||
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
|
|
|
|||
|
|
@ -887,12 +887,14 @@
|
|||
|
||||
/* PLB4 Arbiter - PowerPC440EP Pass1 */
|
||||
#define PLB4_DCR_BASE 0x080
|
||||
#define plb4_acr (PLB4_DCR_BASE+0x1)
|
||||
#define plb4_revid (PLB4_DCR_BASE+0x2)
|
||||
#define plb4_acr (PLB4_DCR_BASE+0x3)
|
||||
#define plb4_besr (PLB4_DCR_BASE+0x4)
|
||||
#define plb4_bearl (PLB4_DCR_BASE+0x6)
|
||||
#define plb4_bearh (PLB4_DCR_BASE+0x7)
|
||||
|
||||
#define PLB4_ACR_WRP (0x80000000 >> 7)
|
||||
|
||||
/* Nebula PLB4 Arbiter - PowerPC440EP */
|
||||
#define PLB_ARBITER_BASE 0x80
|
||||
|
||||
|
|
@ -3284,26 +3286,26 @@ typedef struct { unsigned long add; /* gpio core base address */
|
|||
/*
|
||||
* Macros for accessing the indirect EBC registers
|
||||
*/
|
||||
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
|
||||
#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
|
||||
#define mtebc(reg, data) { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); }
|
||||
#define mfebc(reg, data) { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); }
|
||||
|
||||
/*
|
||||
* Macros for accessing the indirect SDRAM controller registers
|
||||
*/
|
||||
#define mtsdram(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
|
||||
#define mfsdram(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd)
|
||||
#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); }
|
||||
#define mfsdram(reg, data) { mtdcr(memcfga,reg);data = mfdcr(memcfgd); }
|
||||
|
||||
/*
|
||||
* Macros for accessing the indirect clocking controller registers
|
||||
*/
|
||||
#define mtclk(reg, data) mtdcr(clkcfga,reg);mtdcr(clkcfgd,data)
|
||||
#define mfclk(reg, data) mtdcr(clkcfga,reg);data = mfdcr(clkcfgd)
|
||||
#define mtclk(reg, data) { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); }
|
||||
#define mfclk(reg, data) { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); }
|
||||
|
||||
/*
|
||||
* Macros for accessing the sdr controller registers
|
||||
*/
|
||||
#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
|
||||
#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
|
||||
#define mtsdr(reg, data) { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); }
|
||||
#define mfsdr(reg, data) { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); }
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
|
|
|||
|
|
@ -76,7 +76,9 @@ $(obj)init.S:
|
|||
|
||||
$(obj)sdram.c:
|
||||
@rm -f $(obj)sdram.c
|
||||
@rm -f $(obj)sdram.h
|
||||
ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $(obj)sdram.c
|
||||
ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)sdram.h
|
||||
|
||||
# from nand_spl directory
|
||||
$(obj)nand_boot.c:
|
||||
|
|
|
|||
Loading…
Reference in a new issue