Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-24 21:54:01 +00:00
Code Issues Projects Releases Packages Wiki Activity

clk: renesas: Confirm all clock & reset changes on RZ/G2L

Browse source 
When enabling/disabling a clock or reset signal, confirm that the change
has completed before returning from the function. A somewhat arbitrary
100ms timeout is defined to ensure that the system doesn't lock up in
the case of an error.

Since we need to dynamically determine if we're waiting for a 0 bit or a
1 bit, it's easier to use wait_for_bit_32() than readl_poll_timeout().

This change is needed for reliable initialization of the I2C driver
which is added in a following patch.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Paul Barker 2024-02-27 20:40:28 +00:00 committed by Marek Vasut
parent abd4fb5ac1
commit aecd69879d
1 changed files with 13 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
drivers/clk/renesas/rzg2l-cpg.c
View file

@ -23,10 +23,18 @@
#include <linux/iopoll.h>
#include <reset-uclass.h>
#include <reset.h>
#include <wait_bit.h>
#include "rzg2l-cpg.h"
/*
* Monitor registers for both clock and reset signals are offset by 0x180 from
* the corresponding control registers.
*/
#define CLK_MON_R(reg) (0x180 + (reg))
#define RST_MON_R(reg) (0x180 + (reg))
#define CPG_TIMEOUT_MSEC 100
static ulong rzg2l_cpg_clk_get_rate_by_id(struct udevice *dev, unsigned int id);
static ulong rzg2l_cpg_clk_get_rate_by_name(struct udevice *dev, const char *name);
@ -83,9 +91,9 @@ static int rzg2l_cpg_clk_set(struct clk *clk, bool enable)
value |= BIT(mod_clk->bit);
writel(value, data->base + mod_clk->off);
if (enable && readl_poll_timeout(data->base + CLK_MON_R(mod_clk->off),
value, (value & BIT(mod_clk->bit)),
10)) {
if (enable && wait_for_bit_32(data->base + CLK_MON_R(mod_clk->off),
BIT(mod_clk->bit), enable,
CPG_TIMEOUT_MSEC, false)) {
dev_err(clk->dev, "Timeout\n");
return -ETIMEDOUT;
}
@ -420,7 +428,8 @@ static int rzg2l_cpg_rst_set(struct reset_ctl *reset_ctl, bool asserted)
value |= BIT(rst->bit);
writel(value, data->base + rst->off);
return 0;
return wait_for_bit_32(data->base + RST_MON_R(rst->off), BIT(rst->bit),
asserted, CPG_TIMEOUT_MSEC, false);
}
static int rzg2l_cpg_rst_assert(struct reset_ctl *reset_ctl)