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74xx_7xx: CPCI750: Enable access to PCI function > 0

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The Marvell bridge 64360 supports serveral PCI functions, not only 0. This
patch enables access to those functions.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
This commit is contained in:
Stefan Roese 2009-06-05 05:45:41 +02:00 • committed by Wolfgang Denk
parent e5b563e9ec
commit ae7a2739d7
2 changed files with 22 additions and 8 deletions
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16
board/esd/cpci750/cpci750.c
View file

@ -187,6 +187,7 @@ original ppcboot 1.1.6 source end */
static void gt_pci_config (void) static void gt_pci_config (void)
{ {
unsigned int stat; unsigned int stat;
unsigned int data;
unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */ unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
@ -254,10 +255,15 @@ static void gt_pci_config (void)
/*ronen update the pci internal registers base address.*/ /*ronen update the pci internal registers base address.*/
#ifdef MAP_PCI #ifdef MAP_PCI
for (stat = 0; stat <= PCI_HOST1; stat++) for (stat = 0; stat <= PCI_HOST1; stat++) {
data = pciReadConfigReg(stat,
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
SELF);
data = (data & 0x0f) | CONFIG_SYS_GT_REGS;
pciWriteConfigReg (stat, pciWriteConfigReg (stat,
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
SELF, CONFIG_SYS_GT_REGS); SELF, data);
}
#endif #endif
} }
@ -451,9 +457,13 @@ int misc_init_r ()
void after_reloc (ulong dest_addr, gd_t * gd) void after_reloc (ulong dest_addr, gd_t * gd)
{ {
memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE); memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE,
CONFIG_SYS_BOOT_SIZE);
display_mem_map (); display_mem_map ();
GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
/* now, jump to the main ppcboot board init code */ /* now, jump to the main ppcboot board init code */
board_init_r (gd, dest_addr); board_init_r (gd, dest_addr);
/* NOTREACHED */ /* NOTREACHED */

14
board/esd/cpci750/pci.c
View file

@ -768,11 +768,12 @@ static int gt_read_config_dword (struct pci_controller *hose,
int bus = PCI_BUS (dev); int bus = PCI_BUS (dev);
if ((bus == local_buses[0]) || (bus == local_buses[1])) { if ((bus == local_buses[0]) || (bus == local_buses[1])) {
*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr,
offset | (PCI_FUNC(dev) << 8),
PCI_DEV (dev)); PCI_DEV (dev));
} else { } else {
*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->cfg_addr,
cfg_addr, offset, offset | (PCI_FUNC(dev) << 8),
PCI_DEV (dev), bus); PCI_DEV (dev), bus);
} }
@ -785,13 +786,16 @@ static int gt_write_config_dword (struct pci_controller *hose,
int bus = PCI_BUS (dev); int bus = PCI_BUS (dev);
if ((bus == local_buses[0]) || (bus == local_buses[1])) { if ((bus == local_buses[0]) || (bus == local_buses[1])) {
pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, pciWriteConfigReg ((PCI_HOST) hose->cfg_addr,
offset | (PCI_FUNC(dev) << 8),
PCI_DEV (dev), value); PCI_DEV (dev), value);
} else { } else {
pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
offset, PCI_DEV (dev), bus, offset | (PCI_FUNC(dev) << 8),
PCI_DEV (dev), bus,
value); value);
} }
return 0; return 0;
} }