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clk: mediatek: add CLK_XTAL support for clock driver

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This adds the CLK_XTAL macro/flag to allow modeling clocks which are
directly connected to the xtal clock.

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao 2022-09-09 20:00:07 +08:00 • committed by Tom Rini
parent 570b0840b1
commit ad832b915a
2 changed files with 6 additions and 1 deletions
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4
drivers/clk/mediatek/clk-mtk.c
View file

@ -296,6 +296,7 @@ static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
break;
case CLK_PARENT_XTAL:
default:
rate = priv->tree->xtal_rate;
}
@ -314,6 +315,9 @@ static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off)
rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
priv->parent);
break;
case CLK_PARENT_XTAL:
rate = priv->tree->xtal_rate;
break;
default:
rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
}

3
drivers/clk/mediatek/clk-mtk.h
View file

@ -29,7 +29,8 @@
#define CLK_PARENT_APMIXED BIT(4)
#define CLK_PARENT_TOPCKGEN BIT(5)
#define CLK_PARENT_INFRASYS BIT(6)
#define CLK_PARENT_MASK GENMASK(6, 4)
#define CLK_PARENT_XTAL BIT(7)
#define CLK_PARENT_MASK GENMASK(7, 4)
#define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34