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arm: dts: fsl-ls1088a: syncronise MDIO+PCS U-Boot definitions with Linux

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Synchronise the MDIO controller definitions with Linux, so
the controllers will be usable when passing U-Boot's
control FDT to Linux.

This also adds the PCS (internal controller) definitions
which are not used by U-Boot.

Caveat: The kernel definition uses "fsl,fman-memac-mdio",
as with other members of the Layerscape family, but
U-Boot uses a different driver for the DPAA2
Family devices (LS1088/LS2088/LX2160). So
we use "fsl,ls-mdio" as the first compatible string
for these devices.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
This commit is contained in:
Mathew McBride 2023-04-12 07:38:25 +00:00 committed by Peng Fan
parent 10ff7e6b04
commit ad558eff32
2 changed files with 112 additions and 16 deletions
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12
arch/arm/dts/fsl-ls1088a-u-boot.dtsi
View file

@ -17,6 +17,18 @@
bootph-all; bootph-all;
}; };
/* MDIO controllers - U-Boot uses a different
* driver for the DPAA2 (LS/LX2) family,
* so must match fsl,ls-mdio first.
*/
&emdio1 {
compatible = "fsl,ls-mdio", "fsl,fman-memac-mdio";
};
&emdio2 {
compatible = "fsl,ls-mdio", "fsl,fman-memac-mdio";
};
&pcie1 { &pcie1 {
status = "okay"; status = "okay";
}; };

116
arch/arm/dts/fsl-ls1088a.dtsi
View file

@ -477,6 +477,106 @@
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
}; };
emdio1: mdio@8b96000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8b96000 0x0 0x1000>;
little-endian;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <2500000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
status = "disabled";
};
emdio2: mdio@8b97000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8b97000 0x0 0x1000>;
little-endian;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <2500000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
status = "disabled";
};
pcs_mdio1: mdio@8c07000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c07000 0x0 0x1000>;
little-endian;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pcs1: ethernet-phy@0 {
reg = <0>;
};
};
pcs_mdio2: mdio@8c0b000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c0b000 0x0 0x1000>;
little-endian;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pcs2: ethernet-phy@0 {
reg = <0>;
};
};
pcs_mdio3: mdio@8c0f000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c0f000 0x0 0x1000>;
little-endian;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pcs3_0: ethernet-phy@0 {
reg = <0>;
};
pcs3_1: ethernet-phy@1 {
reg = <1>;
};
pcs3_2: ethernet-phy@2 {
reg = <2>;
};
pcs3_3: ethernet-phy@3 {
reg = <3>;
};
};
pcs_mdio7: mdio@8c1f000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c1f000 0x0 0x1000>;
little-endian;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pcs7_0: ethernet-phy@0 {
reg = <0>;
};
pcs7_1: ethernet-phy@1 {
reg = <1>;
};
pcs7_2: ethernet-phy@2 {
reg = <2>;
};
pcs7_3: ethernet-phy@3 {
reg = <3>;
};
};
}; };
dspi: dspi@2100000 { dspi: dspi@2100000 {
@ -645,20 +745,4 @@
}; };
}; };
}; };
emdio1: mdio@8B96000 {
compatible = "fsl,ls-mdio";
reg = <0x0 0x8B96000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
emdio2: mdio@8B97000 {
compatible = "fsl,ls-mdio";
reg = <0x0 0x8B97000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
}; };