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https://github.com/AsahiLinux/u-boot
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rockchip: px30: sync the main px30 dtsi from mainline
There have been multiple peripherals added to the main px30 dtsi in the Linux kernel since its addition to u-boot. So to make it easier to sync board devicetrees, update the core dtsi from Linux. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Heiko Stuebner
Kever Yang
parent
ab800e5a6f
commit
ac3d121c35
1 changed files with 171 additions and 11 deletions
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@ -10,6 +10,7 @@
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/power/px30-power.h>
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#include <dt-bindings/soc/rockchip,boot-mode.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "rockchip,px30";
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@ -113,16 +114,11 @@
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compatible = "operating-points-v2";
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opp-shared;
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <950000 950000 1350000>;
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clock-latency-ns = <40000>;
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opp-suspend;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <950000 950000 1350000>;
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clock-latency-ns = <40000>;
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opp-suspend;
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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@ -186,6 +182,55 @@
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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thermal_zones: thermal-zones {
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soc_thermal: soc-thermal {
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polling-delay-passive = <20>;
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polling-delay = <1000>;
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sustainable-power = <750>;
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thermal-sensors = <&tsadc 0>;
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trips {
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threshold: trip-point-0 {
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temperature = <70000>;
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hysteresis = <2000>;
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type = "passive";
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};
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target: trip-point-1 {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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soc_crit: soc-crit {
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temperature = <115000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&target>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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contribution = <4096>;
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};
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map1 {
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trip = <&target>;
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cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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contribution = <4096>;
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};
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};
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};
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gpu_thermal: gpu-thermal {
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polling-delay-passive = <100>; /* milliseconds */
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polling-delay = <1000>; /* milliseconds */
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thermal-sensors = <&tsadc 1>;
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};
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};
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xin24m: xin24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@ -370,6 +415,36 @@
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compatible = "rockchip,px30-io-voltage-domain";
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status = "disabled";
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};
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lvds: lvds {
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compatible = "rockchip,px30-lvds";
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phys = <&dsi_dphy>;
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phy-names = "dphy";
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rockchip,grf = <&grf>;
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rockchip,output = "lvds";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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lvds_vopb_in: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vopb_out_lvds>;
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};
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lvds_vopl_in: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vopl_out_lvds>;
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};
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};
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};
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};
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};
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uart1: serial@ff158000 {
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@ -650,6 +725,26 @@
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};
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};
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tsadc: tsadc@ff280000 {
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compatible = "rockchip,px30-tsadc";
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reg = <0x0 0xff280000 0x0 0x100>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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assigned-clocks = <&cru SCLK_TSADC>;
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assigned-clock-rates = <50000>;
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clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
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clock-names = "tsadc", "apb_pclk";
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resets = <&cru SRST_TSADC>;
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reset-names = "tsadc-apb";
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rockchip,grf = <&grf>;
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rockchip,hw-tshut-temp = <120000>;
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pinctrl-names = "init", "default", "sleep";
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pinctrl-0 = <&tsadc_otp_gpio>;
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pinctrl-1 = <&tsadc_otp_out>;
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pinctrl-2 = <&tsadc_otp_gpio>;
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#thermal-sensor-cells = <1>;
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status = "disabled";
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};
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saradc: saradc@ff288000 {
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compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
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reg = <0x0 0xff288000 0x0 0x100>;
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@ -706,12 +801,48 @@
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#reset-cells = <1>;
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};
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usb2phy_grf: syscon@ff2c0000 {
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compatible = "rockchip,px30-usb2phy-grf", "syscon",
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"simple-mfd";
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reg = <0x0 0xff2c0000 0x0 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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u2phy: usb2-phy@100 {
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compatible = "rockchip,px30-usb2phy";
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reg = <0x100 0x20>;
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clocks = <&pmucru SCLK_USBPHY_REF>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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assigned-clocks = <&cru USB480M>;
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assigned-clock-parents = <&u2phy>;
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clock-output-names = "usb480m_phy";
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status = "disabled";
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u2phy_host: host-port {
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#phy-cells = <0>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "linestate";
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status = "disabled";
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};
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u2phy_otg: otg-port {
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#phy-cells = <0>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "otg-bvalid", "otg-id",
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"linestate";
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status = "disabled";
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};
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};
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};
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dsi_dphy: phy@ff2e0000 {
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compatible = "rockchip,px30-dsi-dphy";
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reg = <0x0 0xff2e0000 0x0 0x10000>;
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clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
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clock-names = "ref", "pclk";
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#clock-cells = <0>;
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resets = <&cru SRST_MIPIDSIPHY_P>;
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reset-names = "apb";
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#phy-cells = <0>;
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@ -731,6 +862,8 @@
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g-rx-fifo-size = <280>;
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g-tx-fifo-size = <256 128 128 64 32 16>;
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g-use-dma;
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phys = <&u2phy_otg>;
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phy-names = "usb2-phy";
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power-domains = <&power PX30_PD_USB>;
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status = "disabled";
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};
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@ -741,6 +874,8 @@
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST>;
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clock-names = "usbhost";
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phys = <&u2phy_host>;
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phy-names = "usb";
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power-domains = <&power PX30_PD_USB>;
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status = "disabled";
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};
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@ -751,6 +886,8 @@
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST>;
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clock-names = "usbhost";
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phys = <&u2phy_host>;
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phy-names = "usb";
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power-domains = <&power PX30_PD_USB>;
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status = "disabled";
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};
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@ -823,17 +960,30 @@
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status = "disabled";
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};
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gpu: gpu@ff400000 {
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compatible = "rockchip,px30-mali", "arm,mali-bifrost";
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reg = <0x0 0xff400000 0x0 0x4000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "job", "mmu", "gpu";
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clocks = <&cru SCLK_GPU>;
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#cooling-cells = <2>;
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power-domains = <&power PX30_PD_GPU>;
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status = "disabled";
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};
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dsi: dsi@ff450000 {
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compatible = "rockchip,px30-mipi-dsi";
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reg = <0x0 0xff450000 0x0 0x10000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_MIPI_DSI>, <&dsi_dphy>;
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clock-names = "pclk", "pll";
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resets = <&cru SRST_MIPIDSI_HOST_P>;
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reset-names = "apb";
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clocks = <&cru PCLK_MIPI_DSI>;
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clock-names = "pclk";
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phys = <&dsi_dphy>;
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phy-names = "dphy";
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power-domains = <&power PX30_PD_VO>;
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resets = <&cru SRST_MIPIDSI_HOST_P>;
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reset-names = "apb";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -883,6 +1033,11 @@
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reg = <0>;
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remote-endpoint = <&dsi_in_vopb>;
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};
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vopb_out_lvds: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&lvds_vopb_in>;
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};
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};
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};
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@ -920,6 +1075,11 @@
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reg = <0>;
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remote-endpoint = <&dsi_in_vopl>;
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};
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vopl_out_lvds: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&lvds_vopl_in>;
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};
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};
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};
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