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MIPS: refactor cache loops to a macro

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Reduce duplication by performing loops through cache tags using an
assembler macro.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Paul Burton 2015-01-29 01:28:00 +00:00 committed by Daniel Schwierzeck
parent 536cb7ce1a
commit ac22feca11
1 changed files with 13 additions and 17 deletions
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30
arch/mips/lib/cache_init.S
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@ -47,28 +47,28 @@
#endif #endif
.endm .endm
.macro cache_loop curr, end, line_sz, op
10: cache \op, 0(\curr)
PTR_ADDU \curr, \curr, \line_sz
bne \curr, \end, 10b
.endm
/* /*
* mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
*/ */
LEAF(mips_init_icache) LEAF(mips_init_icache)
blez a1, 9f blez a1, 9f
mtc0 zero, CP0_TAGLO mtc0 zero, CP0_TAGLO
/* clear tag to invalidate */
PTR_LI t0, INDEX_BASE PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1 PTR_ADDU t1, t0, a1
1: cache INDEX_STORE_TAG_I, 0(t0) /* clear tag to invalidate */
PTR_ADDU t0, a2 cache_loop t0, t1, a2, INDEX_STORE_TAG_I
bne t0, t1, 1b
/* fill once, so data field parity is correct */ /* fill once, so data field parity is correct */
PTR_LI t0, INDEX_BASE PTR_LI t0, INDEX_BASE
2: cache FILL, 0(t0) cache_loop t0, t1, a2, FILL
PTR_ADDU t0, a2
bne t0, t1, 2b
/* invalidate again - prudent but not strictly neccessary */ /* invalidate again - prudent but not strictly neccessary */
PTR_LI t0, INDEX_BASE PTR_LI t0, INDEX_BASE
1: cache INDEX_STORE_TAG_I, 0(t0) cache_loop t0, t1, a2, INDEX_STORE_TAG_I
PTR_ADDU t0, a2
bne t0, t1, 1b
9: jr ra 9: jr ra
END(mips_init_icache) END(mips_init_icache)
@ -78,12 +78,10 @@ LEAF(mips_init_icache)
LEAF(mips_init_dcache) LEAF(mips_init_dcache)
blez a1, 9f blez a1, 9f
mtc0 zero, CP0_TAGLO mtc0 zero, CP0_TAGLO
/* clear all tags */
PTR_LI t0, INDEX_BASE PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1 PTR_ADDU t1, t0, a1
1: cache INDEX_STORE_TAG_D, 0(t0) /* clear all tags */
PTR_ADDU t0, a2 cache_loop t0, t1, a2, INDEX_STORE_TAG_D
bne t0, t1, 1b
/* load from each line (in cached space) */ /* load from each line (in cached space) */
PTR_LI t0, INDEX_BASE PTR_LI t0, INDEX_BASE
2: LONG_L zero, 0(t0) 2: LONG_L zero, 0(t0)
@ -91,9 +89,7 @@ LEAF(mips_init_dcache)
bne t0, t1, 2b bne t0, t1, 2b
/* clear all tags */ /* clear all tags */
PTR_LI t0, INDEX_BASE PTR_LI t0, INDEX_BASE
1: cache INDEX_STORE_TAG_D, 0(t0) cache_loop t0, t1, a2, INDEX_STORE_TAG_D
PTR_ADDU t0, a2
bne t0, t1, 1b
9: jr ra 9: jr ra
END(mips_init_dcache) END(mips_init_dcache)