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Fixup bug in PMIC TPS65217 register address definition

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The addresses of the registers in TI TPS65217 are not continuous.
     There is a gap between ENABLE(0x16) and DEFUVLO(0x18). No 0x17
     register available.

     Fixup the enum values by adding a 'reserved' placeholder to correct
     the addresses higher than 0x17.

     Series-to: Heiko Schocher <hs@denx.de>

Signed-off-by: Brock Zheng Techyauld Ltd <yzheng@techyauld.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
This commit is contained in:
Brock Zheng Techyauld Ltd 2017-06-06 09:06:21 +08:00 committed by Jaehoon Chung
parent 2dd9dc02a3
commit abf54bf978
1 changed files with 1 additions and 0 deletions
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include/power/tps65217.h
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@ -38,6 +38,7 @@ enum {
TPS65217_DEFLS1, TPS65217_DEFLS1,
TPS65217_DEFLS2, TPS65217_DEFLS2,
TPS65217_ENABLE, TPS65217_ENABLE,
TPS65217_RESERVED0, /* no 0x17 register available */
TPS65217_DEFUVLO, TPS65217_DEFUVLO,
TPS65217_SEQ1, TPS65217_SEQ1,
TPS65217_SEQ2, TPS65217_SEQ2,